Initialize interrupt priority to 0 on all sources.

Without this hardware raises an interrupt regardless of any
pending bits set.

This fixes operation on RocketChip and derivatives (e.g. lowRISC).

Approved by:	re (kib)
Sponsored by:	DARPA, AFRL

sys/riscv/riscv/plic.c

@@ -218,6 +218,7 @@ plic_attach(device_t dev)
 		if (error != 0)
 			return (error);
 
+		WR4(sc, PLIC_PRIORITY(irq), 0);
 		WR4(sc, PLIC_ENABLE(irq, cpu), 0);
 	}
 	WR4(sc, PLIC_THRESHOLD(cpu), 0);