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powerpc/booke: Handle misaligned floating point loads/stores as on AIM
Misaligned floating point loads and stores are already handled for AIM, but use the DSISR to obtain the necessary data. Book-E does not have the DSISR, so these fixups are not performed, leading to a SIGBUS on misaligned FP loads or stores. Obtain the necessary data on the Book-E side, similar to how is done for SPE. MFC after: 1 week
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=349402
@ -130,7 +130,7 @@
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/* Macros to extract register information */
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#define EXC_ALI_RST(dsisr) ((dsisr >> 5) & 0x1f) /* source or target */
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#define EXC_ALI_RA(dsisr) (dsisr & 0x1f)
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#define EXC_ALI_SPE_REG(instr) ((instr >> 21) & 0x1f)
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#define EXC_ALI_INST_RST(instr) ((instr >> 21) & 0x1f)
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/*
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* SRR1 bits for program exception traps. These identify what caused
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@ -788,7 +788,7 @@ static int
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fix_unaligned(struct thread *td, struct trapframe *frame)
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{
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struct thread *fputhread;
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#ifdef __SPE__
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#ifdef BOOKE
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uint32_t inst;
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#endif
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int indicator, reg;
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@ -799,7 +799,7 @@ fix_unaligned(struct thread *td, struct trapframe *frame)
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if (indicator & ESR_SPE) {
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if (copyin((void *)frame->srr0, &inst, sizeof(inst)) != 0)
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return (-1);
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reg = EXC_ALI_SPE_REG(inst);
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reg = EXC_ALI_INST_RST(inst);
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fpr = (double *)td->td_pcb->pcb_vec.vr[reg];
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fputhread = PCPU_GET(vecthread);
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@ -828,13 +828,23 @@ fix_unaligned(struct thread *td, struct trapframe *frame)
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}
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return (0);
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}
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#else
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#ifdef BOOKE
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indicator = (frame->cpu.booke.esr & ESR_ST) ? EXC_ALI_STFD : EXC_ALI_LFD;
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#else
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indicator = EXC_ALI_OPCODE_INDICATOR(frame->cpu.aim.dsisr);
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#endif
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switch (indicator) {
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case EXC_ALI_LFD:
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case EXC_ALI_STFD:
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#ifdef BOOKE
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if (copyin((void *)frame->srr0, &inst, sizeof(inst)) != 0)
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return (-1);
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reg = EXC_ALI_INST_RST(inst);
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#else
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reg = EXC_ALI_RST(frame->cpu.aim.dsisr);
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#endif
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fpr = &td->td_pcb->pcb_fpu.fpr[reg].fpr;
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fputhread = PCPU_GET(fputhread);
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