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libpmc: Import AMD Zen 4 PMU events

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MFC after:	1 week
This commit is contained in:
Alexander Motin 2024-04-20 11:54:04 -04:00
parent dfa39133b3
commit 278d695094
11 changed files with 3871 additions and 1 deletions
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82
lib/libpmc/pmu-events/arch/x86/amdzen4/branch.json Normal file
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[
{
"EventName": "bp_l2_btb_correct",
"EventCode": "0x8b",
"BriefDescription": "L2 branch prediction overrides existing prediction (speculative)."
},
{
"EventName": "bp_dyn_ind_pred",
"EventCode": "0x8e",
"BriefDescription": "Dynamic indirect predictions (branch used the indirect predictor to make a prediction)."
},
{
"EventName": "bp_de_redirect",
"EventCode": "0x91",
"BriefDescription": "Instruction decoder corrects the predicted target and resteers the branch predictor."
},
{
"EventName": "ex_ret_brn",
"EventCode": "0xc2",
"BriefDescription": "Retired branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
},
{
"EventName": "ex_ret_brn_misp",
"EventCode": "0xc3",
"BriefDescription": "Retired branch instructions mispredicted."
},
{
"EventName": "ex_ret_brn_tkn",
"EventCode": "0xc4",
"BriefDescription": "Retired taken branch instructions (all types of architectural control flow changes, including exceptions and interrupts)."
},
{
"EventName": "ex_ret_brn_tkn_misp",
"EventCode": "0xc5",
"BriefDescription": "Retired taken branch instructions mispredicted."
},
{
"EventName": "ex_ret_brn_far",
"EventCode": "0xc6",
"BriefDescription": "Retired far control transfers (far call/jump/return, IRET, SYSCALL and SYSRET, plus exceptions and interrupts). Far control transfers are not subject to branch prediction."
},
{
"EventName": "ex_ret_near_ret",
"EventCode": "0xc8",
"BriefDescription": "Retired near returns (RET or RET Iw)."
},
{
"EventName": "ex_ret_near_ret_mispred",
"EventCode": "0xc9",
"BriefDescription": "Retired near returns mispredicted. Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
},
{
"EventName": "ex_ret_brn_ind_misp",
"EventCode": "0xca",
"BriefDescription": "Retired indirect branch instructions mispredicted (only EX mispredicts). Each misprediction incurs the same penalty as a mispredicted conditional branch instruction."
},
{
"EventName": "ex_ret_ind_brch_instr",
"EventCode": "0xcc",
"BriefDescription": "Retired indirect branch instructions."
},
{
"EventName": "ex_ret_cond",
"EventCode": "0xd1",
"BriefDescription": "Retired conditional branch instructions."
},
{
"EventName": "ex_ret_msprd_brnch_instr_dir_msmtch",
"EventCode": "0x1c7",
"BriefDescription": "Retired branch instructions mispredicted due to direction mismatch."
},
{
"EventName": "ex_ret_uncond_brnch_instr_mispred",
"EventCode": "0x1c8",
"BriefDescription": "Retired unconditional indirect branch instructions mispredicted."
},
{
"EventName": "ex_ret_uncond_brnch_instr",
"EventCode": "0x1c9",
"BriefDescription": "Retired unconditional branch instructions."
}
]

828
lib/libpmc/pmu-events/arch/x86/amdzen4/cache.json Normal file
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[
{
"EventName": "ls_mab_alloc.load_store_allocations",
"EventCode": "0x41",
"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocations.",
"UMask": "0x3f"
},
{
"EventName": "ls_mab_alloc.hardware_prefetcher_allocations",
"EventCode": "0x41",
"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocations.",
"UMask": "0x40"
},
{
"EventName": "ls_mab_alloc.all_allocations",
"EventCode": "0x41",
"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocations.",
"UMask": "0x7f"
},
{
"EventName": "ls_dmnd_fills_from_sys.local_l2",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_dmnd_fills_from_sys.local_ccx",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_dmnd_fills_from_sys.near_cache",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_dmnd_fills_from_sys.dram_io_near",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_dmnd_fills_from_sys.far_cache",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_dmnd_fills_from_sys.dram_io_far",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_dmnd_fills_from_sys.alternate_memories",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_dmnd_fills_from_sys.all",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from all types of data sources.",
"UMask": "0xff"
},
{
"EventName": "ls_any_fills_from_sys.local_l2",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_any_fills_from_sys.local_ccx",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_any_fills_from_sys.local_all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from local L2 cache or L3 cache or different L2 cache in the same CCX.",
"UMask": "0x03"
},
{
"EventName": "ls_any_fills_from_sys.near_cache",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from cache of another CCX when the address was in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_any_fills_from_sys.dram_io_near",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_any_fills_from_sys.far_cache",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from cache of another CCX when the address was in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_any_fills_from_sys.remote_cache",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from cache of another CCX when the address was in the same or a different NUMA node.",
"UMask": "0x14"
},
{
"EventName": "ls_any_fills_from_sys.dram_io_far",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_any_fills_from_sys.dram_io_all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket).",
"UMask": "0x48"
},
{
"EventName": "ls_any_fills_from_sys.far_all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket).",
"UMask": "0x50"
},
{
"EventName": "ls_any_fills_from_sys.all_dram_io",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket).",
"UMask": "0x48"
},
{
"EventName": "ls_any_fills_from_sys.alternate_memories",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_any_fills_from_sys.all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from all types of data sources.",
"UMask": "0xff"
},
{
"EventName": "ls_pref_instr_disp.prefetch",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchT0 (move data to all cache levels), T1 (move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2).",
"UMask": "0x01"
},
{
"EventName": "ls_pref_instr_disp.prefetch_w",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mark it modifiable).",
"UMask": "0x02"
},
{
"EventName": "ls_pref_instr_disp.prefetch_nta",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access).",
"UMask": "0x04"
},
{
"EventName": "ls_pref_instr_disp.all",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of all types.",
"UMask": "0x07"
},
{
"EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
"EventCode": "0x52",
"BriefDescription": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hit.",
"UMask": "0x01"
},
{
"EventName": "ls_inef_sw_pref.mab_mch_cnt",
"EventCode": "0x52",
"BriefDescription": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a match on an already allocated Miss Address Buffer (MAB).",
"UMask": "0x02"
},
{
"EventName": "ls_inef_sw_pref.all",
"EventCode": "0x52",
"BriefDescript6ion": "Software prefetches that did not fetch data outside of the processor core for any reason.",
"UMask": "0x03"
},
{
"EventName": "ls_sw_pf_dc_fills.local_l2",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_sw_pf_dc_fills.local_ccx",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_sw_pf_dc_fills.near_cache",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from cache of another CCX in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_sw_pf_dc_fills.dram_io_near",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_sw_pf_dc_fills.far_cache",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from cache of another CCX in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_sw_pf_dc_fills.dram_io_far",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_sw_pf_dc_fills.alternate_memories",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_sw_pf_dc_fills.all",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from all types of data sources.",
"UMask": "0xdf"
},
{
"EventName": "ls_hw_pf_dc_fills.local_l2",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_hw_pf_dc_fills.local_ccx",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_hw_pf_dc_fills.near_cache",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address was in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_hw_pf_dc_fills.dram_io_near",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_hw_pf_dc_fills.far_cache",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address was in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_hw_pf_dc_fills.dram_io_far",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_hw_pf_dc_fills.alternate_memories",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_hw_pf_dc_fills.all",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from all types of data sources.",
"UMask": "0xdf"
},
{
"EventName": "ls_alloc_mab_count",
"EventCode": "0x5f",
"BriefDescription": "In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations each cycle."
},
{
"EventName": "l2_request_g1.group2",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests of non-cacheable type (non-cached data and instructions reads, self-modifying code checks).",
"UMask": "0x01"
},
{
"EventName": "l2_request_g1.l2_hw_pf",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: from hardware prefetchers to prefetch directly into L2 (hit or miss).",
"UMask": "0x02"
},
{
"EventName": "l2_request_g1.prefetch_l2_cmd",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: prefetch directly into L2.",
"UMask": "0x04"
},
{
"EventName": "l2_request_g1.change_to_x",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: data cache state change to writable, check L2 for current state.",
"UMask": "0x08"
},
{
"EventName": "l2_request_g1.cacheable_ic_read",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: instruction cache reads.",
"UMask": "0x10"
},
{
"EventName": "l2_request_g1.ls_rd_blk_c_s",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: data cache shared reads.",
"UMask": "0x20"
},
{
"EventName": "l2_request_g1.rd_blk_x",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: data cache stores.",
"UMask": "0x40"
},
{
"EventName": "l2_request_g1.rd_blk_l",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests: data cache reads including hardware and software prefetch.",
"UMask": "0x80"
},
{
"EventName": "l2_request_g1.all_dc",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests of common types from L1 data cache (including prefetches).",
"UMask": "0xe8"
},
{
"EventName": "l2_request_g1.all_no_prefetch",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests of common types not including prefetches.",
"UMask": "0xf9"
},
{
"EventName": "l2_request_g1.all",
"EventCode": "0x60",
"BriefDescription": "L2 cache requests of all types.",
"UMask": "0xff"
},
{
"EventName": "l2_cache_req_stat.ic_fill_miss",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache request miss in L2.",
"UMask": "0x01"
},
{
"EventName": "l2_cache_req_stat.ic_fill_hit_s",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit non-modifiable line in L2.",
"UMask": "0x02"
},
{
"EventName": "l2_cache_req_stat.ic_fill_hit_x",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: instruction cache hit modifiable line in L2.",
"UMask": "0x04"
},
{
"EventName": "l2_cache_req_stat.ic_hit_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache hits.",
"UMask": "0x06"
},
{
"EventName": "l2_cache_req_stat.ic_access_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for instruction cache access.",
"UMask": "0x07"
},
{
"EventName": "l2_cache_req_stat.ls_rd_blk_c",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache request miss in L2.",
"UMask": "0x08"
},
{
"EventName": "l2_cache_req_stat.ic_dc_miss_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache misses.",
"UMask": "0x09"
},
{
"EventName": "l2_cache_req_stat.ls_rd_blk_x",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache store or state change hit in L2.",
"UMask": "0x10"
},
{
"EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_s",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit non-modifiable line in L2.",
"UMask": "0x20"
},
{
"EventName": "l2_cache_req_stat.ls_rd_blk_l_hit_x",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache read hit modifiable line in L2.",
"UMask": "0x40"
},
{
"EventName": "l2_cache_req_stat.ls_rd_blk_cs",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) with status: data cache shared read hit in L2.",
"UMask": "0x80"
},
{
"EventName": "l2_cache_req_stat.dc_hit_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache hits.",
"UMask": "0xf0"
},
{
"EventName": "l2_cache_req_stat.ic_dc_hit_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache hits.",
"UMask": "0xf6"
},
{
"EventName": "l2_cache_req_stat.dc_access_in_l2",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data cache access.",
"UMask": "0xf8"
},
{
"EventName": "l2_cache_req_stat.all",
"EventCode": "0x64",
"BriefDescription": "Core to L2 cache requests (not including L2 prefetch) for data and instruction cache access.",
"UMask": "0xff"
},
{
"EventName": "l2_pf_hit_l2.l2_stream",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stream (fetch additional sequential lines into L2 cache).",
"UMask": "0x01"
},
{
"EventName": "l2_pf_hit_l2.l2_next_line",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2NextLine (fetch the next line into L2 cache).",
"UMask": "0x02"
},
{
"EventName": "l2_pf_hit_l2.l2_up_down",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses).",
"UMask": "0x04"
},
{
"EventName": "l2_pf_hit_l2.l2_burst",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache).",
"UMask": "0x08"
},
{
"EventName": "l2_pf_hit_l2.l2_stride",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L2Stride (fetch additional lines into L2 cache when each access is at a constant distance from the previous).",
"UMask": "0x10"
},
{
"EventName": "l2_pf_hit_l2.l1_stream",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stream (fetch additional sequential lines into L1 cache).",
"UMask": "0x20"
},
{
"EventName": "l2_pf_hit_l2.l1_stride",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous).",
"UMask": "0x40"
},
{
"EventName": "l2_pf_hit_l2.l1_region",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region).",
"UMask": "0x80"
},
{
"EventName": "l2_pf_hit_l2.all",
"EventCode": "0x70",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which hit in the L2 cache of all types.",
"UMask": "0xff"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l2_stream",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stream (fetch additional sequential lines into L2 cache).",
"UMask": "0x01"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l2_next_line",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2NextLine (fetch the next line into L2 cache).",
"UMask": "0x02"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l2_up_down",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses).",
"UMask": "0x04"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l2_burst",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Burst (aggressively fetch additional sequential lines into L2 cache).",
"UMask": "0x08"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l2_stride",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous).",
"UMask": "0x10"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l1_stream",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stream (fetch additional sequential lines into L1 cache).",
"UMask": "0x20"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l1_stride",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous).",
"UMask": "0x40"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.l1_region",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region).",
"UMask": "0x80"
},
{
"EventName": "l2_pf_miss_l2_hit_l3.all",
"EventCode": "0x71",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 cache and hit in the L3 cache cache of all types.",
"UMask": "0xff"
},
{
"EventName": "l2_pf_miss_l2_l3.l2_stream",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stream (fetch additional sequential lines into L2 cache).",
"UMask": "0x01"
},
{
"EventName": "l2_pf_miss_l2_l3.l2_next_line",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2NextLine (fetch the next line into L2 cache).",
"UMask": "0x02"
},
{
"EventName": "l2_pf_miss_l2_l3.l2_up_down",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2UpDown (fetch the next or previous line into L2 cache for all memory accesses).",
"UMask": "0x04"
},
{
"EventName": "l2_pf_miss_l2_l3.l2_burst",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Burst (aggressively fetch additional sequential lines into L2 cache).",
"UMask": "0x08"
},
{
"EventName": "l2_pf_miss_l2_l3.l2_stride",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L2Stride (fetch additional lines into L2 cache when each access is a constant distance from the previous).",
"UMask": "0x10"
},
{
"EventName": "l2_pf_miss_l2_l3.l1_stream",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stream (fetch additional sequential lines into L1 cache).",
"UMask": "0x20"
},
{
"EventName": "l2_pf_miss_l2_l3.l1_stride",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Stride (fetch additional lines into L1 cache when each access is a constant distance from the previous).",
"UMask": "0x40"
},
{
"EventName": "l2_pf_miss_l2_l3.l1_region",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of type L1Region (fetch additional lines into L1 cache when the data access for a given instruction tends to be followed by a consistent pattern of other accesses within a localized region).",
"UMask": "0x80"
},
{
"EventName": "l2_pf_miss_l2_l3.all",
"EventCode": "0x72",
"BriefDescription": "L2 prefetches accepted by the L2 pipeline which miss the L2 and the L3 caches of all types.",
"UMask": "0xff"
},
{
"EventName": "ic_cache_fill_l2",
"EventCode": "0x82",
"BriefDescription": "Instruction cache lines (64 bytes) fulfilled from the L2 cache."
},
{
"EventName": "ic_cache_fill_sys",
"EventCode": "0x83",
"BriefDescription": "Instruction cache lines (64 bytes) fulfilled from system memory or another cache."
},
{
"EventName": "ic_tag_hit_miss.instruction_cache_hit",
"EventCode": "0x18e",
"BriefDescription": "Instruction cache hits.",
"UMask": "0x07"
},
{
"EventName": "ic_tag_hit_miss.instruction_cache_miss",
"EventCode": "0x18e",
"BriefDescription": "Instruction cache misses.",
"UMask": "0x18"
},
{
"EventName": "ic_tag_hit_miss.all_instruction_cache_accesses",
"EventCode": "0x18e",
"BriefDescription": "Instruction cache accesses of all types.",
"UMask": "0x1f"
},
{
"EventName": "op_cache_hit_miss.op_cache_hit",
"EventCode": "0x28f",
"BriefDescription": "Op cache hits.",
"UMask": "0x03"
},
{
"EventName": "op_cache_hit_miss.op_cache_miss",
"EventCode": "0x28f",
"BriefDescription": "Op cache misses.",
"UMask": "0x04"
},
{
"EventName": "op_cache_hit_miss.all_op_cache_accesses",
"EventCode": "0x28f",
"BriefDescription": "Op cache accesses of all types.",
"UMask": "0x07"
},
{
"EventName": "l3_lookup_state.l3_miss",
"EventCode": "0x04",
"BriefDescription": "L3 cache misses.",
"UMask": "0x01",
"Unit": "L3PMC"
},
{
"EventName": "l3_lookup_state.l3_hit",
"EventCode": "0x04",
"BriefDescription": "L3 cache hits.",
"UMask": "0xfe",
"Unit": "L3PMC"
},
{
"EventName": "l3_lookup_state.all_coherent_accesses_to_l3",
"EventCode": "0x04",
"BriefDescription": "L3 cache requests for all coherent accesses.",
"UMask": "0xff",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.dram_near",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from DRAM in the same NUMA node.",
"UMask": "0x01",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.dram_far",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from DRAM in a different NUMA node.",
"UMask": "0x02",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.near_cache",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node.",
"UMask": "0x04",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.far_cache",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node.",
"UMask": "0x08",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.ext_near",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node.",
"UMask": "0x10",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.ext_far",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node.",
"UMask": "0x20",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency.all",
"EventCode": "0xac",
"BriefDescription": "Average sampled latency from all data sources.",
"UMask": "0x3f",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.dram_near",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from DRAM in the same NUMA node.",
"UMask": "0x01",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.dram_far",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from DRAM in a different NUMA node.",
"UMask": "0x02",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.near_cache",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node.",
"UMask": "0x04",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.far_cache",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node.",
"UMask": "0x08",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.ext_near",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node.",
"UMask": "0x10",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.ext_far",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node.",
"UMask": "0x20",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
},
{
"EventName": "l3_xi_sampled_latency_requests.all",
"EventCode": "0xad",
"BriefDescription": "L3 cache fill requests sourced from all data sources.",
"UMask": "0x3f",
"EnAllCores": "0x1",
"EnAllSlices": "0x1",
"SliceId": "0x3",
"ThreadMask": "0x3",
"Unit": "L3PMC"
}
]

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[
{
"EventName": "ls_locks.bus_lock",
"EventCode": "0x25",
"BriefDescription": "Retired Lock instructions which caused a bus lock.",
"UMask": "0x01"
},
{
"EventName": "ls_ret_cl_flush",
"EventCode": "0x26",
"BriefDescription": "Retired CLFLUSH instructions."
},
{
"EventName": "ls_ret_cpuid",
"EventCode": "0x27",
"BriefDescription": "Retired CPUID instructions."
},
{
"EventName": "ls_smi_rx",
"EventCode": "0x2b",
"BriefDescription": "SMIs received."
},
{
"EventName": "ls_int_taken",
"EventCode": "0x2c",
"BriefDescription": "Interrupts taken."
},
{
"EventName": "ls_not_halted_cyc",
"EventCode": "0x76",
"BriefDescription": "Core cycles not in halt."
},
{
"EventName": "ex_ret_instr",
"EventCode": "0xc0",
"BriefDescription": "Retired instructions."
},
{
"EventName": "ex_ret_ops",
"EventCode": "0xc1",
"BriefDescription": "Retired macro-ops."
},
{
"EventName": "ex_div_busy",
"EventCode": "0xd3",
"BriefDescription": "Number of cycles the divider is busy."
},
{
"EventName": "ex_div_count",
"EventCode": "0xd4",
"BriefDescription": "Divide ops executed."
},
{
"EventName": "ex_no_retire.empty",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire due to the lack of valid ops in the retire queue (may be caused by front-end bottlenecks or pipeline redirects).",
"UMask": "0x01"
},
{
"EventName": "ex_no_retire.not_complete",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire while the oldest op is waiting to be executed.",
"UMask": "0x02"
},
{
"EventName": "ex_no_retire.other",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire caused by other reasons (retire breaks, traps, faults, etc.).",
"UMask": "0x08"
},
{
"EventName": "ex_no_retire.thread_not_selected",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire because thread arbitration did not select the thread.",
"UMask": "0x10"
},
{
"EventName": "ex_no_retire.load_not_complete",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire while the oldest op is waiting for load data.",
"UMask": "0xa2"
},
{
"EventName": "ex_no_retire.all",
"EventCode": "0xd6",
"BriefDescription": "Cycles with no retire for any reason.",
"UMask": "0x1b"
},
{
"EventName": "ls_not_halted_p0_cyc.p0_freq_cyc",
"EventCode": "0x120",
"BriefDescription": "Reference cycles (P0 frequency) not in halt .",
"UMask": "0x1"
},
{
"EventName": "ex_ret_ucode_instr",
"EventCode": "0x1c1",
"BriefDescription": "Retired microcoded instructions."
},
{
"EventName": "ex_ret_ucode_ops",
"EventCode": "0x1c2",
"BriefDescription": "Retired microcode ops."
},
{
"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops",
"EventCode": "0x1cf",
"BriefDescription": "Ops tagged by IBS.",
"UMask": "0x01"
},
{
"EventName": "ex_tagged_ibs_ops.ibs_tagged_ops_ret",
"EventCode": "0x1cf",
"BriefDescription": "Ops tagged by IBS that retired.",
"UMask": "0x02"
},
{
"EventName": "ex_ret_fused_instr",
"EventCode": "0x1d0",
"BriefDescription": "Retired fused instructions."
}
]

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[
{
"EventName": "fp_ret_x87_fp_ops.add_sub_ops",
"EventCode": "0x02",
"BriefDescription": "Retired x87 floating-point add and subtract ops.",
"UMask": "0x01"
},
{
"EventName": "fp_ret_x87_fp_ops.mul_ops",
"EventCode": "0x02",
"BriefDescription": "Retired x87 floating-point multiply ops.",
"UMask": "0x02"
},
{
"EventName": "fp_ret_x87_fp_ops.div_sqrt_ops",
"EventCode": "0x02",
"BriefDescription": "Retired x87 floating-point divide and square root ops.",
"UMask": "0x04"
},
{
"EventName": "fp_ret_x87_fp_ops.all",
"EventCode": "0x02",
"BriefDescription": "Retired x87 floating-point ops of all types.",
"UMask": "0x07"
},
{
"EventName": "fp_ret_sse_avx_ops.add_sub_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point add and subtract ops.",
"UMask": "0x01"
},
{
"EventName": "fp_ret_sse_avx_ops.mult_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point multiply ops.",
"UMask": "0x02"
},
{
"EventName": "fp_ret_sse_avx_ops.div_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point divide and square root ops.",
"UMask": "0x04"
},
{
"EventName": "fp_ret_sse_avx_ops.mac_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point multiply-accumulate ops (each operation is counted as 2 ops).",
"UMask": "0x08"
},
{
"EventName": "fp_ret_sse_avx_ops.bfloat_mac_flops",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point bfloat multiply-accumulate ops (each operation is counted as 2 ops).",
"UMask": "0x10"
},
{
"EventName": "fp_ret_sse_avx_ops.all",
"EventCode": "0x03",
"BriefDescription": "Retired SSE and AVX floating-point ops of all types.",
"UMask": "0x1f"
},
{
"EventName": "fp_retired_ser_ops.x87_ctrl_ret",
"EventCode": "0x05",
"BriefDescription": "Retired x87 control word mispredict traps due to mispredictions in RC or PC, or changes in exception mask bits.",
"UMask": "0x01"
},
{
"EventName": "fp_retired_ser_ops.x87_bot_ret",
"EventCode": "0x05",
"BriefDescription": "Retired x87 bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executing.",
"UMask": "0x02"
},
{
"EventName": "fp_retired_ser_ops.sse_ctrl_ret",
"EventCode": "0x05",
"BriefDescription": "Retired SSE and AVX control word mispredict traps.",
"UMask": "0x04"
},
{
"EventName": "fp_retired_ser_ops.sse_bot_ret",
"EventCode": "0x05",
"BriefDescription": "Retired SSE and AVX bottom-executing ops. Bottom-executing ops wait for all older ops to retire before executing.",
"UMask": "0x08"
},
{
"EventName": "fp_retired_ser_ops.all",
"EventCode": "0x05",
"BriefDescription": "Retired SSE and AVX serializing ops of all types.",
"UMask": "0x0f"
},
{
"EventName": "fp_ops_retired_by_width.x87_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired x87 floating-point ops.",
"UMask": "0x01"
},
{
"EventName": "fp_ops_retired_by_width.mmx_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired MMX floating-point ops.",
"UMask": "0x02"
},
{
"EventName": "fp_ops_retired_by_width.scalar_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired scalar floating-point ops.",
"UMask": "0x04"
},
{
"EventName": "fp_ops_retired_by_width.pack_128_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired packed 128-bit floating-point ops.",
"UMask": "0x08"
},
{
"EventName": "fp_ops_retired_by_width.pack_256_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired packed 256-bit floating-point ops.",
"UMask": "0x10"
},
{
"EventName": "fp_ops_retired_by_width.pack_512_uops_retired",
"EventCode": "0x08",
"BriefDescription": "Retired packed 512-bit floating-point ops.",
"UMask": "0x20"
},
{
"EventName": "fp_ops_retired_by_width.all",
"EventCode": "0x08",
"BriefDescription": "Retired floating-point ops of all widths.",
"UMask": "0x3f"
},
{
"EventName": "fp_ops_retired_by_type.scalar_add",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point add ops.",
"UMask": "0x01"
},
{
"EventName": "fp_ops_retired_by_type.scalar_sub",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point subtract ops.",
"UMask": "0x02"
},
{
"EventName": "fp_ops_retired_by_type.scalar_mul",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point multiply ops.",
"UMask": "0x03"
},
{
"EventName": "fp_ops_retired_by_type.scalar_mac",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point multiply-accumulate ops.",
"UMask": "0x04"
},
{
"EventName": "fp_ops_retired_by_type.scalar_div",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point divide ops.",
"UMask": "0x05"
},
{
"EventName": "fp_ops_retired_by_type.scalar_sqrt",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point square root ops.",
"UMask": "0x06"
},
{
"EventName": "fp_ops_retired_by_type.scalar_cmp",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point compare ops.",
"UMask": "0x07"
},
{
"EventName": "fp_ops_retired_by_type.scalar_cvt",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point convert ops.",
"UMask": "0x08"
},
{
"EventName": "fp_ops_retired_by_type.scalar_blend",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point blend ops.",
"UMask": "0x09"
},
{
"EventName": "fp_ops_retired_by_type.scalar_other",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point ops of other types.",
"UMask": "0x0e"
},
{
"EventName": "fp_ops_retired_by_type.scalar_all",
"EventCode": "0x0a",
"BriefDescription": "Retired scalar floating-point ops of all types.",
"UMask": "0x0f"
},
{
"EventName": "fp_ops_retired_by_type.vector_add",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point add ops.",
"UMask": "0x10"
},
{
"EventName": "fp_ops_retired_by_type.vector_sub",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point subtract ops.",
"UMask": "0x20"
},
{
"EventName": "fp_ops_retired_by_type.vector_mul",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point multiply ops.",
"UMask": "0x30"
},
{
"EventName": "fp_ops_retired_by_type.vector_mac",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point multiply-accumulate ops.",
"UMask": "0x40"
},
{
"EventName": "fp_ops_retired_by_type.vector_div",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point divide ops.",
"UMask": "0x50"
},
{
"EventName": "fp_ops_retired_by_type.vector_sqrt",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point square root ops.",
"UMask": "0x60"
},
{
"EventName": "fp_ops_retired_by_type.vector_cmp",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point compare ops.",
"UMask": "0x70"
},
{
"EventName": "fp_ops_retired_by_type.vector_cvt",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point convert ops.",
"UMask": "0x80"
},
{
"EventName": "fp_ops_retired_by_type.vector_blend",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point blend ops.",
"UMask": "0x90"
},
{
"EventName": "fp_ops_retired_by_type.vector_shuffle",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0xb0"
},
{
"EventName": "fp_ops_retired_by_type.vector_logical",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point logical ops.",
"UMask": "0xd0"
},
{
"EventName": "fp_ops_retired_by_type.vector_other",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point ops of other types.",
"UMask": "0xe0"
},
{
"EventName": "fp_ops_retired_by_type.vector_all",
"EventCode": "0x0a",
"BriefDescription": "Retired vector floating-point ops of all types.",
"UMask": "0xf0"
},
{
"EventName": "fp_ops_retired_by_type.all",
"EventCode": "0x0a",
"BriefDescription": "Retired floating-point ops of all types.",
"UMask": "0xff"
},
{
"EventName": "sse_avx_ops_retired.mmx_add",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer add.",
"UMask": "0x01"
},
{
"EventName": "sse_avx_ops_retired.mmx_sub",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer subtract ops.",
"UMask": "0x02"
},
{
"EventName": "sse_avx_ops_retired.mmx_mul",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer multiply ops.",
"UMask": "0x03"
},
{
"EventName": "sse_avx_ops_retired.mmx_mac",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer multiply-accumulate ops.",
"UMask": "0x04"
},
{
"EventName": "sse_avx_ops_retired.mmx_cmp",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer compare ops.",
"UMask": "0x07"
},
{
"EventName": "sse_avx_ops_retired.mmx_shift",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer shift ops.",
"UMask": "0x09"
},
{
"EventName": "sse_avx_ops_retired.mmx_mov",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer MOV ops.",
"UMask": "0x0a"
},
{
"EventName": "sse_avx_ops_retired.mmx_shuffle",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0x0b"
},
{
"EventName": "sse_avx_ops_retired.mmx_pack",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer pack ops.",
"UMask": "0x0c"
},
{
"EventName": "sse_avx_ops_retired.mmx_logical",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer logical ops.",
"UMask": "0x0d"
},
{
"EventName": "sse_avx_ops_retired.mmx_other",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer multiply ops of other types.",
"UMask": "0x0e"
},
{
"EventName": "sse_avx_ops_retired.mmx_all",
"EventCode": "0x0b",
"BriefDescription": "Retired MMX integer ops of all types.",
"UMask": "0x0f"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_add",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer add ops.",
"UMask": "0x10"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_sub",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer subtract ops.",
"UMask": "0x20"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_mul",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer multiply ops.",
"UMask": "0x30"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_mac",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer multiply-accumulate ops.",
"UMask": "0x40"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_aes",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer AES ops.",
"UMask": "0x50"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_sha",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer SHA ops.",
"UMask": "0x60"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_cmp",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer compare ops.",
"UMask": "0x70"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_clm",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer CLM ops.",
"UMask": "0x80"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_shift",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer shift ops.",
"UMask": "0x90"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_mov",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer MOV ops.",
"UMask": "0xa0"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_shuffle",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0xb0"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_pack",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer pack ops.",
"UMask": "0xc0"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_logical",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer logical ops.",
"UMask": "0xd0"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_other",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer ops of other types.",
"UMask": "0xe0"
},
{
"EventName": "sse_avx_ops_retired.sse_avx_all",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE and AVX integer ops of all types.",
"UMask": "0xf0"
},
{
"EventName": "sse_avx_ops_retired.all",
"EventCode": "0x0b",
"BriefDescription": "Retired SSE, AVX and MMX integer ops of all types.",
"UMask": "0xff"
},
{
"EventName": "fp_pack_ops_retired.fp128_add",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point add ops.",
"UMask": "0x01"
},
{
"EventName": "fp_pack_ops_retired.fp128_sub",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point subtract ops.",
"UMask": "0x02"
},
{
"EventName": "fp_pack_ops_retired.fp128_mul",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point multiply ops.",
"UMask": "0x03"
},
{
"EventName": "fp_pack_ops_retired.fp128_mac",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point multiply-accumulate ops.",
"UMask": "0x04"
},
{
"EventName": "fp_pack_ops_retired.fp128_div",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point divide ops.",
"UMask": "0x05"
},
{
"EventName": "fp_pack_ops_retired.fp128_sqrt",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point square root ops.",
"UMask": "0x06"
},
{
"EventName": "fp_pack_ops_retired.fp128_cmp",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point compare ops.",
"UMask": "0x07"
},
{
"EventName": "fp_pack_ops_retired.fp128_cvt",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point convert ops.",
"UMask": "0x08"
},
{
"EventName": "fp_pack_ops_retired.fp128_blend",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point blend ops.",
"UMask": "0x09"
},
{
"EventName": "fp_pack_ops_retired.fp128_shuffle",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0x0b"
},
{
"EventName": "fp_pack_ops_retired.fp128_logical",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point logical ops.",
"UMask": "0x0d"
},
{
"EventName": "fp_pack_ops_retired.fp128_other",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point ops of other types.",
"UMask": "0x0e"
},
{
"EventName": "fp_pack_ops_retired.fp128_all",
"EventCode": "0x0c",
"BriefDescription": "Retired 128-bit packed floating-point ops of all types.",
"UMask": "0x0f"
},
{
"EventName": "fp_pack_ops_retired.fp256_add",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point add ops.",
"UMask": "0x10"
},
{
"EventName": "fp_pack_ops_retired.fp256_sub",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point subtract ops.",
"UMask": "0x20"
},
{
"EventName": "fp_pack_ops_retired.fp256_mul",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point multiply ops.",
"UMask": "0x30"
},
{
"EventName": "fp_pack_ops_retired.fp256_mac",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point multiply-accumulate ops.",
"UMask": "0x40"
},
{
"EventName": "fp_pack_ops_retired.fp256_div",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point divide ops.",
"UMask": "0x50"
},
{
"EventName": "fp_pack_ops_retired.fp256_sqrt",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point square root ops.",
"UMask": "0x60"
},
{
"EventName": "fp_pack_ops_retired.fp256_cmp",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point compare ops.",
"UMask": "0x70"
},
{
"EventName": "fp_pack_ops_retired.fp256_cvt",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point convert ops.",
"UMask": "0x80"
},
{
"EventName": "fp_pack_ops_retired.fp256_blend",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point blend ops.",
"UMask": "0x90"
},
{
"EventName": "fp_pack_ops_retired.fp256_shuffle",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0xb0"
},
{
"EventName": "fp_pack_ops_retired.fp256_logical",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point logical ops.",
"UMask": "0xd0"
},
{
"EventName": "fp_pack_ops_retired.fp256_other",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point ops of other types.",
"UMask": "0xe0"
},
{
"EventName": "fp_pack_ops_retired.fp256_all",
"EventCode": "0x0c",
"BriefDescription": "Retired 256-bit packed floating-point ops of all types.",
"UMask": "0xf0"
},
{
"EventName": "fp_pack_ops_retired.all",
"EventCode": "0x0c",
"BriefDescription": "Retired packed floating-point ops of all types.",
"UMask": "0xff"
},
{
"EventName": "packed_int_op_type.int128_add",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer add ops.",
"UMask": "0x01"
},
{
"EventName": "packed_int_op_type.int128_sub",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer subtract ops.",
"UMask": "0x02"
},
{
"EventName": "packed_int_op_type.int128_mul",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer multiply ops.",
"UMask": "0x03"
},
{
"EventName": "packed_int_op_type.int128_mac",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer multiply-accumulate ops.",
"UMask": "0x04"
},
{
"EventName": "packed_int_op_type.int128_aes",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer AES ops.",
"UMask": "0x05"
},
{
"EventName": "packed_int_op_type.int128_sha",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer SHA ops.",
"UMask": "0x06"
},
{
"EventName": "packed_int_op_type.int128_cmp",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer compare ops.",
"UMask": "0x07"
},
{
"EventName": "packed_int_op_type.int128_clm",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer CLM ops.",
"UMask": "0x08"
},
{
"EventName": "packed_int_op_type.int128_shift",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer shift ops.",
"UMask": "0x09"
},
{
"EventName": "packed_int_op_type.int128_mov",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer MOV ops.",
"UMask": "0x0a"
},
{
"EventName": "packed_int_op_type.int128_shuffle",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0x0b"
},
{
"EventName": "packed_int_op_type.int128_pack",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer pack ops.",
"UMask": "0x0c"
},
{
"EventName": "packed_int_op_type.int128_logical",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer logical ops.",
"UMask": "0x0d"
},
{
"EventName": "packed_int_op_type.int128_other",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer ops of other types.",
"UMask": "0x0e"
},
{
"EventName": "packed_int_op_type.int128_all",
"EventCode": "0x0d",
"BriefDescription": "Retired 128-bit packed integer ops of all types.",
"UMask": "0x0f"
},
{
"EventName": "packed_int_op_type.int256_add",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer add ops.",
"UMask": "0x10"
},
{
"EventName": "packed_int_op_type.int256_sub",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer subtract ops.",
"UMask": "0x20"
},
{
"EventName": "packed_int_op_type.int256_mul",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer multiply ops.",
"UMask": "0x30"
},
{
"EventName": "packed_int_op_type.int256_mac",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer multiply-accumulate ops.",
"UMask": "0x40"
},
{
"EventName": "packed_int_op_type.int256_cmp",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer compare ops.",
"UMask": "0x70"
},
{
"EventName": "packed_int_op_type.int256_shift",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer shift ops.",
"UMask": "0x90"
},
{
"EventName": "packed_int_op_type.int256_mov",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer MOV ops.",
"UMask": "0xa0"
},
{
"EventName": "packed_int_op_type.int256_shuffle",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer shuffle ops (may include instructions not necessarily thought of as including shuffles e.g. horizontal add, dot product, and certain MOV instructions).",
"UMask": "0xb0"
},
{
"EventName": "packed_int_op_type.int256_pack",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer pack ops.",
"UMask": "0xc0"
},
{
"EventName": "packed_int_op_type.int256_logical",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer logical ops.",
"UMask": "0xd0"
},
{
"EventName": "packed_int_op_type.int256_other",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer ops of other types.",
"UMask": "0xe0"
},
{
"EventName": "packed_int_op_type.int256_all",
"EventCode": "0x0d",
"BriefDescription": "Retired 256-bit packed integer ops of all types.",
"UMask": "0xf0"
},
{
"EventName": "packed_int_op_type.all",
"EventCode": "0x0d",
"BriefDescription": "Retired packed integer ops of all types.",
"UMask": "0xff"
},
{
"EventName": "fp_disp_faults.x87_fill_fault",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults for x87 fills.",
"UMask": "0x01"
},
{
"EventName": "fp_disp_faults.xmm_fill_fault",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults for XMM fills.",
"UMask": "0x02"
},
{
"EventName": "fp_disp_faults.ymm_fill_fault",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults for YMM fills.",
"UMask": "0x04"
},
{
"EventName": "fp_disp_faults.ymm_spill_fault",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults for YMM spills.",
"UMask": "0x08"
},
{
"EventName": "fp_disp_faults.sse_avx_all",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults of all types for SSE and AVX ops.",
"UMask": "0x0e"
},
{
"EventName": "fp_disp_faults.all",
"EventCode": "0x0e",
"BriefDescription": "Floating-point dispatch faults of all types.",
"UMask": "0x0f"
}
]

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lib/libpmc/pmu-events/arch/x86/amdzen4/memory-controller.json Normal file
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[
{
"EventName": "umc_mem_clk",
"PublicDescription": "Number of memory clock cycles.",
"EventCode": "0x00",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_act_cmd.all",
"PublicDescription": "Number of ACTIVATE commands sent.",
"EventCode": "0x05",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_act_cmd.rd",
"PublicDescription": "Number of ACTIVATE commands sent for reads.",
"EventCode": "0x05",
"RdWrMask": "0x1",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_act_cmd.wr",
"PublicDescription": "Number of ACTIVATE commands sent for writes.",
"EventCode": "0x05",
"RdWrMask": "0x2",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_pchg_cmd.all",
"PublicDescription": "Number of PRECHARGE commands sent.",
"EventCode": "0x06",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_pchg_cmd.rd",
"PublicDescription": "Number of PRECHARGE commands sent for reads.",
"EventCode": "0x06",
"RdWrMask": "0x1",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_pchg_cmd.wr",
"PublicDescription": "Number of PRECHARGE commands sent for writes.",
"EventCode": "0x06",
"RdWrMask": "0x2",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_cas_cmd.all",
"PublicDescription": "Number of CAS commands sent.",
"EventCode": "0x0a",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_cas_cmd.rd",
"PublicDescription": "Number of CAS commands sent for reads.",
"EventCode": "0x0a",
"RdWrMask": "0x1",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_cas_cmd.wr",
"PublicDescription": "Number of CAS commands sent for writes.",
"EventCode": "0x0a",
"RdWrMask": "0x2",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_data_slot_clks.all",
"PublicDescription": "Number of clocks used by the data bus.",
"EventCode": "0x14",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_data_slot_clks.rd",
"PublicDescription": "Number of clocks used by the data bus for reads.",
"EventCode": "0x14",
"RdWrMask": "0x1",
"PerPkg": "1",
"Unit": "UMCPMC"
},
{
"EventName": "umc_data_slot_clks.wr",
"PublicDescription": "Number of clocks used by the data bus for writes.",
"EventCode": "0x14",
"RdWrMask": "0x2",
"PerPkg": "1",
"Unit": "UMCPMC"
}
]

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[
{
"EventName": "ls_bad_status2.stli_other",
"EventCode": "0x24",
"BriefDescription": "Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store).",
"UMask": "0x02"
},
{
"EventName": "ls_dispatch.ld_dispatch",
"EventCode": "0x29",
"BriefDescription": "Number of memory load operations dispatched to the load-store unit.",
"UMask": "0x01"
},
{
"EventName": "ls_dispatch.store_dispatch",
"EventCode": "0x29",
"BriefDescription": "Number of memory store operations dispatched to the load-store unit.",
"UMask": "0x02"
},
{
"EventName": "ls_dispatch.ld_st_dispatch",
"EventCode": "0x29",
"BriefDescription": "Number of memory load-store operations dispatched to the load-store unit.",
"UMask": "0x04"
},
{
"EventName": "ls_stlf",
"EventCode": "0x35",
"BriefDescription": "Store-to-load-forward (STLF) hits."
},
{
"EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",
"EventCode": "0x37",
"BriefDescription": "Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full.",
"UMask": "0x01"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",
"UMask": "0x01"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
"UMask": "0x02"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",
"UMask": "0x04"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",
"UMask": "0x08"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages.",
"UMask": "0x10"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
"UMask": "0x20"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages.",
"UMask": "0x40"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages.",
"UMask": "0x80"
},
{
"EventName": "ls_l1_d_tlb_miss.all_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes.",
"UMask": "0xf0"
},
{
"EventName": "ls_l1_d_tlb_miss.all",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses for all page sizes.",
"UMask": "0xff"
},
{
"EventName": "ls_misal_loads.ma64",
"EventCode": "0x47",
"BriefDescription": "64B misaligned (cacheline crossing) loads.",
"UMask": "0x01"
},
{
"EventName": "ls_misal_loads.ma4k",
"EventCode": "0x47",
"BriefDescription": "4kB misaligned (page crossing) loads.",
"UMask": "0x02"
},
{
"EventName": "ls_tlb_flush.all",
"EventCode": "0x78",
"BriefDescription": "All TLB Flushes.",
"UMask": "0xff"
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_hit",
"EventCode": "0x84",
"BriefDescription": "Instruction fetches that miss in the L1 ITLB but hit in the L2 ITLB."
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if4k",
"EventCode": "0x85",
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 4k pages.",
"UMask": "0x01"
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if2m",
"EventCode": "0x85",
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 2M pages.",
"UMask": "0x02"
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.if1g",
"EventCode": "0x85",
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for 1G pages.",
"UMask": "0x04"
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.coalesced_4k",
"EventCode": "0x85",
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
"UMask": "0x08"
},
{
"EventName": "bp_l1_tlb_miss_l2_tlb_miss.all",
"EventCode": "0x85",
"BriefDescription": "Instruction fetches that miss in both the L1 and L2 ITLBs (page-table walks are requested) for all page sizes.",
"UMask": "0x0f"
},
{
"EventName": "bp_l1_tlb_fetch_hit.if4k",
"EventCode": "0x94",
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 4k or coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
"UMask": "0x01"
},
{
"EventName": "bp_l1_tlb_fetch_hit.if2m",
"EventCode": "0x94",
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 2M pages.",
"UMask": "0x02"
},
{
"EventName": "bp_l1_tlb_fetch_hit.if1g",
"EventCode": "0x94",
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for 1G pages.",
"UMask": "0x04"
},
{
"EventName": "bp_l1_tlb_fetch_hit.all",
"EventCode": "0x94",
"BriefDescription": "Instruction fetches that hit in the L1 ITLB for all page sizes.",
"UMask": "0x07"
}
]

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[
{
"EventName": "resyncs_or_nc_redirects",
"EventCode": "0x96",
"BriefDescription": "Pipeline restarts not caused by branch mispredicts."
},
{
"EventName": "de_op_queue_empty",
"EventCode": "0xa9",
"BriefDescription": "Cycles when the op queue is empty. Such cycles indicate that the front-end is not delivering instructions fast enough."
},
{
"EventName": "de_src_op_disp.decoder",
"EventCode": "0xaa",
"BriefDescription": "Ops fetched from instruction cache and dispatched.",
"UMask": "0x01"
},
{
"EventName": "de_src_op_disp.op_cache",
"EventCode": "0xaa",
"BriefDescription": "Ops fetched from op cache and dispatched.",
"UMask": "0x02"
},
{
"EventName": "de_src_op_disp.loop_buffer",
"EventCode": "0xaa",
"BriefDescription": "Ops dispatched from loop buffer.",
"UMask": "0x04"
},
{
"EventName": "de_src_op_disp.all",
"EventCode": "0xaa",
"BriefDescription": "Ops dispatched from any source.",
"UMask": "0x07"
},
{
"EventName": "de_dis_ops_from_decoder.any_fp_dispatch",
"EventCode": "0xab",
"BriefDescription": "Number of ops dispatched to the floating-point unit.",
"UMask": "0x04"
},
{
"EventName": "de_dis_ops_from_decoder.disp_op_type.any_integer_dispatch",
"EventCode": "0xab",
"BriefDescription": "Number of ops dispatched to the integer execution unit.",
"UMask": "0x08"
},
{
"EventName": "de_dis_dispatch_token_stalls1.int_phy_reg_file_rsrc_stall",
"EventCode": "0xae",
"BriefDescription": "Number of cycles dispatch is stalled for integer physical register file tokens.",
"UMask": "0x01"
},
{
"EventName": "de_dis_dispatch_token_stalls1.load_queue_rsrc_stall",
"EventCode": "0xae",
"BriefDescription": "Number of cycles dispatch is stalled for Load queue token.",
"UMask": "0x02"
},
{
"EventName": "de_dis_dispatch_token_stalls1.store_queue_rsrc_stall",
"EventCode": "0xae",
"BriefDescription": "Number of cycles dispatch is stalled for store queue tokens.",
"UMask": "0x04"
},
{
"EventName": "de_dis_dispatch_token_stalls1.taken_brnch_buffer_rsrc",
"EventCode": "0xae",
"BriefDescription": "Number of cycles dispatch is stalled for taken branch buffer tokens.",
"UMask": "0x10"
},
{
"EventName": "de_dis_dispatch_token_stalls1.fp_reg_file_rsrc_stall",
"EventCode": "0xae",
"BriefDescription": "Number of cycles dispatch is stalled for floating-point register file tokens.",
"UMask": "0x20"
},
{
"EventName": "de_dis_dispatch_token_stalls1.fp_sch_rsrc_stall",
"EventCode": "0xae",
"BriefDescription": "Number of cycles dispatch is stalled for floating-point scheduler tokens.",
"UMask": "0x40"
},
{
"EventName": "de_dis_dispatch_token_stalls1.fp_flush_recovery_stall",
"EventCode": "0xae",
"BriefDescription": "Number of cycles dispatch is stalled for floating-point flush recovery.",
"UMask": "0x80"
},
{
"EventName": "de_dis_dispatch_token_stalls2.int_sch0_token_stall",
"EventCode": "0xaf",
"BriefDescription": "Number of cycles dispatch is stalled for integer scheduler queue 0 tokens.",
"UMask": "0x01"
},
{
"EventName": "de_dis_dispatch_token_stalls2.int_sch1_token_stall",
"EventCode": "0xaf",
"BriefDescription": "Number of cycles dispatch is stalled for integer scheduler queue 1 tokens.",
"UMask": "0x02"
},
{
"EventName": "de_dis_dispatch_token_stalls2.int_sch2_token_stall",
"EventCode": "0xaf",
"BriefDescription": "Number of cycles dispatch is stalled for integer scheduler queue 2 tokens.",
"UMask": "0x04"
},
{
"EventName": "de_dis_dispatch_token_stalls2.int_sch3_token_stall",
"EventCode": "0xaf",
"BriefDescription": "Number of cycles dispatch is stalled for integer scheduler queue 3 tokens.",
"UMask": "0x08"
},
{
"EventName": "de_dis_dispatch_token_stalls2.retire_token_stall",
"EventCode": "0xaf",
"BriefDescription": "Number of cycles dispatch is stalled for retire queue tokens.",
"UMask": "0x20"
},
{
"EventName": "de_no_dispatch_per_slot.no_ops_from_frontend",
"EventCode": "0x1a0",
"BriefDescription": "In each cycle counts dispatch slots left empty because the front-end did not supply ops.",
"UMask": "0x01"
},
{
"EventName": "de_no_dispatch_per_slot.backend_stalls",
"EventCode": "0x1a0",
"BriefDescription": "In each cycle counts ops unable to dispatch because of back-end stalls.",
"UMask": "0x1e"
},
{
"EventName": "de_no_dispatch_per_slot.smt_contention",
"EventCode": "0x1a0",
"BriefDescription": "In each cycle counts ops unable to dispatch because the dispatch cycle was granted to the other SMT thread.",
"UMask": "0x60"
}
]

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[
{
"MetricName": "total_dispatch_slots",
"BriefDescription": "Total dispatch slots (upto 6 instructions can be dispatched in each cycle).",
"MetricExpr": "6 * ls_not_halted_cyc"
},
{
"MetricName": "frontend_bound",
"BriefDescription": "Fraction of dispatch slots that remained unused because the frontend did not supply enough instructions/ops.",
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend, total_dispatch_slots)",
"MetricGroup": "PipelineL1",
"ScaleUnit": "100%"
},
{
"MetricName": "bad_speculation",
"BriefDescription": "Fraction of dispatched ops that did not retire.",
"MetricExpr": "d_ratio(de_src_op_disp.all - ex_ret_ops, total_dispatch_slots)",
"MetricGroup": "PipelineL1",
"ScaleUnit": "100%"
},
{
"MetricName": "backend_bound",
"BriefDescription": "Fraction of dispatch slots that remained unused because of backend stalls.",
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.backend_stalls, total_dispatch_slots)",
"MetricGroup": "PipelineL1",
"ScaleUnit": "100%"
},
{
"MetricName": "smt_contention",
"BriefDescription": "Fraction of dispatch slots that remained unused because the other thread was selected.",
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.smt_contention, total_dispatch_slots)",
"MetricGroup": "PipelineL1",
"ScaleUnit": "100%"
},
{
"MetricName": "retiring",
"BriefDescription": "Fraction of dispatch slots used by ops that retired.",
"MetricExpr": "d_ratio(ex_ret_ops, total_dispatch_slots)",
"MetricGroup": "PipelineL1",
"ScaleUnit": "100%"
},
{
"MetricName": "frontend_bound_latency",
"BriefDescription": "Fraction of dispatch slots that remained unused because of a latency bottleneck in the frontend (such as instruction cache or TLB misses).",
"MetricExpr": "d_ratio((6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\\,cmask\\=0x6@), total_dispatch_slots)",
"MetricGroup": "PipelineL2;frontend_bound_group",
"ScaleUnit": "100%"
},
{
"MetricName": "frontend_bound_bandwidth",
"BriefDescription": "Fraction of dispatch slots that remained unused because of a bandwidth bottleneck in the frontend (such as decode or op cache fetch bandwidth).",
"MetricExpr": "d_ratio(de_no_dispatch_per_slot.no_ops_from_frontend - (6 * cpu@de_no_dispatch_per_slot.no_ops_from_frontend\\,cmask\\=0x6@), total_dispatch_slots)",
"MetricGroup": "PipelineL2;frontend_bound_group",
"ScaleUnit": "100%"
},
{
"MetricName": "bad_speculation_mispredicts",
"BriefDescription": "Fraction of dispatched ops that were flushed due to branch mispredicts.",
"MetricExpr": "d_ratio(bad_speculation * ex_ret_brn_misp, ex_ret_brn_misp + resyncs_or_nc_redirects)",
"MetricGroup": "PipelineL2;bad_speculation_group",
"ScaleUnit": "100%"
},
{
"MetricName": "bad_speculation_pipeline_restarts",
"BriefDescription": "Fraction of dispatched ops that were flushed due to pipeline restarts (resyncs).",
"MetricExpr": "d_ratio(bad_speculation * resyncs_or_nc_redirects, ex_ret_brn_misp + resyncs_or_nc_redirects)",
"MetricGroup": "PipelineL2;bad_speculation_group",
"ScaleUnit": "100%"
},
{
"MetricName": "backend_bound_memory",
"BriefDescription": "Fraction of dispatch slots that remained unused because of stalls due to the memory subsystem.",
"MetricExpr": "backend_bound * d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete)",
"MetricGroup": "PipelineL2;backend_bound_group",
"ScaleUnit": "100%"
},
{
"MetricName": "backend_bound_cpu",
"BriefDescription": "Fraction of dispatch slots that remained unused because of stalls not related to the memory subsystem.",
"MetricExpr": "backend_bound * (1 - d_ratio(ex_no_retire.load_not_complete, ex_no_retire.not_complete))",
"MetricGroup": "PipelineL2;backend_bound_group",
"ScaleUnit": "100%"
},
{
"MetricName": "retiring_fastpath",
"BriefDescription": "Fraction of dispatch slots used by fastpath ops that retired.",
"MetricExpr": "retiring * (1 - d_ratio(ex_ret_ucode_ops, ex_ret_ops))",
"MetricGroup": "PipelineL2;retiring_group",
"ScaleUnit": "100%"
},
{
"MetricName": "retiring_microcode",
"BriefDescription": "Fraction of dispatch slots used by microcode ops that retired.",
"MetricExpr": "retiring * d_ratio(ex_ret_ucode_ops, ex_ret_ops)",
"MetricGroup": "PipelineL2;retiring_group",
"ScaleUnit": "100%"
}
]

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[
{
"MetricName": "branch_misprediction_ratio",
"BriefDescription": "Execution-time branch misprediction ratio (non-speculative).",
"MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
"MetricGroup": "branch_prediction",
"ScaleUnit": "100%"
},
{
"EventName": "all_data_cache_accesses",
"EventCode": "0x29",
"BriefDescription": "All data cache accesses.",
"UMask": "0x07"
},
{
"MetricName": "all_l2_cache_accesses",
"BriefDescription": "All L2 cache accesses.",
"MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_accesses_from_l1_ic_misses",
"BriefDescription": "L2 cache accesses from L1 instruction cache misses (including prefetch).",
"MetricExpr": "l2_request_g1.cacheable_ic_read",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_accesses_from_l1_dc_misses",
"BriefDescription": "L2 cache accesses from L1 data cache misses (including prefetch).",
"MetricExpr": "l2_request_g1.all_dc",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_accesses_from_l2_hwpf",
"BriefDescription": "L2 cache accesses from L2 cache hardware prefetcher.",
"MetricExpr": "l2_pf_hit_l2.all + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
"MetricGroup": "l2_cache"
},
{
"MetricName": "all_l2_cache_misses",
"BriefDescription": "All L2 cache misses.",
"MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_misses_from_l1_ic_miss",
"BriefDescription": "L2 cache misses from L1 instruction cache misses.",
"MetricExpr": "l2_cache_req_stat.ic_fill_miss",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_misses_from_l1_dc_miss",
"BriefDescription": "L2 cache misses from L1 data cache misses.",
"MetricExpr": "l2_cache_req_stat.ls_rd_blk_c",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_misses_from_l2_hwpf",
"BriefDescription": "L2 cache misses from L2 cache hardware prefetcher.",
"MetricExpr": "l2_pf_miss_l2_hit_l3.all + l2_pf_miss_l2_l3.all",
"MetricGroup": "l2_cache"
},
{
"MetricName": "all_l2_cache_hits",
"BriefDescription": "All L2 cache hits.",
"MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2.all",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_hits_from_l1_ic_miss",
"BriefDescription": "L2 cache hits from L1 instruction cache misses.",
"MetricExpr": "l2_cache_req_stat.ic_hit_in_l2",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_hits_from_l1_dc_miss",
"BriefDescription": "L2 cache hits from L1 data cache misses.",
"MetricExpr": "l2_cache_req_stat.dc_hit_in_l2",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l2_cache_hits_from_l2_hwpf",
"BriefDescription": "L2 cache hits from L2 cache hardware prefetcher.",
"MetricExpr": "l2_pf_hit_l2.all",
"MetricGroup": "l2_cache"
},
{
"MetricName": "l3_cache_accesses",
"BriefDescription": "L3 cache accesses.",
"MetricExpr": "l3_lookup_state.all_coherent_accesses_to_l3",
"MetricGroup": "l3_cache"
},
{
"MetricName": "l3_misses",
"BriefDescription": "L3 misses (including cacheline state change requests).",
"MetricExpr": "l3_lookup_state.l3_miss",
"MetricGroup": "l3_cache"
},
{
"MetricName": "l3_read_miss_latency",
"BriefDescription": "Average L3 read miss latency (in core clocks).",
"MetricExpr": "(l3_xi_sampled_latency.all * 10) / l3_xi_sampled_latency_requests.all",
"MetricGroup": "l3_cache",
"ScaleUnit": "1core clocks"
},
{
"MetricName": "op_cache_fetch_miss_ratio",
"BriefDescription": "Op cache miss ratio for all fetches.",
"MetricExpr": "d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses)",
"ScaleUnit": "100%"
},
{
"MetricName": "ic_fetch_miss_ratio",
"BriefDescription": "Instruction cache miss ratio for all fetches. An instruction cache miss will not be counted by this metric if it is an OC hit.",
"MetricExpr": "d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses)",
"ScaleUnit": "100%"
},
{
"MetricName": "l1_data_cache_fills_from_memory",
"BriefDescription": "L1 data cache fills from DRAM or MMIO in any NUMA node.",
"MetricExpr": "ls_any_fills_from_sys.dram_io_all",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_data_cache_fills_from_remote_node",
"BriefDescription": "L1 data cache fills from a different NUMA node.",
"MetricExpr": "ls_any_fills_from_sys.far_all",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_data_cache_fills_from_same_ccx",
"BriefDescription": "L1 data cache fills from within the same CCX.",
"MetricExpr": "ls_any_fills_from_sys.local_all",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_data_cache_fills_from_different_ccx",
"BriefDescription": "L1 data cache fills from another CCX cache in any NUMA node.",
"MetricExpr": "ls_any_fills_from_sys.remote_cache",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "all_l1_data_cache_fills",
"BriefDescription": "All L1 data cache fills.",
"MetricExpr": "ls_any_fills_from_sys.all",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_demand_data_cache_fills_from_local_l2",
"BriefDescription": "L1 demand data cache fills from local L2 cache.",
"MetricExpr": "ls_dmnd_fills_from_sys.local_l2",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_demand_data_cache_fills_from_same_ccx",
"BriefDescription": "L1 demand data cache fills from within the same CCX.",
"MetricExpr": "ls_dmnd_fills_from_sys.local_ccx",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_demand_data_cache_fills_from_near_cache",
"BriefDescription": "L1 demand data cache fills from another CCX cache in the same NUMA node.",
"MetricExpr": "ls_dmnd_fills_from_sys.near_cache",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_demand_data_cache_fills_from_near_memory",
"BriefDescription": "L1 demand data cache fills from DRAM or MMIO in the same NUMA node.",
"MetricExpr": "ls_dmnd_fills_from_sys.dram_io_near",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_demand_data_cache_fills_from_far_cache",
"BriefDescription": "L1 demand data cache fills from another CCX cache in a different NUMA node.",
"MetricExpr": "ls_dmnd_fills_from_sys.far_cache",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_demand_data_cache_fills_from_far_memory",
"BriefDescription": "L1 demand data cache fills from DRAM or MMIO in a different NUMA node.",
"MetricExpr": "ls_dmnd_fills_from_sys.dram_io_far",
"MetricGroup": "l1_dcache"
},
{
"MetricName": "l1_itlb_misses",
"BriefDescription": "L1 instruction TLB misses.",
"MetricExpr": "bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss.all",
"MetricGroup": "tlb"
},
{
"MetricName": "l2_itlb_misses",
"BriefDescription": "L2 instruction TLB misses and instruction page walks.",
"MetricExpr": "bp_l1_tlb_miss_l2_tlb_miss.all",
"MetricGroup": "tlb"
},
{
"MetricName": "l1_dtlb_misses",
"BriefDescription": "L1 data TLB misses.",
"MetricExpr": "ls_l1_d_tlb_miss.all",
"MetricGroup": "tlb"
},
{
"MetricName": "l2_dtlb_misses",
"BriefDescription": "L2 data TLB misses and data page walks.",
"MetricExpr": "ls_l1_d_tlb_miss.all_l2_miss",
"MetricGroup": "tlb"
},
{
"MetricName": "all_tlbs_flushed",
"BriefDescription": "All TLBs flushed.",
"MetricExpr": "ls_tlb_flush.all",
"MetricGroup": "tlb"
},
{
"MetricName": "macro_ops_dispatched",
"BriefDescription": "Macro-ops dispatched.",
"MetricExpr": "de_src_op_disp.all",
"MetricGroup": "decoder"
},
{
"MetricName": "sse_avx_stalls",
"BriefDescription": "Mixed SSE/AVX stalls.",
"MetricExpr": "fp_disp_faults.sse_avx_all"
},
{
"MetricName": "macro_ops_retired",
"BriefDescription": "Macro-ops retired.",
"MetricExpr": "ex_ret_ops"
},
{
"MetricName": "dram_read_data_for_local_processor",
"BriefDescription": "DRAM read data for local processor.",
"MetricExpr": "local_processor_read_data_beats_cs0 + local_processor_read_data_beats_cs1 + local_processor_read_data_beats_cs2 + local_processor_read_data_beats_cs3 + local_processor_read_data_beats_cs4 + local_processor_read_data_beats_cs5 + local_processor_read_data_beats_cs6 + local_processor_read_data_beats_cs7 + local_processor_read_data_beats_cs8 + local_processor_read_data_beats_cs9 + local_processor_read_data_beats_cs10 + local_processor_read_data_beats_cs11",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "dram_write_data_for_local_processor",
"BriefDescription": "DRAM write data for local processor.",
"MetricExpr": "local_processor_write_data_beats_cs0 + local_processor_write_data_beats_cs1 + local_processor_write_data_beats_cs2 + local_processor_write_data_beats_cs3 + local_processor_write_data_beats_cs4 + local_processor_write_data_beats_cs5 + local_processor_write_data_beats_cs6 + local_processor_write_data_beats_cs7 + local_processor_write_data_beats_cs8 + local_processor_write_data_beats_cs9 + local_processor_write_data_beats_cs10 + local_processor_write_data_beats_cs11",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "dram_read_data_for_remote_processor",
"BriefDescription": "DRAM read data for remote processor.",
"MetricExpr": "remote_processor_read_data_beats_cs0 + remote_processor_read_data_beats_cs1 + remote_processor_read_data_beats_cs2 + remote_processor_read_data_beats_cs3 + remote_processor_read_data_beats_cs4 + remote_processor_read_data_beats_cs5 + remote_processor_read_data_beats_cs6 + remote_processor_read_data_beats_cs7 + remote_processor_read_data_beats_cs8 + remote_processor_read_data_beats_cs9 + remote_processor_read_data_beats_cs10 + remote_processor_read_data_beats_cs11",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "dram_write_data_for_remote_processor",
"BriefDescription": "DRAM write data for remote processor.",
"MetricExpr": "remote_processor_write_data_beats_cs0 + remote_processor_write_data_beats_cs1 + remote_processor_write_data_beats_cs2 + remote_processor_write_data_beats_cs3 + remote_processor_write_data_beats_cs4 + remote_processor_write_data_beats_cs5 + remote_processor_write_data_beats_cs6 + remote_processor_write_data_beats_cs7 + remote_processor_write_data_beats_cs8 + remote_processor_write_data_beats_cs9 + remote_processor_write_data_beats_cs10 + remote_processor_write_data_beats_cs11",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "local_socket_upstream_dma_read_data",
"BriefDescription": "Local socket upstream DMA read data.",
"MetricExpr": "local_socket_upstream_read_beats_iom0 + local_socket_upstream_read_beats_iom1 + local_socket_upstream_read_beats_iom2 + local_socket_upstream_read_beats_iom3",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "local_socket_upstream_dma_write_data",
"BriefDescription": "Local socket upstream DMA write data.",
"MetricExpr": "local_socket_upstream_write_beats_iom0 + local_socket_upstream_write_beats_iom1 + local_socket_upstream_write_beats_iom2 + local_socket_upstream_write_beats_iom3",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "remote_socket_upstream_dma_read_data",
"BriefDescription": "Remote socket upstream DMA read data.",
"MetricExpr": "remote_socket_upstream_read_beats_iom0 + remote_socket_upstream_read_beats_iom1 + remote_socket_upstream_read_beats_iom2 + remote_socket_upstream_read_beats_iom3",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "remote_socket_upstream_dma_write_data",
"BriefDescription": "Remote socket upstream DMA write data.",
"MetricExpr": "remote_socket_upstream_write_beats_iom0 + remote_socket_upstream_write_beats_iom1 + remote_socket_upstream_write_beats_iom2 + remote_socket_upstream_write_beats_iom3",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "local_socket_inbound_data_to_cpu",
"BriefDescription": "Local socket inbound data to the CPU (e.g. read data).",
"MetricExpr": "local_socket_inf0_inbound_data_beats_ccm0 + local_socket_inf1_inbound_data_beats_ccm0 + local_socket_inf0_inbound_data_beats_ccm1 + local_socket_inf1_inbound_data_beats_ccm1 + local_socket_inf0_inbound_data_beats_ccm2 + local_socket_inf1_inbound_data_beats_ccm2 + local_socket_inf0_inbound_data_beats_ccm3 + local_socket_inf1_inbound_data_beats_ccm3 + local_socket_inf0_inbound_data_beats_ccm4 + local_socket_inf1_inbound_data_beats_ccm4 + local_socket_inf0_inbound_data_beats_ccm5 + local_socket_inf1_inbound_data_beats_ccm5 + local_socket_inf0_inbound_data_beats_ccm6 + local_socket_inf1_inbound_data_beats_ccm6 + local_socket_inf0_inbound_data_beats_ccm7 + local_socket_inf1_inbound_data_beats_ccm7",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "3.0517578125e-5MiB"
},
{
"MetricName": "local_socket_outbound_data_from_cpu",
"BriefDescription": "Local socket outbound data from the CPU (e.g. write data).",
"MetricExpr": "local_socket_inf0_outbound_data_beats_ccm0 + local_socket_inf1_outbound_data_beats_ccm0 + local_socket_inf0_outbound_data_beats_ccm1 + local_socket_inf1_outbound_data_beats_ccm1 + local_socket_inf0_outbound_data_beats_ccm2 + local_socket_inf1_outbound_data_beats_ccm2 + local_socket_inf0_outbound_data_beats_ccm3 + local_socket_inf1_outbound_data_beats_ccm3 + local_socket_inf0_outbound_data_beats_ccm4 + local_socket_inf1_outbound_data_beats_ccm4 + local_socket_inf0_outbound_data_beats_ccm5 + local_socket_inf1_outbound_data_beats_ccm5 + local_socket_inf0_outbound_data_beats_ccm6 + local_socket_inf1_outbound_data_beats_ccm6 + local_socket_inf0_outbound_data_beats_ccm7 + local_socket_inf1_outbound_data_beats_ccm7",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "remote_socket_inbound_data_to_cpu",
"BriefDescription": "Remote socket inbound data to the CPU (e.g. read data).",
"MetricExpr": "remote_socket_inf0_inbound_data_beats_ccm0 + remote_socket_inf1_inbound_data_beats_ccm0 + remote_socket_inf0_inbound_data_beats_ccm1 + remote_socket_inf1_inbound_data_beats_ccm1 + remote_socket_inf0_inbound_data_beats_ccm2 + remote_socket_inf1_inbound_data_beats_ccm2 + remote_socket_inf0_inbound_data_beats_ccm3 + remote_socket_inf1_inbound_data_beats_ccm3 + remote_socket_inf0_inbound_data_beats_ccm4 + remote_socket_inf1_inbound_data_beats_ccm4 + remote_socket_inf0_inbound_data_beats_ccm5 + remote_socket_inf1_inbound_data_beats_ccm5 + remote_socket_inf0_inbound_data_beats_ccm6 + remote_socket_inf1_inbound_data_beats_ccm6 + remote_socket_inf0_inbound_data_beats_ccm7 + remote_socket_inf1_inbound_data_beats_ccm7",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "3.0517578125e-5MiB"
},
{
"MetricName": "remote_socket_outbound_data_from_cpu",
"BriefDescription": "Remote socket outbound data from the CPU (e.g. write data).",
"MetricExpr": "remote_socket_inf0_outbound_data_beats_ccm0 + remote_socket_inf1_outbound_data_beats_ccm0 + remote_socket_inf0_outbound_data_beats_ccm1 + remote_socket_inf1_outbound_data_beats_ccm1 + remote_socket_inf0_outbound_data_beats_ccm2 + remote_socket_inf1_outbound_data_beats_ccm2 + remote_socket_inf0_outbound_data_beats_ccm3 + remote_socket_inf1_outbound_data_beats_ccm3 + remote_socket_inf0_outbound_data_beats_ccm4 + remote_socket_inf1_outbound_data_beats_ccm4 + remote_socket_inf0_outbound_data_beats_ccm5 + remote_socket_inf1_outbound_data_beats_ccm5 + remote_socket_inf0_outbound_data_beats_ccm6 + remote_socket_inf1_outbound_data_beats_ccm6 + remote_socket_inf0_outbound_data_beats_ccm7 + remote_socket_inf1_outbound_data_beats_ccm7",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "local_socket_outbound_data_from_all_links",
"BriefDescription": "Outbound data from all links (local socket).",
"MetricExpr": "local_socket_outbound_data_beats_link0 + local_socket_outbound_data_beats_link1 + local_socket_outbound_data_beats_link2 + local_socket_outbound_data_beats_link3 + local_socket_outbound_data_beats_link4 + local_socket_outbound_data_beats_link5 + local_socket_outbound_data_beats_link6 + local_socket_outbound_data_beats_link7",
"MetricGroup": "data_fabric",
"PerPkg": "1",
"ScaleUnit": "6.103515625e-5MiB"
},
{
"MetricName": "umc_data_bus_utilization",
"BriefDescription": "Memory controller data bus utilization.",
"MetricExpr": "d_ratio(umc_data_slot_clks.all / 2, umc_mem_clk)",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "100%"
},
{
"MetricName": "umc_cas_cmd_rate",
"BriefDescription": "Memory controller CAS command rate.",
"MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)",
"MetricGroup": "memory_controller",
"PerPkg": "1"
},
{
"MetricName": "umc_cas_cmd_read_ratio",
"BriefDescription": "Ratio of memory controller CAS commands for reads.",
"MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "100%"
},
{
"MetricName": "umc_cas_cmd_write_ratio",
"BriefDescription": "Ratio of memory controller CAS commands for writes.",
"MetricExpr": "d_ratio(umc_cas_cmd.wr, umc_cas_cmd.all)",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "100%"
},
{
"MetricName": "umc_mem_read_bandwidth",
"BriefDescription": "Estimated memory read bandwidth.",
"MetricExpr": "(umc_cas_cmd.rd * 64) / 1e6 / duration_time",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "1MB/s"
},
{
"MetricName": "umc_mem_write_bandwidth",
"BriefDescription": "Estimated memory write bandwidth.",
"MetricExpr": "(umc_cas_cmd.wr * 64) / 1e6 / duration_time",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "1MB/s"
},
{
"MetricName": "umc_mem_bandwidth",
"BriefDescription": "Estimated combined memory bandwidth.",
"MetricExpr": "(umc_cas_cmd.all * 64) / 1e6 / duration_time",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "1MB/s"
},
{
"MetricName": "umc_cas_cmd_read_ratio",
"BriefDescription": "Ratio of memory controller CAS commands for reads.",
"MetricExpr": "d_ratio(umc_cas_cmd.rd, umc_cas_cmd.all)",
"MetricGroup": "memory_controller",
"PerPkg": "1",
"ScaleUnit": "100%"
},
{
"MetricName": "umc_cas_cmd_rate",
"BriefDescription": "Memory controller CAS command rate.",
"MetricExpr": "d_ratio(umc_cas_cmd.all * 1000, umc_mem_clk)",
"MetricGroup": "memory_controller",
"PerPkg": "1"
},
{
"MetricName": "umc_activate_cmd_rate",
"BriefDescription": "Memory controller ACTIVATE command rate.",
"MetricExpr": "d_ratio(umc_act_cmd.all * 1000, umc_mem_clk)",
"MetricGroup": "memory_controller",
"PerPkg": "1"
},
{
"MetricName": "umc_precharge_cmd_rate",
"BriefDescription": "Memory controller PRECHARGE command rate.",
"MetricExpr": "d_ratio(umc_pchg_cmd.all * 1000, umc_mem_clk)",
"MetricGroup": "memory_controller",
"PerPkg": "1"
}
]

3
lib/libpmc/pmu-events/arch/x86/mapfile.csv
View File

@ -48,5 +48,6 @@ GenuineIntel-6-9A,v1,alderlake,core
GenuineIntel-6-8F,v1,sapphirerapids,core
AuthenticAMD-23-[012][0-9A-F],v2,amdzen1,core
AuthenticAMD-23-[[:xdigit:]]+,v1,amdzen2,core
AuthenticAMD-25-[[:xdigit:]]+,v1,amdzen3,core
AuthenticAMD-25-[0245][[:xdigit:]],v1,amdzen3,core
AuthenticAMD-25-[[:xdigit:]]+,v1,amdzen4,core
HygonGenuine-24-00,v2,amdzen1,core

1 Family-model Version Filename EventType
48 GenuineIntel-6-8F v1 sapphirerapids core
49 AuthenticAMD-23-[012][0-9A-F] v2 amdzen1 core
50 AuthenticAMD-23-[[:xdigit:]]+ v1 amdzen2 core
51 AuthenticAMD-25-[[:xdigit:]]+ AuthenticAMD-25-[0245][[:xdigit:]] v1 amdzen3 core
52 AuthenticAMD-25-[[:xdigit:]]+ v1 amdzen4 core
53 HygonGenuine-24-00 v2 amdzen1 core