jimzah/freebsd-src
1
0
Fork 0
mirror of https://github.com/freebsd/freebsd-src.git synced 2024-11-28 19:52:44 +00:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

This is an MFC candidate.

Browse Source 
In our idle loop, use an or instruction to set PRELOADEN rather
than rewriting the contents of DMAPARAMS to DFCNTRL.  The later
may re-enable the DMA engine if the idle loop is called to complete
the preload of at least one segment when a target disconnects on
an S/G segment boundary but before we have completed fetching the
next segment.  This correts a hang, usually in message out phase,
when this situation occurs.  This bug has been here for a long
time, so the situation is rare, but not impossible to reproduce.
It only affected Ultra2/U160 controllers.

Correct a few comments.

Extra Sanity. Make sure that SCSIEN is also turned off, along with
HDMAEN, at the end of the data phase.
This commit is contained in:
Justin T. Gibbs 2001-03-20 04:37:19 +00:00
parent 2eacd2671d
commit 27bbd0d3ef
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=74507
1 changed files with 6 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
sys/dev/aic7xxx/aic7xxx.seq
View File

@ -28,7 +28,7 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: //depot/src/aic7xxx/aic7xxx.seq#23 $
* $Id: //depot/src/aic7xxx/aic7xxx.seq#24 $
*
* $FreeBSD$
*/
@ -758,8 +758,8 @@ idle_sg_avail:
test SCB_RESIDUAL_DATACNT[3], SG_LAST_SEG jz . + 2;
or SINDEX, LAST_SEG;
mov SG_CACHE_PRE, SINDEX;
/* Load the segment by writing DFCNTRL again */
mov DFCNTRL, DMAPARAMS;
/* Load the segment */
or DFCNTRL, PRELOADEN;
}
ret;
}
@ -948,7 +948,7 @@ ultra2_dmafifoempty:
test DFSTATUS, MREQPEND jnz ultra2_dmafifoempty;
ultra2_dmahalt:
and DFCNTRL, ~(SCSIEN|HDMAEN);
test DFCNTRL, HDMAEN jnz .;
test DFCNTRL, SCSIEN|HDMAEN jnz .;
/*
* If, by chance, we stopped before being able
@ -2068,7 +2068,7 @@ dma_scb_fromhost:
* latch is full.
*/
clr A;
/* Wait for some data to arrive. */
/* Wait for at least 8 bytes of data to arrive. */
dma_scb_hang_fifo:
test DFSTATUS, FIFOQWDEMP jnz dma_scb_hang_fifo;
dma_scb_hang_wait:
@ -2078,8 +2078,7 @@ dma_scb_hang_wait:
test DFSTATUS, HDONE jnz dma_scb_hang_dma_done;
/*
* The PCI module no longer intends to perform
* a PCI transaction and HDONE has not come true.
* We are hung. Drain the fifo.
* a PCI transaction. Drain the fifo.
*/
dma_scb_hang_empty_fifo:
/*