mirror of
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Add Marvell PHY support for 10/100/1000 LIVENGOOD_CU Intel NIC.
Parag Patel did all of the grunt work, so he gets the credit. Register definitions and actions inferred from a Linux driver, so Intel also gets some 'credit'.
This commit is contained in:
Matt Jacob
parent
a7aee8e14f
commit
2a4339f78f
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=75353
@ -367,6 +367,7 @@ dev/md/md.c optional md
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dev/mii/amphy.c optional miibus
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dev/mii/brgphy.c optional miibus
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dev/mii/dcphy.c optional miibus pci
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dev/mii/e1000phy.c optional miibus
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dev/mii/exphy.c optional miibus
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dev/mii/inphy.c optional miibus
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dev/mii/mii.c optional miibus
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473
sys/dev/mii/e1000phy.c
Normal file
473
sys/dev/mii/e1000phy.c
Normal file
@ -0,0 +1,473 @@
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/* $FreeBSD$ */
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/*
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* Principal Author: Parag Patel
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* Copyright (c) 2001
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Additonal Copyright (c) 2001 by Traakan Software under same licence.
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* Secondary Author: Matthew Jacob
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*/
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/*
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* driver for the Marvell 88E1000 series external 1000/100/10-BT PHY.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/socket.h>
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#include <sys/bus.h>
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#include <machine/clock.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/miidevs.h>
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#include <dev/mii/e1000phyreg.h>
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#include "miibus_if.h"
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static int e1000phy_probe(device_t);
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static int e1000phy_attach(device_t);
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static int e1000phy_detach(device_t);
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static device_method_t e1000phy_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, e1000phy_probe),
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DEVMETHOD(device_attach, e1000phy_attach),
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DEVMETHOD(device_detach, e1000phy_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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{ 0, 0 }
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};
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static devclass_t e1000phy_devclass;
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static driver_t e1000phy_driver = {
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"e1000phy", e1000phy_methods, sizeof (struct mii_softc)
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};
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DRIVER_MODULE(e1000phy, miibus, e1000phy_driver, e1000phy_devclass, 0, 0);
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int e1000phy_service(struct mii_softc *, struct mii_data *, int);
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void e1000phy_status(struct mii_softc *);
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static int e1000phy_mii_phy_auto(struct mii_softc *, int);
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extern void mii_phy_auto_timeout(void *);
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static void e1000phy_reset(struct mii_softc *);
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static int e1000phy_debug = 0;
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static int
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e1000phy_probe(device_t dev)
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{
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struct mii_attach_args *ma;
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u_int32_t id;
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ma = device_get_ivars(dev);
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id = ((ma->mii_id1 << 16) | ma->mii_id2) & E1000_ID_MASK;
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if (id != E1000_ID_88E1000 && id != E1000_ID_88E1000S) {
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return ENXIO;
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}
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device_set_desc(dev, MII_STR_MARVELL_E1000);
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return 0;
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}
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static int
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e1000phy_attach(device_t dev)
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{
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struct mii_softc *sc;
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struct mii_attach_args *ma;
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struct mii_data *mii;
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const char *sep = "";
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getenv_int("e1000phy_debug", &e1000phy_debug);
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sc = device_get_softc(dev);
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ma = device_get_ivars(dev);
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sc->mii_dev = device_get_parent(dev);
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mii = device_get_softc(sc->mii_dev);
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LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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sc->mii_service = e1000phy_service;
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sc->mii_pdata = mii;
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sc->mii_flags |= MIIF_NOISOLATE;
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mii->mii_instance++;
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e1000phy_reset(sc);
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#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
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#define PRINT(s) printf("%s%s", sep, s); sep = ", "
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#if 0
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
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E1000_CR_ISOLATE);
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#endif
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device_printf(dev, " ");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_TX, IFM_FDX, sc->mii_inst),
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E1000_CR_SPEED_1000 | E1000_CR_FULL_DUPLEX);
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PRINT("1000baseTX-FDX");
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/*
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TODO - apparently 1000BT-simplex not supported?
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_TX, 0, sc->mii_inst),
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E1000_CR_SPEED_1000);
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PRINT("1000baseTX");
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*/
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
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E1000_CR_SPEED_100 | E1000_CR_FULL_DUPLEX);
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PRINT("100baseTX-FDX");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst),
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E1000_CR_SPEED_100);
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PRINT("100baseTX");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
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E1000_CR_SPEED_10 | E1000_CR_FULL_DUPLEX);
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PRINT("10baseTX-FDX");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst),
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E1000_CR_SPEED_10);
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PRINT("10baseTX");
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ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
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PRINT("auto");
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printf("\n");
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#undef ADD
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#undef PRINT
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MIIBUS_MEDIAINIT(sc->mii_dev);
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return(0);
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}
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static int
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e1000phy_detach(device_t dev)
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{
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struct mii_softc *sc;
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struct mii_data *mii;
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sc = device_get_softc(dev);
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mii = device_get_softc(device_get_parent(dev));
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if (sc->mii_flags & MIIF_DOINGAUTO)
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untimeout(mii_phy_auto_timeout, sc, sc->mii_auto_ch);
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sc->mii_dev = NULL;
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LIST_REMOVE(sc, mii_list);
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return 0;
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}
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static void
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e1000phy_reset(struct mii_softc *sc)
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{
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u_int32_t reg;
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int i;
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/* initialize custom E1000 registers to magic values */
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reg = PHY_READ(sc, E1000_SCR);
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reg &= ~E1000_SCR_AUTO_X_MODE;
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PHY_WRITE(sc, E1000_SCR, reg);
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/* normal PHY reset */
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/*mii_phy_reset(sc);*/
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reg = PHY_READ(sc, E1000_CR);
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reg |= E1000_CR_RESET;
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PHY_WRITE(sc, E1000_CR, reg);
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for (i = 0; i < 500; i++) {
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DELAY(1);
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reg = PHY_READ(sc, E1000_CR);
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if (!(reg & E1000_CR_RESET))
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break;
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}
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/* set more custom E1000 registers to magic values */
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reg = PHY_READ(sc, E1000_SCR);
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reg |= E1000_SCR_ASSERT_CRS_ON_TX;
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PHY_WRITE(sc, E1000_SCR, reg);
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reg = PHY_READ(sc, E1000_ESCR);
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reg |= E1000_ESCR_TX_CLK_25;
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PHY_WRITE(sc, E1000_ESCR, reg);
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/* even more magic to reset DSP? */
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PHY_WRITE(sc, 29, 0x1d);
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PHY_WRITE(sc, 30, 0xc1);
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PHY_WRITE(sc, 30, 0x00);
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}
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int
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e1000phy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
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int reg;
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switch (cmd) {
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case MII_POLLSTAT:
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/*
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* If we're not polling our PHY instance, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst)
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return (0);
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break;
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case MII_MEDIACHG:
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/*
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* If the media indicates a different PHY instance,
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* isolate ourselves.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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reg = PHY_READ(sc, E1000_CR);
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PHY_WRITE(sc, E1000_CR, reg | E1000_CR_ISOLATE);
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return (0);
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}
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/*
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* If the interface is not up, don't do anything.
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0) {
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break;
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}
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switch (IFM_SUBTYPE(ife->ifm_media)) {
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case IFM_AUTO:
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/*
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* If we're already in auto mode, just return.
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*/
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if (sc->mii_flags & MIIF_DOINGAUTO) {
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return (0);
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}
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e1000phy_reset(sc);
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(void)e1000phy_mii_phy_auto(sc, 1);
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break;
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case IFM_1000_TX:
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if (sc->mii_flags & MIIF_DOINGAUTO)
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return (0);
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e1000phy_reset(sc);
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/* TODO - any other way to force 1000BT? */
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(void)e1000phy_mii_phy_auto(sc, 1);
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break;
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case IFM_100_TX:
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e1000phy_reset(sc);
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if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
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PHY_WRITE(sc, E1000_CR,
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E1000_CR_FULL_DUPLEX | E1000_CR_SPEED_100);
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PHY_WRITE(sc, E1000_AR, E1000_AR_100TX_FD);
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} else {
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PHY_WRITE(sc, E1000_CR, E1000_CR_SPEED_100);
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PHY_WRITE(sc, E1000_AR, E1000_AR_100TX);
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}
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break;
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case IFM_10_T:
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e1000phy_reset(sc);
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if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
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PHY_WRITE(sc, E1000_CR,
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E1000_CR_FULL_DUPLEX | E1000_CR_SPEED_10);
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PHY_WRITE(sc, E1000_AR, E1000_AR_10T_FD);
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} else {
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PHY_WRITE(sc, E1000_CR, E1000_CR_SPEED_10);
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PHY_WRITE(sc, E1000_AR, E1000_AR_10T);
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}
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break;
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default:
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return (EINVAL);
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}
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break;
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case MII_TICK:
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/*
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* If we're not currently selected, just return.
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*/
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if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
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return (0);
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}
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/*
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* Only used for autonegotiation.
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*/
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if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
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return (0);
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}
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/*
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* Is the interface even up?
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*/
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if ((mii->mii_ifp->if_flags & IFF_UP) == 0) {
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return (0);
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}
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/*
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* Only retry autonegotiation every 5 seconds.
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*/
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if (++(sc->mii_ticks) != 5) {
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return (0);
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}
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sc->mii_ticks = 0;
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/*
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* Check to see if we have link. If we do, we don't
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* need to restart the autonegotiation process. Read
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* the BMSR twice in case it's latched.
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*/
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reg = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
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if (reg & E1000_SR_LINK_STATUS)
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break;
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e1000phy_reset(sc);
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if (e1000phy_mii_phy_auto(sc, 0) == EJUSTRETURN) {
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return(0);
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}
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break;
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}
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/* Update the media status. */
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e1000phy_status(sc);
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/* Callback if something changed. */
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if (sc->mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) {
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MIIBUS_STATCHG(sc->mii_dev);
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sc->mii_active = mii->mii_media_active;
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}
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return (0);
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}
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void
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e1000phy_status(struct mii_softc *sc)
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{
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struct mii_data *mii = sc->mii_pdata;
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int bmsr, bmcr, esr, ssr, isr, ar, lpar;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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bmsr = PHY_READ(sc, E1000_SR) | PHY_READ(sc, E1000_SR);
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esr = PHY_READ(sc, E1000_ESR);
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bmcr = PHY_READ(sc, E1000_CR);
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ssr = PHY_READ(sc, E1000_SSR);
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isr = PHY_READ(sc, E1000_ISR);
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ar = PHY_READ(sc, E1000_AR);
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lpar = PHY_READ(sc, E1000_LPAR);
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if (bmsr & E1000_SR_LINK_STATUS)
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mii->mii_media_status |= IFM_ACTIVE;
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if (bmcr & E1000_CR_LOOPBACK)
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mii->mii_media_active |= IFM_LOOP;
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if ((sc->mii_flags & MIIF_DOINGAUTO) &&
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(!(bmsr & E1000_SR_AUTO_NEG_COMPLETE) || !(ssr & E1000_SSR_LINK) ||
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!(ssr & E1000_SSR_SPD_DPLX_RESOLVED))) {
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/* Erg, still trying, I guess... */
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mii->mii_media_active |= IFM_NONE;
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return;
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}
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if (ssr & E1000_SSR_1000MBS)
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mii->mii_media_active |= IFM_1000_TX;
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else if (ssr & E1000_SSR_100MBS)
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mii->mii_media_active |= IFM_100_TX;
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else
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mii->mii_media_active |= IFM_10_T;
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if (ssr & E1000_SSR_DUPLEX)
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mii->mii_media_active |= IFM_FDX;
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else
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mii->mii_media_active |= IFM_HDX;
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/* FLAG0==rx-flow-control FLAG1==tx-flow-control */
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if ((ar & E1000_AR_PAUSE) && (lpar & E1000_LPAR_PAUSE)) {
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mii->mii_media_active |= IFM_FLAG0 | IFM_FLAG1;
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} else if (!(ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
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(lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {
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mii->mii_media_active |= IFM_FLAG1;
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} else if ((ar & E1000_AR_PAUSE) && (ar & E1000_AR_ASM_DIR) &&
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!(lpar & E1000_LPAR_PAUSE) && (lpar & E1000_LPAR_ASM_DIR)) {
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mii->mii_media_active |= IFM_FLAG0;
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}
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}
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static int
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e1000phy_mii_phy_auto(struct mii_softc *mii, int waitfor)
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{
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int bmsr, i;
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if ((mii->mii_flags & MIIF_DOINGAUTO) == 0) {
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PHY_WRITE(mii, E1000_AR, E1000_AR_10T | E1000_AR_10T_FD |
|
||||
E1000_AR_100TX | E1000_AR_100TX_FD |
|
||||
E1000_AR_PAUSE | E1000_AR_ASM_DIR);
|
||||
PHY_WRITE(mii, E1000_1GCR, E1000_1GCR_1000T_FD);
|
||||
PHY_WRITE(mii, E1000_CR,
|
||||
E1000_CR_AUTO_NEG_ENABLE | E1000_CR_RESTART_AUTO_NEG);
|
||||
}
|
||||
|
||||
if (waitfor) {
|
||||
/* Wait 500ms for it to complete. */
|
||||
for (i = 0; i < 500; i++) {
|
||||
bmsr =
|
||||
PHY_READ(mii, E1000_SR) | PHY_READ(mii, E1000_SR);
|
||||
|
||||
if (bmsr & E1000_SR_AUTO_NEG_COMPLETE) {
|
||||
return (0);
|
||||
}
|
||||
DELAY(1000);
|
||||
}
|
||||
|
||||
/*
|
||||
* Don't need to worry about clearing MIIF_DOINGAUTO.
|
||||
* If that's set, a timeout is pending, and it will
|
||||
* clear the flag. [do it anyway]
|
||||
*/
|
||||
}
|
||||
|
||||
/*
|
||||
* Just let it finish asynchronously. This is for the benefit of
|
||||
* the tick handler driving autonegotiation. Don't want 500ms
|
||||
* delays all the time while the system is running!
|
||||
*/
|
||||
if ((mii->mii_flags & MIIF_DOINGAUTO) == 0) {
|
||||
mii->mii_flags |= MIIF_DOINGAUTO;
|
||||
mii->mii_ticks = 0;
|
||||
mii->mii_auto_ch = timeout(mii_phy_auto_timeout, mii, hz >> 1);
|
||||
}
|
||||
return (EJUSTRETURN);
|
||||
}
|
||||
286
sys/dev/mii/e1000phyreg.h
Normal file
286
sys/dev/mii/e1000phyreg.h
Normal file
@ -0,0 +1,286 @@
|
||||
/* $FreeBSD$ */
|
||||
/*
|
||||
* Principal Author: Parag Patel
|
||||
* Copyright (c) 2001
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice unmodified, this list of conditions, and the following
|
||||
* disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* Additonal Copyright (c) 2001 by Traakan Software under same licence.
|
||||
* Secondary Author: Matthew Jacob
|
||||
*/
|
||||
|
||||
/*
|
||||
* Derived by information released by Intel under the following license:
|
||||
*
|
||||
* Copyright (c) 1999 - 2001, Intel Corporation
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of Intel Corporation nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS''
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Marvell E1000 PHY registers
|
||||
*/
|
||||
|
||||
#define E1000_MAX_REG_ADDRESS 0x1F
|
||||
|
||||
#define E1000_CR 0x00 /* control register */
|
||||
#define E1000_CR_SPEED_SELECT_MSB 0x0040
|
||||
#define E1000_CR_COLL_TEST_ENABLE 0x0080
|
||||
#define E1000_CR_FULL_DUPLEX 0x0100
|
||||
#define E1000_CR_RESTART_AUTO_NEG 0x0200
|
||||
#define E1000_CR_ISOLATE 0x0400
|
||||
#define E1000_CR_POWER_DOWN 0x0800
|
||||
#define E1000_CR_AUTO_NEG_ENABLE 0x1000
|
||||
#define E1000_CR_SPEED_SELECT_LSB 0x2000
|
||||
#define E1000_CR_LOOPBACK 0x4000
|
||||
#define E1000_CR_RESET 0x8000
|
||||
|
||||
#define E1000_CR_SPEED_1000 0x0040
|
||||
#define E1000_CR_SPEED_100 0x2000
|
||||
#define E1000_CR_SPEED_10 0x0000
|
||||
|
||||
#define E1000_SR 0x01 /* status register */
|
||||
#define E1000_SR_EXTENDED 0x0001
|
||||
#define E1000_SR_JABBER_DETECT 0x0002
|
||||
#define E1000_SR_LINK_STATUS 0x0004
|
||||
#define E1000_SR_AUTO_NEG 0x0008
|
||||
#define E1000_SR_REMOTE_FAULT 0x0010
|
||||
#define E1000_SR_AUTO_NEG_COMPLETE 0x0020
|
||||
#define E1000_SR_PREAMBLE_SUPPRESS 0x0040
|
||||
#define E1000_SR_EXTENDED_STATUS 0x0100
|
||||
#define E1000_SR_100T2 0x0200
|
||||
#define E1000_SR_100T2_FD 0x0400
|
||||
#define E1000_SR_10T 0x0800
|
||||
#define E1000_SR_10T_FD 0x1000
|
||||
#define E1000_SR_100TX 0x2000
|
||||
#define E1000_SR_100TX_FD 0x4000
|
||||
#define E1000_SR_100T4 0x8000
|
||||
|
||||
#define E1000_ID1 0x02 /* ID register 1 */
|
||||
#define E1000_ID2 0x03 /* ID register 2 */
|
||||
#define E1000_ID_88E1000 0x01410C50
|
||||
#define E1000_ID_88E1000S 0x01410C40
|
||||
#define E1000_ID_MASK 0xFFFFFFF0
|
||||
|
||||
#define E1000_AR 0x04 /* autonegotiation advertise reg */
|
||||
#define E1000_AR_SELECTOR_FIELD 0x0001
|
||||
#define E1000_AR_10T 0x0020
|
||||
#define E1000_AR_10T_FD 0x0040
|
||||
#define E1000_AR_100TX 0x0080
|
||||
#define E1000_AR_100TX_FD 0x0100
|
||||
#define E1000_AR_100T4 0x0200
|
||||
#define E1000_AR_PAUSE 0x0400
|
||||
#define E1000_AR_ASM_DIR 0x0800
|
||||
#define E1000_AR_REMOTE_FAULT 0x2000
|
||||
#define E1000_AR_NEXT_PAGE 0x8000
|
||||
#define E1000_AR_SPEED_MASK 0x01E0
|
||||
|
||||
#define E1000_LPAR 0x05 /* autoneg link partner abilities reg */
|
||||
#define E1000_LPAR_SELECTOR_FIELD 0x0001
|
||||
#define E1000_LPAR_10T 0x0020
|
||||
#define E1000_LPAR_10T_FD 0x0040
|
||||
#define E1000_LPAR_100TX 0x0080
|
||||
#define E1000_LPAR_100TX_FD 0x0100
|
||||
#define E1000_LPAR_100T4 0x0200
|
||||
#define E1000_LPAR_PAUSE 0x0400
|
||||
#define E1000_LPAR_ASM_DIR 0x0800
|
||||
#define E1000_LPAR_REMOTE_FAULT 0x2000
|
||||
#define E1000_LPAR_ACKNOWLEDGE 0x4000
|
||||
#define E1000_LPAR_NEXT_PAGE 0x8000
|
||||
|
||||
#define E1000_ER 0x06 /* autoneg expansion reg */
|
||||
#define E1000_ER_LP_NWAY 0x0001
|
||||
#define E1000_ER_PAGE_RXD 0x0002
|
||||
#define E1000_ER_NEXT_PAGE 0x0004
|
||||
#define E1000_ER_LP_NEXT_PAGE 0x0008
|
||||
#define E1000_ER_PAR_DETECT_FAULT 0x0100
|
||||
|
||||
#define E1000_NPTX 0x07 /* autoneg next page TX */
|
||||
#define E1000_NPTX_MSG_CODE_FIELD 0x0001
|
||||
#define E1000_NPTX_TOGGLE 0x0800
|
||||
#define E1000_NPTX_ACKNOWLDGE2 0x1000
|
||||
#define E1000_NPTX_MSG_PAGE 0x2000
|
||||
#define E1000_NPTX_NEXT_PAGE 0x8000
|
||||
|
||||
#define E1000_RNPR 0x08 /* autoneg link-partner (?) next page */
|
||||
#define E1000_RNPR_MSG_CODE_FIELD 0x0001
|
||||
#define E1000_RNPR_TOGGLE 0x0800
|
||||
#define E1000_RNPR_ACKNOWLDGE2 0x1000
|
||||
#define E1000_RNPR_MSG_PAGE 0x2000
|
||||
#define E1000_RNPR_ACKNOWLDGE 0x4000
|
||||
#define E1000_RNPR_NEXT_PAGE 0x8000
|
||||
|
||||
#define E1000_1GCR 0x09 /* 1000T (1G) control reg */
|
||||
#define E1000_1GCR_ASYM_PAUSE 0x0080
|
||||
#define E1000_1GCR_1000T 0x0100
|
||||
#define E1000_1GCR_1000T_FD 0x0200
|
||||
#define E1000_1GCR_REPEATER_DTE 0x0400
|
||||
#define E1000_1GCR_MS_VALUE 0x0800
|
||||
#define E1000_1GCR_MS_ENABLE 0x1000
|
||||
#define E1000_1GCR_TEST_MODE_NORMAL 0x0000
|
||||
#define E1000_1GCR_TEST_MODE_1 0x2000
|
||||
#define E1000_1GCR_TEST_MODE_2 0x4000
|
||||
#define E1000_1GCR_TEST_MODE_3 0x6000
|
||||
#define E1000_1GCR_TEST_MODE_4 0x8000
|
||||
#define E1000_1GCR_SPEED_MASK 0x0300
|
||||
|
||||
#define E1000_1GSR 0x0A /* 1000T (1G) status reg */
|
||||
#define E1000_1GSR_IDLE_ERROR_CNT 0x0000
|
||||
#define E1000_1GSR_ASYM_PAUSE_DIR 0x0100
|
||||
#define E1000_1GSR_LP 0x0400
|
||||
#define E1000_1GSR_LP_FD 0x0800
|
||||
#define E1000_1GSR_REMOTE_RX_STATUS 0x1000
|
||||
#define E1000_1GSR_LOCAL_RX_STATUS 0x2000
|
||||
#define E1000_1GSR_MS_CONFIG_RES 0x4000
|
||||
#define E1000_1GSR_MS_CONFIG_FAULT 0x8000
|
||||
|
||||
#define E1000_ESR 0x0F /* IEEE extended status reg */
|
||||
#define E1000_ESR_1000T 0x1000
|
||||
#define E1000_ESR_1000T_FD 0x2000
|
||||
#define E1000_ESR_1000X 0x4000
|
||||
#define E1000_ESR_1000X_FD 0x8000
|
||||
|
||||
#define E1000_TX_POLARITY_MASK 0x0100
|
||||
#define E1000_TX_NORMAL_POLARITY 0
|
||||
|
||||
#define E1000_AUTO_POLARITY_DISABLE 0x0010
|
||||
|
||||
#define E1000_SCR 0x10 /* special control register */
|
||||
#define E1000_SCR_JABBER_DISABLE 0x0001
|
||||
#define E1000_SCR_POLARITY_REVERSAL 0x0002
|
||||
#define E1000_SCR_SQE_TEST 0x0004
|
||||
#define E1000_SCR_INT_FIFO_DISABLE 0x0008
|
||||
#define E1000_SCR_CLK125_DISABLE 0x0010
|
||||
#define E1000_SCR_MDI_MANUAL_MODE 0x0000
|
||||
#define E1000_SCR_MDIX_MANUAL_MODE 0x0020
|
||||
#define E1000_SCR_AUTO_X_1000T 0x0040
|
||||
#define E1000_SCR_AUTO_X_MODE 0x0060
|
||||
#define E1000_SCR_10BT_EXT_ENABLE 0x0080
|
||||
#define E1000_SCR_MII_5BIT_ENABLE 0x0100
|
||||
#define E1000_SCR_SCRAMBLER_DISABLE 0x0200
|
||||
#define E1000_SCR_FORCE_LINK_GOOD 0x0400
|
||||
#define E1000_SCR_ASSERT_CRS_ON_TX 0x0800
|
||||
#define E1000_SCR_RX_FIFO_DEPTH_6 0x0000
|
||||
#define E1000_SCR_RX_FIFO_DEPTH_8 0x1000
|
||||
#define E1000_SCR_RX_FIFO_DEPTH_10 0x2000
|
||||
#define E1000_SCR_RX_FIFO_DEPTH_12 0x3000
|
||||
#define E1000_SCR_TX_FIFO_DEPTH_6 0x0000
|
||||
#define E1000_SCR_TX_FIFO_DEPTH_8 0x4000
|
||||
#define E1000_SCR_TX_FIFO_DEPTH_10 0x8000
|
||||
#define E1000_SCR_TX_FIFO_DEPTH_12 0xC000
|
||||
|
||||
#define E1000_SSR 0x11 /* special status register */
|
||||
#define E1000_SSR_JABBER 0x0001
|
||||
#define E1000_SSR_REV_POLARITY 0x0002
|
||||
#define E1000_SSR_MDIX 0x0020
|
||||
#define E1000_SSR_LINK 0x0400
|
||||
#define E1000_SSR_SPD_DPLX_RESOLVED 0x0800
|
||||
#define E1000_SSR_PAGE_RCVD 0x1000
|
||||
#define E1000_SSR_DUPLEX 0x2000
|
||||
#define E1000_SSR_SPEED 0xC000
|
||||
#define E1000_SSR_10MBS 0x0000
|
||||
#define E1000_SSR_100MBS 0x4000
|
||||
#define E1000_SSR_1000MBS 0x8000
|
||||
|
||||
#define E1000_IER 0x12 /* interrupt enable reg */
|
||||
#define E1000_IER_JABBER 0x0001
|
||||
#define E1000_IER_POLARITY_CHANGE 0x0002
|
||||
#define E1000_IER_MDIX_CHANGE 0x0040
|
||||
#define E1000_IER_FIFO_OVER_UNDERUN 0x0080
|
||||
#define E1000_IER_FALSE_CARRIER 0x0100
|
||||
#define E1000_IER_SYMBOL_ERROR 0x0200
|
||||
#define E1000_IER_LINK_STAT_CHANGE 0x0400
|
||||
#define E1000_IER_AUTO_NEG_COMPLETE 0x0800
|
||||
#define E1000_IER_PAGE_RECEIVED 0x1000
|
||||
#define E1000_IER_DUPLEX_CHANGED 0x2000
|
||||
#define E1000_IER_SPEED_CHANGED 0x4000
|
||||
#define E1000_IER_AUTO_NEG_ERR 0x8000
|
||||
|
||||
#define E1000_ISR 0x13 /* interrupt status reg */
|
||||
#define E1000_ISR_JABBER 0x0001
|
||||
#define E1000_ISR_POLARITY_CHANGE 0x0002
|
||||
#define E1000_ISR_MDIX_CHANGE 0x0040
|
||||
#define E1000_ISR_FIFO_OVER_UNDERUN 0x0080
|
||||
#define E1000_ISR_FALSE_CARRIER 0x0100
|
||||
#define E1000_ISR_SYMBOL_ERROR 0x0200
|
||||
#define E1000_ISR_LINK_STAT_CHANGE 0x0400
|
||||
#define E1000_ISR_AUTO_NEG_COMPLETE 0x0800
|
||||
#define E1000_ISR_PAGE_RECEIVED 0x1000
|
||||
#define E1000_ISR_DUPLEX_CHANGED 0x2000
|
||||
#define E1000_ISR_SPEED_CHANGED 0x4000
|
||||
#define E1000_ISR_AUTO_NEG_ERR 0x8000
|
||||
|
||||
#define E1000_ESCR 0x14 /* extended special control reg */
|
||||
#define E1000_ESCR_FIBER_LOOPBACK 0x4000
|
||||
#define E1000_ESCR_DOWN_NO_IDLE 0x8000
|
||||
#define E1000_ESCR_TX_CLK_2_5 0x0060
|
||||
#define E1000_ESCR_TX_CLK_25 0x0070
|
||||
#define E1000_ESCR_TX_CLK_0 0x0000
|
||||
|
||||
#define E1000_RECR 0x15 /* RX error counter reg */
|
||||
|
||||
#define E1000_LCR 0x18 /* LED control reg */
|
||||
#define E1000_LCR_LED_TX 0x0001
|
||||
#define E1000_LCR_LED_RX 0x0002
|
||||
#define E1000_LCR_LED_DUPLEX 0x0004
|
||||
#define E1000_LCR_LINK 0x0008
|
||||
#define E1000_LCR_BLINK_42MS 0x0000
|
||||
#define E1000_LCR_BLINK_84MS 0x0100
|
||||
#define E1000_LCR_BLINK_170MS 0x0200
|
||||
#define E1000_LCR_BLINK_340MS 0x0300
|
||||
#define E1000_LCR_BLINK_670MS 0x0400
|
||||
#define E1000_LCR_PULSE_OFF 0x0000
|
||||
#define E1000_LCR_PULSE_21_42MS 0x1000
|
||||
#define E1000_LCR_PULSE_42_84MS 0x2000
|
||||
#define E1000_LCR_PULSE_84_170MS 0x3000
|
||||
#define E1000_LCR_PULSE_170_340MS 0x4000
|
||||
#define E1000_LCR_PULSE_340_670MS 0x5000
|
||||
#define E1000_LCR_PULSE_670_13S 0x6000
|
||||
#define E1000_LCR_PULSE_13_26S 0x7000
|
||||
@ -63,6 +63,7 @@ oui SIS 0x00e006 Silicon Integrated Systems
|
||||
oui TDK 0x00c039 TDK
|
||||
oui TI 0x080028 Texas Instruments
|
||||
oui XAQTI 0x00e0ae XaQti Corp.
|
||||
oui MARVELL 0x005043 Marvell Semiconductor
|
||||
|
||||
/* in the 79c873, AMD uses another OUI (which matches Davicom!) */
|
||||
oui xxAMD 0x00606e Advanced Micro Devices
|
||||
@ -141,3 +142,6 @@ model xxTI 100VGPMI 0x0002 ThunderLAN 100VG-AnyLan media interface
|
||||
|
||||
/* XaQti Corp. PHYs. */
|
||||
model XAQTI XMACII 0x0000 XaQti Corp. XMAC II gigabit interface
|
||||
|
||||
/* Marvell Semiconductor PHYs */
|
||||
model MARVELL E1000 0x0000 Marvell Semiconductor 88E1000* gigabit PHY
|
||||
|
||||
@ -70,6 +70,7 @@
|
||||
#define MII_OUI_TDK 0x00c039 /* TDK */
|
||||
#define MII_OUI_TI 0x080028 /* Texas Instruments */
|
||||
#define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */
|
||||
#define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */
|
||||
|
||||
/* in the 79c873, AMD uses another OUI (which matches Davicom!) */
|
||||
#define MII_OUI_xxAMD 0x00606e /* Advanced Micro Devices */
|
||||
@ -170,3 +171,7 @@
|
||||
/* XaQti Corp. PHYs. */
|
||||
#define MII_MODEL_XAQTI_XMACII 0x0000
|
||||
#define MII_STR_XAQTI_XMACII "XaQti Corp. XMAC II gigabit interface"
|
||||
|
||||
/* Marvell Semiconductor PHYs */
|
||||
#define MII_MODEL_MARVELL_E1000 0x0000
|
||||
#define MII_STR_MARVELL_E1000 "Marvell Semiconductor 88E1000* gigabit PHY"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user