mirror of
https://github.com/freebsd/freebsd-src.git
synced 2024-12-04 10:19:26 +00:00
- Handle multiphy MAC case: create interface with
fixed-state media with parameters set via hints
and configure MAC accordingly to these parameters.
All the underlying PHY magic is done by boot manager
on startup. At the moment there is no proper way
to make active and control all PHYs simultaneously
from one MII bus and there is no way to associate
incoming/outgoing packet with specific PHY.
This commit is contained in:
Oleksandr Tymoshenko
parent
445ee40baa
commit
2b8344b8fa
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/projects/mips/; revision=199234
@ -95,6 +95,7 @@ static int arge_ioctl(struct ifnet *, u_long, caddr_t);
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static void arge_init(void *);
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static void arge_init_locked(struct arge_softc *);
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static void arge_link_task(void *, int);
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static void arge_set_pll(struct arge_softc *, int, int);
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static int arge_miibus_readreg(device_t, int, int);
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static void arge_miibus_statchg(device_t);
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static int arge_miibus_writereg(device_t, int, int, int);
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@ -118,6 +119,12 @@ static void arge_intr(void *);
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static int arge_intr_filter(void *);
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static void arge_tick(void *);
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/*
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* ifmedia callbacks for multiPHY MAC
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*/
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void arge_multiphy_mediastatus(struct ifnet *, struct ifmediareq *);
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int arge_multiphy_mediachange(struct ifnet *);
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static void arge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
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static int arge_dma_alloc(struct arge_softc *);
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static void arge_dma_free(struct arge_softc *);
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@ -197,9 +204,10 @@ arge_attach(device_t dev)
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uint8_t eaddr[ETHER_ADDR_LEN];
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struct ifnet *ifp;
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struct arge_softc *sc;
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int error = 0, rid, phynum;
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int error = 0, rid, phymask;
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uint32_t reg, rnd;
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int is_base_mac_empty, i;
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int is_base_mac_empty, i, phys_total;
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uint32_t hint;
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sc = device_get_softc(dev);
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sc->arge_dev = dev;
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@ -221,20 +229,43 @@ arge_attach(device_t dev)
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* Get which PHY of 5 available we should use for this unit
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*/
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if (resource_int_value(device_get_name(dev), device_get_unit(dev),
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"phy", &phynum) != 0) {
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"phymask", &phymask) != 0) {
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/*
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* Use port 4 (WAN) for GE0. For any other port use
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* its PHY the same as its unit number
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*/
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if (sc->arge_mac_unit == 0)
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phynum = 4;
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phymask = (1 << 4);
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else
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phynum = sc->arge_mac_unit;
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/* Use all phys up to 4 */
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phymask = (1 << 4) - 1;
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device_printf(dev, "No PHY specified, using %d\n", phynum);
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device_printf(dev, "No PHY specified, using mask %d\n", phymask);
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}
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sc->arge_phy_num = phynum;
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/*
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* Get default media & duplex mode, by default its Base100T
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* and full duplex
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*/
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if (resource_int_value(device_get_name(dev), device_get_unit(dev),
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"media", &hint) != 0)
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hint = 0;
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if (hint == 1000)
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sc->arge_media_type = IFM_1000_T;
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else
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sc->arge_media_type = IFM_100_TX;
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if (resource_int_value(device_get_name(dev), device_get_unit(dev),
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"fduplex", &hint) != 0)
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hint = 1;
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if (hint)
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sc->arge_duplex_mode = IFM_FDX;
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else
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sc->arge_duplex_mode = 0;
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sc->arge_phymask = phymask;
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mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
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MTX_DEF);
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@ -379,14 +410,40 @@ arge_attach(device_t dev)
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ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
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FIFO_RX_FILTMASK_DEFAULT);
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/* Do MII setup. */
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if (mii_phy_probe(dev, &sc->arge_miibus,
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arge_ifmedia_upd, arge_ifmedia_sts)) {
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device_printf(dev, "MII without any phy!\n");
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error = ENXIO;
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/*
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* Check if we have single-PHY MAC or multi-PHY
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*/
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phys_total = 0;
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for (i = 0; i < ARGE_NPHY; i++)
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if (phymask & (1 << i))
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phys_total ++;
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if (phys_total == 0) {
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error = EINVAL;
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goto fail;
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}
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if (phys_total == 1) {
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/* Do MII setup. */
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if (mii_phy_probe(dev, &sc->arge_miibus,
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arge_ifmedia_upd, arge_ifmedia_sts)) {
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device_printf(dev, "MII without any phy!\n");
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error = ENXIO;
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goto fail;
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}
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}
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else {
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ifmedia_init(&sc->arge_ifmedia, 0,
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arge_multiphy_mediachange,
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arge_multiphy_mediastatus);
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ifmedia_add(&sc->arge_ifmedia,
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IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode,
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0, NULL);
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ifmedia_set(&sc->arge_ifmedia,
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IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode);
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arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode);
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}
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/* Call MI attach routine. */
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ether_ifattach(ifp, eaddr);
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@ -432,6 +489,7 @@ arge_detach(device_t dev)
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if (sc->arge_miibus)
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device_delete_child(dev, sc->arge_miibus);
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bus_generic_detach(dev);
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if (sc->arge_intrhand)
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@ -490,7 +548,7 @@ arge_miibus_readreg(device_t dev, int phy, int reg)
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uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT)
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| (reg & MAC_MII_REG_MASK);
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if (phy != sc->arge_phy_num)
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if ((sc->arge_phymask & (1 << phy)) == 0)
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return (0);
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mtx_lock(&miibus_mtx);
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@ -529,7 +587,7 @@ arge_miibus_writereg(device_t dev, int phy, int reg, int data)
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(phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK);
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if (phy != sc->arge_phy_num)
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if ((sc->arge_phymask & (1 << phy)) == 0)
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return (-1);
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dprintf("%s: phy=%d, reg=%02x, value=%04x\n", __func__,
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@ -570,8 +628,7 @@ arge_link_task(void *arg, int pending)
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struct arge_softc *sc;
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struct mii_data *mii;
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struct ifnet *ifp;
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uint32_t media;
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uint32_t cfg, ifcontrol, rx_filtmask, pll, sec_cfg;
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uint32_t media, duplex;
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sc = (struct arge_softc *)arg;
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@ -590,68 +647,8 @@ arge_link_task(void *arg, int pending)
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if (media != IFM_NONE) {
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sc->arge_link_status = 1;
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cfg = ARGE_READ(sc, AR71XX_MAC_CFG2);
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cfg &= ~(MAC_CFG2_IFACE_MODE_1000
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| MAC_CFG2_IFACE_MODE_10_100
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| MAC_CFG2_FULL_DUPLEX);
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if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
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cfg |= MAC_CFG2_FULL_DUPLEX;
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ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL);
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ifcontrol &= ~MAC_IFCONTROL_SPEED;
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rx_filtmask =
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ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK);
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rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE;
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switch(media) {
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case IFM_10_T:
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cfg |= MAC_CFG2_IFACE_MODE_10_100;
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pll = PLL_ETH_INT_CLK_10;
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break;
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case IFM_100_TX:
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cfg |= MAC_CFG2_IFACE_MODE_10_100;
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ifcontrol |= MAC_IFCONTROL_SPEED;
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pll = PLL_ETH_INT_CLK_100;
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break;
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case IFM_1000_T:
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case IFM_1000_SX:
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cfg |= MAC_CFG2_IFACE_MODE_1000;
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rx_filtmask |= FIFO_RX_MASK_BYTE_MODE;
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pll = PLL_ETH_INT_CLK_1000;
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break;
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default:
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pll = PLL_ETH_INT_CLK_100;
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device_printf(sc->arge_dev,
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"Unknown media %d\n", media);
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}
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ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD,
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0x008001ff);
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ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg);
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ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol);
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ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
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rx_filtmask);
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/* set PLL registers */
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sec_cfg = ATH_READ_REG(AR71XX_PLL_SEC_CONFIG);
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sec_cfg &= ~(3 << sc->arge_pll_reg_shift);
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sec_cfg |= (2 << sc->arge_pll_reg_shift);
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ATH_WRITE_REG(AR71XX_PLL_SEC_CONFIG, sec_cfg);
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DELAY(100);
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ATH_WRITE_REG(sc->arge_pll_reg, pll);
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sec_cfg |= (3 << sc->arge_pll_reg_shift);
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ATH_WRITE_REG(AR71XX_PLL_SEC_CONFIG, sec_cfg);
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DELAY(100);
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sec_cfg &= ~(3 << sc->arge_pll_reg_shift);
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ATH_WRITE_REG(AR71XX_PLL_SEC_CONFIG, sec_cfg);
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DELAY(100);
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duplex = mii->mii_media_active & IFM_GMASK;
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arge_set_pll(sc, media, duplex);
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}
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} else
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sc->arge_link_status = 0;
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@ -659,6 +656,75 @@ arge_link_task(void *arg, int pending)
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ARGE_UNLOCK(sc);
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}
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static void
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arge_set_pll(struct arge_softc *sc, int media, int duplex)
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{
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uint32_t cfg, ifcontrol, rx_filtmask, pll, sec_cfg;
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cfg = ARGE_READ(sc, AR71XX_MAC_CFG2);
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cfg &= ~(MAC_CFG2_IFACE_MODE_1000
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| MAC_CFG2_IFACE_MODE_10_100
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| MAC_CFG2_FULL_DUPLEX);
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if (duplex == IFM_FDX)
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cfg |= MAC_CFG2_FULL_DUPLEX;
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ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL);
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ifcontrol &= ~MAC_IFCONTROL_SPEED;
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rx_filtmask =
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ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK);
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rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE;
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switch(media) {
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case IFM_10_T:
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cfg |= MAC_CFG2_IFACE_MODE_10_100;
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pll = PLL_ETH_INT_CLK_10;
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break;
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case IFM_100_TX:
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cfg |= MAC_CFG2_IFACE_MODE_10_100;
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ifcontrol |= MAC_IFCONTROL_SPEED;
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pll = PLL_ETH_INT_CLK_100;
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break;
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case IFM_1000_T:
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case IFM_1000_SX:
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cfg |= MAC_CFG2_IFACE_MODE_1000;
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rx_filtmask |= FIFO_RX_MASK_BYTE_MODE;
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pll = PLL_ETH_INT_CLK_1000;
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break;
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default:
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pll = PLL_ETH_INT_CLK_100;
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device_printf(sc->arge_dev,
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"Unknown media %d\n", media);
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}
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ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD,
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0x008001ff);
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ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg);
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ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol);
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ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK,
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rx_filtmask);
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/* set PLL registers */
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sec_cfg = ATH_READ_REG(AR71XX_PLL_SEC_CONFIG);
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sec_cfg &= ~(3 << sc->arge_pll_reg_shift);
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sec_cfg |= (2 << sc->arge_pll_reg_shift);
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ATH_WRITE_REG(AR71XX_PLL_SEC_CONFIG, sec_cfg);
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DELAY(100);
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ATH_WRITE_REG(sc->arge_pll_reg, pll);
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sec_cfg |= (3 << sc->arge_pll_reg_shift);
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ATH_WRITE_REG(AR71XX_PLL_SEC_CONFIG, sec_cfg);
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DELAY(100);
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sec_cfg &= ~(3 << sc->arge_pll_reg_shift);
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ATH_WRITE_REG(AR71XX_PLL_SEC_CONFIG, sec_cfg);
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DELAY(100);
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}
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static void
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arge_reset_dma(struct arge_softc *sc)
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{
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@ -707,8 +773,6 @@ arge_init_locked(struct arge_softc *sc)
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ARGE_LOCK_ASSERT(sc);
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mii = device_get_softc(sc->arge_miibus);
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arge_stop(sc);
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/* Init circular RX list. */
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@ -724,13 +788,24 @@ arge_init_locked(struct arge_softc *sc)
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arge_reset_dma(sc);
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sc->arge_link_status = 0;
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mii_mediachg(mii);
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if (sc->arge_miibus) {
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sc->arge_link_status = 0;
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mii = device_get_softc(sc->arge_miibus);
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mii_mediachg(mii);
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}
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else {
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/*
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* Sun always shines over multiPHY interface
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*/
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sc->arge_link_status = 1;
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}
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ifp->if_drv_flags |= IFF_DRV_RUNNING;
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
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callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
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if (sc->arge_miibus)
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callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
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ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0));
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ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0));
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@ -899,7 +974,8 @@ arge_stop(struct arge_softc *sc)
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ifp = sc->arge_ifp;
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ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
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callout_stop(&sc->arge_stat_callout);
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if (sc->arge_miibus)
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callout_stop(&sc->arge_stat_callout);
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/* mask out interrupts */
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ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
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@ -948,8 +1024,12 @@ arge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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break;
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case SIOCGIFMEDIA:
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case SIOCSIFMEDIA:
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mii = device_get_softc(sc->arge_miibus);
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error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
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if (sc->arge_miibus) {
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mii = device_get_softc(sc->arge_miibus);
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error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
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}
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else
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error = ifmedia_ioctl(ifp, ifr, &sc->arge_ifmedia, command);
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break;
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case SIOCSIFCAP:
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/* XXX: Check other capabilities */
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@ -1690,7 +1770,42 @@ arge_tick(void *xsc)
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ARGE_LOCK_ASSERT(sc);
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mii = device_get_softc(sc->arge_miibus);
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mii_tick(mii);
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callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
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if (sc->arge_miibus) {
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mii = device_get_softc(sc->arge_miibus);
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mii_tick(mii);
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callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
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}
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}
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int
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arge_multiphy_mediachange(struct ifnet *ifp)
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{
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struct arge_softc *sc = ifp->if_softc;
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struct ifmedia *ifm = &sc->arge_ifmedia;
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struct ifmedia_entry *ife = ifm->ifm_cur;
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if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
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return (EINVAL);
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if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
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device_printf(sc->arge_dev,
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"AUTO is not supported for multiphy MAC");
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return (EINVAL);
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}
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/*
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* Ignore everything
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*/
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return (0);
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}
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void
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arge_multiphy_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
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{
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struct arge_softc *sc = ifp->if_softc;
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ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
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ifmr->ifm_active = IFM_ETHER | sc->arge_media_type |
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sc->arge_duplex_mode;
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}
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@ -28,6 +28,7 @@
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#ifndef __IF_ARGEVAR_H__
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#define __IF_ARGEVAR_H__
|
||||
|
||||
#define ARGE_NPHY 32
|
||||
#define ARGE_TX_RING_COUNT 128
|
||||
#define ARGE_RX_RING_COUNT 128
|
||||
#define ARGE_RX_DMA_SIZE ARGE_RX_RING_COUNT * sizeof(struct arge_desc)
|
||||
@ -124,6 +125,12 @@ struct arge_ring_data {
|
||||
struct arge_softc {
|
||||
struct ifnet *arge_ifp; /* interface info */
|
||||
device_t arge_dev;
|
||||
struct ifmedia arge_ifmedia;
|
||||
/*
|
||||
* Media & duples settings for multiPHY MAC
|
||||
*/
|
||||
uint32_t arge_media_type;
|
||||
uint32_t arge_duplex_mode;
|
||||
struct resource *arge_res;
|
||||
int arge_rid;
|
||||
struct resource *arge_irq;
|
||||
@ -140,7 +147,7 @@ struct arge_softc {
|
||||
int arge_detach;
|
||||
uint32_t arge_intr_status;
|
||||
int arge_mac_unit;
|
||||
int arge_phy_num;
|
||||
int arge_phymask;
|
||||
uint32_t arge_ddr_flush_reg;
|
||||
uint32_t arge_pll_reg;
|
||||
uint32_t arge_pll_reg_shift;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user