mirror of
https://github.com/freebsd/freebsd-src.git
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Some more i386-only BIOS-friendliness:
- Add support for using the PCI BIOS functions for configuration space accesses, and make this the default. - Make PNPBIOS the default (obsoletes the PNPBIOS config option). - Add two new boot-time tunables to disable each of the above.
This commit is contained in:
Mike Smith
parent
27322174cd
commit
300451c472
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=59294
@ -31,8 +31,6 @@
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* Code for dealing with the BIOS in x86 PC systems.
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*/
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#include "opt_pnp.h"
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#include "isa.h"
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#include <sys/param.h>
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@ -79,9 +77,10 @@ bios32_init(void *junk)
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struct PnPBIOS_table *pt;
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u_int8_t ck, *cv;
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int i;
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char *p;
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/*
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* BIOS32 Service Directory
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* BIOS32 Service Directory, PCI BIOS
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*/
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/* look for the signature */
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@ -100,10 +99,15 @@ bios32_init(void *junk)
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printf("bios32: Entry = 0x%x (%x) Rev = %d Len = %d\n",
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sdh->entry, bios32_SDCI, sdh->revision, sdh->len);
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}
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/* See if there's a PCI BIOS entrypoint here */
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PCIbios.ident.id = 0x49435024; /* PCI systems should have this */
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if (!bios32_SDlookup(&PCIbios) && bootverbose)
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printf("pcibios: PCI BIOS entry at 0x%x\n", PCIbios.entry);
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/* Allow user override of PCI BIOS search */
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if (((p = getenv("machdep.bios.pci")) == NULL) || strcmp(p, "disable")) {
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/* See if there's a PCI BIOS entrypoint here */
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PCIbios.ident.id = 0x49435024; /* PCI systems should have this */
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if (!bios32_SDlookup(&PCIbios) && bootverbose)
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printf("pcibios: PCI BIOS entry at 0x%x+0x%x\n", PCIbios.base, PCIbios.entry);
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}
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} else {
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printf("bios32: Bad BIOS32 Service Directory\n");
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}
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@ -111,8 +115,11 @@ bios32_init(void *junk)
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/*
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* PnP BIOS
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*
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* Allow user override of PnP BIOS search
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*/
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if ((sigaddr = bios_sigsearch(0, "$PnP", 4, 16, 0)) != 0) {
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if ((((p = getenv("machdep.bios.pnp")) == NULL) || strcmp(p, "disable")) &&
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((sigaddr = bios_sigsearch(0, "$PnP", 4, 16, 0)) != 0)) {
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/* get a virtual pointer to the structure */
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pt = (struct PnPBIOS_table *)(uintptr_t)BIOS_PADDRTOVADDR(sigaddr);
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@ -166,6 +173,7 @@ bios32_SDlookup(struct bios32_SDentry *ent)
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ent->base = args.ebx;
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ent->len = args.ecx;
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ent->entry = args.edx;
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ent->ventry = BIOS_PADDRTOVADDR(ent->base + ent->entry);
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return (0); /* all OK */
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}
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return (1); /* failed */
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@ -454,8 +462,6 @@ bios16(struct bios_args *args, char *fmt, ...)
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return (i);
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}
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#ifdef PNPBIOS /* remove conditional later */
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/*
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* PnP BIOS interface; enumerate devices only known to the system
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* BIOS and save information about them for later use.
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@ -518,7 +524,7 @@ pnpbios_identify(driver_t *driver, device_t parent)
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/* no PnP BIOS information */
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if (pt == NULL)
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return;
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bzero(&args, sizeof(args));
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args.seg.code16.base = BIOS_PADDRTOVADDR(pt->pmentrybase);
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args.seg.code16.limit = 0xffff; /* XXX ? */
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@ -623,5 +629,3 @@ static driver_t pnpbios_driver = {
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static devclass_t pnpbios_devclass;
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DRIVER_MODULE(pnpbios, isa, pnpbios_driver, pnpbios_devclass, 0, 0);
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#endif /* PNPBIOS */
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@ -54,6 +54,7 @@ struct bios32_SDentry
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u_int32_t base; /* base of service */
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u_int32_t len; /* service length */
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u_int32_t entry; /* entrypoint offset from base */
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vm_offset_t ventry; /* entrypoint in kernel virtual segment */
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};
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extern int bios32_SDlookup(struct bios32_SDentry *ent);
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@ -203,6 +204,16 @@ struct bios_args {
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#define PNP_GET_BOOTFIRST "sp", 0x65
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#define PNP_SET_BOOTFIRST "sp", 0x66
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/*
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* PCI BIOS functions
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*/
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#define PCIBIOS_READ_CONFIG_BYTE 0xb108
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#define PCIBIOS_READ_CONFIG_WORD 0xb109
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#define PCIBIOS_READ_CONFIG_DWORD 0xb10a
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#define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b
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#define PCIBIOS_WRITE_CONFIG_WORD 0xb10c
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#define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d
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extern int bios16(struct bios_args *, char *, ...);
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extern int bios16_call(struct bios_regs *, char *);
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extern int bios32(struct bios_regs *, u_int, u_short);
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@ -36,8 +36,115 @@
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#include <pci/pcireg.h>
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#include <i386/isa/pcibus.h>
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#include <machine/segments.h>
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#include <machine/pc/bios.h>
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static int cfgmech;
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static int devmax;
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static int usebios;
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static int pcibios_cfgread(pcicfgregs *cfg, int reg, int bytes);
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static void pcibios_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes);
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static int pcibios_cfgopen(void);
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static int pcireg_cfgread(pcicfgregs *cfg, int reg, int bytes);
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static void pcireg_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes);
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static int pcireg_cfgopen(void);
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/* read configuration space register */
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int
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pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
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{
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return(usebios ?
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pcibios_cfgread(cfg, reg, bytes) :
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pcireg_cfgread(cfg, reg, bytes));
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}
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/* write configuration space register */
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void
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pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
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{
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return(usebios ?
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pcibios_cfgwrite(cfg, reg, data, bytes) :
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pcireg_cfgwrite(cfg, reg, data, bytes));
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}
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/* initialise access to PCI configuration space */
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static int
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pci_cfgopen(void)
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{
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if (pcibios_cfgopen() != 0) {
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usebios = 1;
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} else if (pcireg_cfgopen() != 0) {
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usebios = 0;
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} else {
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return(0);
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}
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return(1);
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}
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/* config space access using BIOS functions */
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static int
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pcibios_cfgread(pcicfgregs *cfg, int reg, int bytes)
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{
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struct bios_regs args;
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switch(bytes) {
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case 1:
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args.eax = PCIBIOS_READ_CONFIG_BYTE;
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break;
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case 2:
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args.eax = PCIBIOS_READ_CONFIG_WORD;
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break;
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case 4:
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args.eax = PCIBIOS_READ_CONFIG_DWORD;
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break;
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default:
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return(-1);
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}
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args.ebx = (cfg->bus << 8) | (cfg->slot << 3) | (cfg->func);
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args.edi = reg;
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bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
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/* check call results? */
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return(args.ecx);
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}
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static void
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pcibios_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
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{
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struct bios_regs args;
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switch(bytes) {
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case 1:
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args.eax = PCIBIOS_WRITE_CONFIG_BYTE;
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break;
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case 2:
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args.eax = PCIBIOS_WRITE_CONFIG_WORD;
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break;
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case 4:
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args.eax = PCIBIOS_WRITE_CONFIG_DWORD;
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break;
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default:
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return;
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}
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args.ebx = (cfg->bus << 8) | (cfg->slot << 3) | (cfg->func);
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args.ecx = data;
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args.edi = reg;
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bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
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}
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/* determine whether there is a PCI BIOS present */
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static int
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pcibios_cfgopen(void)
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{
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/* check for a found entrypoint */
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return(PCIbios.entry != 0);
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}
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/* configuration space access using direct register operations */
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/* enable configuration space accesses and return data port address */
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@ -86,10 +193,8 @@ pci_cfgdisable(void)
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}
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}
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/* read configuration space register */
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int
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pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
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static int
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pcireg_cfgread(pcicfgregs *cfg, int reg, int bytes)
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{
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int data = -1;
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int port;
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@ -113,10 +218,8 @@ pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
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return (data);
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}
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/* write configuration space register */
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void
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pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
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static void
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pcireg_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
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{
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int port;
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@ -182,7 +285,7 @@ pci_cfgcheck(int maxdev)
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}
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static int
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pci_cfgopen(void)
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pcireg_cfgopen(void)
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{
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unsigned long mode1res,oldval1;
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unsigned char mode2res,oldval2;
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@ -36,8 +36,115 @@
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#include <pci/pcireg.h>
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#include <i386/isa/pcibus.h>
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#include <machine/segments.h>
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#include <machine/pc/bios.h>
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static int cfgmech;
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static int devmax;
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static int usebios;
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static int pcibios_cfgread(pcicfgregs *cfg, int reg, int bytes);
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static void pcibios_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes);
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static int pcibios_cfgopen(void);
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static int pcireg_cfgread(pcicfgregs *cfg, int reg, int bytes);
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static void pcireg_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes);
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static int pcireg_cfgopen(void);
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/* read configuration space register */
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int
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pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
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{
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return(usebios ?
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pcibios_cfgread(cfg, reg, bytes) :
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pcireg_cfgread(cfg, reg, bytes));
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}
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/* write configuration space register */
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void
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pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
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{
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return(usebios ?
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pcibios_cfgwrite(cfg, reg, data, bytes) :
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pcireg_cfgwrite(cfg, reg, data, bytes));
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}
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/* initialise access to PCI configuration space */
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static int
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pci_cfgopen(void)
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{
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if (pcibios_cfgopen() != 0) {
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usebios = 1;
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} else if (pcireg_cfgopen() != 0) {
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usebios = 0;
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} else {
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return(0);
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}
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return(1);
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}
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/* config space access using BIOS functions */
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static int
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pcibios_cfgread(pcicfgregs *cfg, int reg, int bytes)
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{
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struct bios_regs args;
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switch(bytes) {
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case 1:
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args.eax = PCIBIOS_READ_CONFIG_BYTE;
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break;
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case 2:
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args.eax = PCIBIOS_READ_CONFIG_WORD;
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break;
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case 4:
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args.eax = PCIBIOS_READ_CONFIG_DWORD;
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break;
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default:
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return(-1);
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}
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args.ebx = (cfg->bus << 8) | (cfg->slot << 3) | (cfg->func);
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args.edi = reg;
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bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
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/* check call results? */
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return(args.ecx);
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}
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static void
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pcibios_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
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{
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struct bios_regs args;
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switch(bytes) {
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case 1:
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args.eax = PCIBIOS_WRITE_CONFIG_BYTE;
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break;
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case 2:
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args.eax = PCIBIOS_WRITE_CONFIG_WORD;
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break;
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case 4:
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args.eax = PCIBIOS_WRITE_CONFIG_DWORD;
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break;
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default:
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return;
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}
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args.ebx = (cfg->bus << 8) | (cfg->slot << 3) | (cfg->func);
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args.ecx = data;
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args.edi = reg;
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bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
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}
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/* determine whether there is a PCI BIOS present */
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static int
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pcibios_cfgopen(void)
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{
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/* check for a found entrypoint */
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return(PCIbios.entry != 0);
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}
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/* configuration space access using direct register operations */
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/* enable configuration space accesses and return data port address */
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@ -86,10 +193,8 @@ pci_cfgdisable(void)
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}
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}
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/* read configuration space register */
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int
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pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
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static int
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pcireg_cfgread(pcicfgregs *cfg, int reg, int bytes)
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{
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int data = -1;
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int port;
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@ -113,10 +218,8 @@ pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
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return (data);
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}
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/* write configuration space register */
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void
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pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
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static void
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pcireg_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
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{
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int port;
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@ -182,7 +285,7 @@ pci_cfgcheck(int maxdev)
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}
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static int
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pci_cfgopen(void)
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pcireg_cfgopen(void)
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{
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unsigned long mode1res,oldval1;
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unsigned char mode2res,oldval2;
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@ -246,6 +246,14 @@
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set to 0, an interrupt will not be assigned and the
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controller will operate in polled mode only.
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set machdep.bios.pnp=disable
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Disable the use of the PnP BIOS (i386 only)
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set machdep.bios.pci=disable
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Disable the use of the PCI BIOS (i386 only)
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set net.inet.tcp.tcbhashsize=<value> TCBHASHSIZE
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Overrides the compile-time set value of TCBHASHSIZE or
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@ -1349,7 +1349,6 @@ options NATM #native ATM
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#device uart0 at isa? port 0x330 irq 5
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# The newpcm driver (use INSTEAD of snd0 and all VOXWARE drivers!).
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# Note that motherboard sound devices may require options PNPBIOS.
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#
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# Supported cards include:
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# Creative SoundBlaster ISA PnP/non-PnP
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@ -2336,7 +2335,6 @@ options NMBCLUSTERS=1024
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#options OLTR_NO_HAWKEYE_MAC
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#options OLTR_NO_TMS_MAC
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options PANIC_REBOOT_WAIT_TIME=16
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options PNPBIOS
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options PSM_DEBUG=1
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options SCSI_NCR_DEBUG
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options SCSI_NCR_MAX_SYNC=10000
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@ -193,9 +193,6 @@ OLTR_NO_BULLSEYE_MAC opt_oltr.h
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# Defaults to NDGB*16.
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NDGBPORTS opt_dgb.h
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# Temporary options for moving to pnpbios
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PNPBIOS opt_pnp.h
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# -------------------------------
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# EOF
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# -------------------------------
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@ -1349,7 +1349,6 @@ options NATM #native ATM
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#device uart0 at isa? port 0x330 irq 5
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# The newpcm driver (use INSTEAD of snd0 and all VOXWARE drivers!).
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# Note that motherboard sound devices may require options PNPBIOS.
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#
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# Supported cards include:
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# Creative SoundBlaster ISA PnP/non-PnP
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@ -2336,7 +2335,6 @@ options NMBCLUSTERS=1024
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#options OLTR_NO_HAWKEYE_MAC
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#options OLTR_NO_TMS_MAC
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options PANIC_REBOOT_WAIT_TIME=16
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options PNPBIOS
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options PSM_DEBUG=1
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options SCSI_NCR_DEBUG
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options SCSI_NCR_MAX_SYNC=10000
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@ -1349,7 +1349,6 @@ options NATM #native ATM
|
||||
#device uart0 at isa? port 0x330 irq 5
|
||||
|
||||
# The newpcm driver (use INSTEAD of snd0 and all VOXWARE drivers!).
|
||||
# Note that motherboard sound devices may require options PNPBIOS.
|
||||
#
|
||||
# Supported cards include:
|
||||
# Creative SoundBlaster ISA PnP/non-PnP
|
||||
@ -2336,7 +2335,6 @@ options NMBCLUSTERS=1024
|
||||
#options OLTR_NO_HAWKEYE_MAC
|
||||
#options OLTR_NO_TMS_MAC
|
||||
options PANIC_REBOOT_WAIT_TIME=16
|
||||
options PNPBIOS
|
||||
options PSM_DEBUG=1
|
||||
options SCSI_NCR_DEBUG
|
||||
options SCSI_NCR_MAX_SYNC=10000
|
||||
|
||||
@ -31,8 +31,6 @@
|
||||
* Code for dealing with the BIOS in x86 PC systems.
|
||||
*/
|
||||
|
||||
#include "opt_pnp.h"
|
||||
|
||||
#include "isa.h"
|
||||
|
||||
#include <sys/param.h>
|
||||
@ -79,9 +77,10 @@ bios32_init(void *junk)
|
||||
struct PnPBIOS_table *pt;
|
||||
u_int8_t ck, *cv;
|
||||
int i;
|
||||
char *p;
|
||||
|
||||
/*
|
||||
* BIOS32 Service Directory
|
||||
* BIOS32 Service Directory, PCI BIOS
|
||||
*/
|
||||
|
||||
/* look for the signature */
|
||||
@ -100,10 +99,15 @@ bios32_init(void *junk)
|
||||
printf("bios32: Entry = 0x%x (%x) Rev = %d Len = %d\n",
|
||||
sdh->entry, bios32_SDCI, sdh->revision, sdh->len);
|
||||
}
|
||||
/* See if there's a PCI BIOS entrypoint here */
|
||||
PCIbios.ident.id = 0x49435024; /* PCI systems should have this */
|
||||
if (!bios32_SDlookup(&PCIbios) && bootverbose)
|
||||
printf("pcibios: PCI BIOS entry at 0x%x\n", PCIbios.entry);
|
||||
|
||||
/* Allow user override of PCI BIOS search */
|
||||
if (((p = getenv("machdep.bios.pci")) == NULL) || strcmp(p, "disable")) {
|
||||
|
||||
/* See if there's a PCI BIOS entrypoint here */
|
||||
PCIbios.ident.id = 0x49435024; /* PCI systems should have this */
|
||||
if (!bios32_SDlookup(&PCIbios) && bootverbose)
|
||||
printf("pcibios: PCI BIOS entry at 0x%x+0x%x\n", PCIbios.base, PCIbios.entry);
|
||||
}
|
||||
} else {
|
||||
printf("bios32: Bad BIOS32 Service Directory\n");
|
||||
}
|
||||
@ -111,8 +115,11 @@ bios32_init(void *junk)
|
||||
|
||||
/*
|
||||
* PnP BIOS
|
||||
*
|
||||
* Allow user override of PnP BIOS search
|
||||
*/
|
||||
if ((sigaddr = bios_sigsearch(0, "$PnP", 4, 16, 0)) != 0) {
|
||||
if ((((p = getenv("machdep.bios.pnp")) == NULL) || strcmp(p, "disable")) &&
|
||||
((sigaddr = bios_sigsearch(0, "$PnP", 4, 16, 0)) != 0)) {
|
||||
|
||||
/* get a virtual pointer to the structure */
|
||||
pt = (struct PnPBIOS_table *)(uintptr_t)BIOS_PADDRTOVADDR(sigaddr);
|
||||
@ -166,6 +173,7 @@ bios32_SDlookup(struct bios32_SDentry *ent)
|
||||
ent->base = args.ebx;
|
||||
ent->len = args.ecx;
|
||||
ent->entry = args.edx;
|
||||
ent->ventry = BIOS_PADDRTOVADDR(ent->base + ent->entry);
|
||||
return (0); /* all OK */
|
||||
}
|
||||
return (1); /* failed */
|
||||
@ -454,8 +462,6 @@ bios16(struct bios_args *args, char *fmt, ...)
|
||||
return (i);
|
||||
}
|
||||
|
||||
#ifdef PNPBIOS /* remove conditional later */
|
||||
|
||||
/*
|
||||
* PnP BIOS interface; enumerate devices only known to the system
|
||||
* BIOS and save information about them for later use.
|
||||
@ -518,7 +524,7 @@ pnpbios_identify(driver_t *driver, device_t parent)
|
||||
/* no PnP BIOS information */
|
||||
if (pt == NULL)
|
||||
return;
|
||||
|
||||
|
||||
bzero(&args, sizeof(args));
|
||||
args.seg.code16.base = BIOS_PADDRTOVADDR(pt->pmentrybase);
|
||||
args.seg.code16.limit = 0xffff; /* XXX ? */
|
||||
@ -623,5 +629,3 @@ static driver_t pnpbios_driver = {
|
||||
static devclass_t pnpbios_devclass;
|
||||
|
||||
DRIVER_MODULE(pnpbios, isa, pnpbios_driver, pnpbios_devclass, 0, 0);
|
||||
|
||||
#endif /* PNPBIOS */
|
||||
|
||||
@ -54,6 +54,7 @@ struct bios32_SDentry
|
||||
u_int32_t base; /* base of service */
|
||||
u_int32_t len; /* service length */
|
||||
u_int32_t entry; /* entrypoint offset from base */
|
||||
vm_offset_t ventry; /* entrypoint in kernel virtual segment */
|
||||
};
|
||||
|
||||
extern int bios32_SDlookup(struct bios32_SDentry *ent);
|
||||
@ -203,6 +204,16 @@ struct bios_args {
|
||||
#define PNP_GET_BOOTFIRST "sp", 0x65
|
||||
#define PNP_SET_BOOTFIRST "sp", 0x66
|
||||
|
||||
/*
|
||||
* PCI BIOS functions
|
||||
*/
|
||||
#define PCIBIOS_READ_CONFIG_BYTE 0xb108
|
||||
#define PCIBIOS_READ_CONFIG_WORD 0xb109
|
||||
#define PCIBIOS_READ_CONFIG_DWORD 0xb10a
|
||||
#define PCIBIOS_WRITE_CONFIG_BYTE 0xb10b
|
||||
#define PCIBIOS_WRITE_CONFIG_WORD 0xb10c
|
||||
#define PCIBIOS_WRITE_CONFIG_DWORD 0xb10d
|
||||
|
||||
extern int bios16(struct bios_args *, char *, ...);
|
||||
extern int bios16_call(struct bios_regs *, char *);
|
||||
extern int bios32(struct bios_regs *, u_int, u_short);
|
||||
|
||||
@ -36,8 +36,115 @@
|
||||
#include <pci/pcireg.h>
|
||||
#include <i386/isa/pcibus.h>
|
||||
|
||||
#include <machine/segments.h>
|
||||
#include <machine/pc/bios.h>
|
||||
|
||||
static int cfgmech;
|
||||
static int devmax;
|
||||
static int usebios;
|
||||
|
||||
static int pcibios_cfgread(pcicfgregs *cfg, int reg, int bytes);
|
||||
static void pcibios_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes);
|
||||
static int pcibios_cfgopen(void);
|
||||
static int pcireg_cfgread(pcicfgregs *cfg, int reg, int bytes);
|
||||
static void pcireg_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes);
|
||||
static int pcireg_cfgopen(void);
|
||||
|
||||
/* read configuration space register */
|
||||
|
||||
int
|
||||
pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
{
|
||||
return(usebios ?
|
||||
pcibios_cfgread(cfg, reg, bytes) :
|
||||
pcireg_cfgread(cfg, reg, bytes));
|
||||
}
|
||||
|
||||
/* write configuration space register */
|
||||
|
||||
void
|
||||
pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
{
|
||||
return(usebios ?
|
||||
pcibios_cfgwrite(cfg, reg, data, bytes) :
|
||||
pcireg_cfgwrite(cfg, reg, data, bytes));
|
||||
}
|
||||
|
||||
/* initialise access to PCI configuration space */
|
||||
static int
|
||||
pci_cfgopen(void)
|
||||
{
|
||||
if (pcibios_cfgopen() != 0) {
|
||||
usebios = 1;
|
||||
} else if (pcireg_cfgopen() != 0) {
|
||||
usebios = 0;
|
||||
} else {
|
||||
return(0);
|
||||
}
|
||||
return(1);
|
||||
}
|
||||
|
||||
/* config space access using BIOS functions */
|
||||
|
||||
static int
|
||||
pcibios_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
{
|
||||
struct bios_regs args;
|
||||
|
||||
switch(bytes) {
|
||||
case 1:
|
||||
args.eax = PCIBIOS_READ_CONFIG_BYTE;
|
||||
break;
|
||||
case 2:
|
||||
args.eax = PCIBIOS_READ_CONFIG_WORD;
|
||||
break;
|
||||
case 4:
|
||||
args.eax = PCIBIOS_READ_CONFIG_DWORD;
|
||||
break;
|
||||
default:
|
||||
return(-1);
|
||||
}
|
||||
args.ebx = (cfg->bus << 8) | (cfg->slot << 3) | (cfg->func);
|
||||
args.edi = reg;
|
||||
bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
|
||||
/* check call results? */
|
||||
return(args.ecx);
|
||||
}
|
||||
|
||||
static void
|
||||
pcibios_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
{
|
||||
struct bios_regs args;
|
||||
|
||||
switch(bytes) {
|
||||
case 1:
|
||||
args.eax = PCIBIOS_WRITE_CONFIG_BYTE;
|
||||
break;
|
||||
case 2:
|
||||
args.eax = PCIBIOS_WRITE_CONFIG_WORD;
|
||||
break;
|
||||
case 4:
|
||||
args.eax = PCIBIOS_WRITE_CONFIG_DWORD;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
args.ebx = (cfg->bus << 8) | (cfg->slot << 3) | (cfg->func);
|
||||
args.ecx = data;
|
||||
args.edi = reg;
|
||||
bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
|
||||
}
|
||||
|
||||
/* determine whether there is a PCI BIOS present */
|
||||
|
||||
static int
|
||||
pcibios_cfgopen(void)
|
||||
{
|
||||
/* check for a found entrypoint */
|
||||
return(PCIbios.entry != 0);
|
||||
}
|
||||
|
||||
/* configuration space access using direct register operations */
|
||||
|
||||
/* enable configuration space accesses and return data port address */
|
||||
|
||||
@ -86,10 +193,8 @@ pci_cfgdisable(void)
|
||||
}
|
||||
}
|
||||
|
||||
/* read configuration space register */
|
||||
|
||||
int
|
||||
pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
static int
|
||||
pcireg_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
{
|
||||
int data = -1;
|
||||
int port;
|
||||
@ -113,10 +218,8 @@ pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
return (data);
|
||||
}
|
||||
|
||||
/* write configuration space register */
|
||||
|
||||
void
|
||||
pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
static void
|
||||
pcireg_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
{
|
||||
int port;
|
||||
|
||||
@ -182,7 +285,7 @@ pci_cfgcheck(int maxdev)
|
||||
}
|
||||
|
||||
static int
|
||||
pci_cfgopen(void)
|
||||
pcireg_cfgopen(void)
|
||||
{
|
||||
unsigned long mode1res,oldval1;
|
||||
unsigned char mode2res,oldval2;
|
||||
|
||||
@ -36,8 +36,115 @@
|
||||
#include <pci/pcireg.h>
|
||||
#include <i386/isa/pcibus.h>
|
||||
|
||||
#include <machine/segments.h>
|
||||
#include <machine/pc/bios.h>
|
||||
|
||||
static int cfgmech;
|
||||
static int devmax;
|
||||
static int usebios;
|
||||
|
||||
static int pcibios_cfgread(pcicfgregs *cfg, int reg, int bytes);
|
||||
static void pcibios_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes);
|
||||
static int pcibios_cfgopen(void);
|
||||
static int pcireg_cfgread(pcicfgregs *cfg, int reg, int bytes);
|
||||
static void pcireg_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes);
|
||||
static int pcireg_cfgopen(void);
|
||||
|
||||
/* read configuration space register */
|
||||
|
||||
int
|
||||
pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
{
|
||||
return(usebios ?
|
||||
pcibios_cfgread(cfg, reg, bytes) :
|
||||
pcireg_cfgread(cfg, reg, bytes));
|
||||
}
|
||||
|
||||
/* write configuration space register */
|
||||
|
||||
void
|
||||
pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
{
|
||||
return(usebios ?
|
||||
pcibios_cfgwrite(cfg, reg, data, bytes) :
|
||||
pcireg_cfgwrite(cfg, reg, data, bytes));
|
||||
}
|
||||
|
||||
/* initialise access to PCI configuration space */
|
||||
static int
|
||||
pci_cfgopen(void)
|
||||
{
|
||||
if (pcibios_cfgopen() != 0) {
|
||||
usebios = 1;
|
||||
} else if (pcireg_cfgopen() != 0) {
|
||||
usebios = 0;
|
||||
} else {
|
||||
return(0);
|
||||
}
|
||||
return(1);
|
||||
}
|
||||
|
||||
/* config space access using BIOS functions */
|
||||
|
||||
static int
|
||||
pcibios_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
{
|
||||
struct bios_regs args;
|
||||
|
||||
switch(bytes) {
|
||||
case 1:
|
||||
args.eax = PCIBIOS_READ_CONFIG_BYTE;
|
||||
break;
|
||||
case 2:
|
||||
args.eax = PCIBIOS_READ_CONFIG_WORD;
|
||||
break;
|
||||
case 4:
|
||||
args.eax = PCIBIOS_READ_CONFIG_DWORD;
|
||||
break;
|
||||
default:
|
||||
return(-1);
|
||||
}
|
||||
args.ebx = (cfg->bus << 8) | (cfg->slot << 3) | (cfg->func);
|
||||
args.edi = reg;
|
||||
bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
|
||||
/* check call results? */
|
||||
return(args.ecx);
|
||||
}
|
||||
|
||||
static void
|
||||
pcibios_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
{
|
||||
struct bios_regs args;
|
||||
|
||||
switch(bytes) {
|
||||
case 1:
|
||||
args.eax = PCIBIOS_WRITE_CONFIG_BYTE;
|
||||
break;
|
||||
case 2:
|
||||
args.eax = PCIBIOS_WRITE_CONFIG_WORD;
|
||||
break;
|
||||
case 4:
|
||||
args.eax = PCIBIOS_WRITE_CONFIG_DWORD;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
args.ebx = (cfg->bus << 8) | (cfg->slot << 3) | (cfg->func);
|
||||
args.ecx = data;
|
||||
args.edi = reg;
|
||||
bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
|
||||
}
|
||||
|
||||
/* determine whether there is a PCI BIOS present */
|
||||
|
||||
static int
|
||||
pcibios_cfgopen(void)
|
||||
{
|
||||
/* check for a found entrypoint */
|
||||
return(PCIbios.entry != 0);
|
||||
}
|
||||
|
||||
/* configuration space access using direct register operations */
|
||||
|
||||
/* enable configuration space accesses and return data port address */
|
||||
|
||||
@ -86,10 +193,8 @@ pci_cfgdisable(void)
|
||||
}
|
||||
}
|
||||
|
||||
/* read configuration space register */
|
||||
|
||||
int
|
||||
pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
static int
|
||||
pcireg_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
{
|
||||
int data = -1;
|
||||
int port;
|
||||
@ -113,10 +218,8 @@ pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
return (data);
|
||||
}
|
||||
|
||||
/* write configuration space register */
|
||||
|
||||
void
|
||||
pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
static void
|
||||
pcireg_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
{
|
||||
int port;
|
||||
|
||||
@ -182,7 +285,7 @@ pci_cfgcheck(int maxdev)
|
||||
}
|
||||
|
||||
static int
|
||||
pci_cfgopen(void)
|
||||
pcireg_cfgopen(void)
|
||||
{
|
||||
unsigned long mode1res,oldval1;
|
||||
unsigned char mode2res,oldval2;
|
||||
|
||||
@ -36,8 +36,115 @@
|
||||
#include <pci/pcireg.h>
|
||||
#include <i386/isa/pcibus.h>
|
||||
|
||||
#include <machine/segments.h>
|
||||
#include <machine/pc/bios.h>
|
||||
|
||||
static int cfgmech;
|
||||
static int devmax;
|
||||
static int usebios;
|
||||
|
||||
static int pcibios_cfgread(pcicfgregs *cfg, int reg, int bytes);
|
||||
static void pcibios_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes);
|
||||
static int pcibios_cfgopen(void);
|
||||
static int pcireg_cfgread(pcicfgregs *cfg, int reg, int bytes);
|
||||
static void pcireg_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes);
|
||||
static int pcireg_cfgopen(void);
|
||||
|
||||
/* read configuration space register */
|
||||
|
||||
int
|
||||
pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
{
|
||||
return(usebios ?
|
||||
pcibios_cfgread(cfg, reg, bytes) :
|
||||
pcireg_cfgread(cfg, reg, bytes));
|
||||
}
|
||||
|
||||
/* write configuration space register */
|
||||
|
||||
void
|
||||
pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
{
|
||||
return(usebios ?
|
||||
pcibios_cfgwrite(cfg, reg, data, bytes) :
|
||||
pcireg_cfgwrite(cfg, reg, data, bytes));
|
||||
}
|
||||
|
||||
/* initialise access to PCI configuration space */
|
||||
static int
|
||||
pci_cfgopen(void)
|
||||
{
|
||||
if (pcibios_cfgopen() != 0) {
|
||||
usebios = 1;
|
||||
} else if (pcireg_cfgopen() != 0) {
|
||||
usebios = 0;
|
||||
} else {
|
||||
return(0);
|
||||
}
|
||||
return(1);
|
||||
}
|
||||
|
||||
/* config space access using BIOS functions */
|
||||
|
||||
static int
|
||||
pcibios_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
{
|
||||
struct bios_regs args;
|
||||
|
||||
switch(bytes) {
|
||||
case 1:
|
||||
args.eax = PCIBIOS_READ_CONFIG_BYTE;
|
||||
break;
|
||||
case 2:
|
||||
args.eax = PCIBIOS_READ_CONFIG_WORD;
|
||||
break;
|
||||
case 4:
|
||||
args.eax = PCIBIOS_READ_CONFIG_DWORD;
|
||||
break;
|
||||
default:
|
||||
return(-1);
|
||||
}
|
||||
args.ebx = (cfg->bus << 8) | (cfg->slot << 3) | (cfg->func);
|
||||
args.edi = reg;
|
||||
bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
|
||||
/* check call results? */
|
||||
return(args.ecx);
|
||||
}
|
||||
|
||||
static void
|
||||
pcibios_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
{
|
||||
struct bios_regs args;
|
||||
|
||||
switch(bytes) {
|
||||
case 1:
|
||||
args.eax = PCIBIOS_WRITE_CONFIG_BYTE;
|
||||
break;
|
||||
case 2:
|
||||
args.eax = PCIBIOS_WRITE_CONFIG_WORD;
|
||||
break;
|
||||
case 4:
|
||||
args.eax = PCIBIOS_WRITE_CONFIG_DWORD;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
args.ebx = (cfg->bus << 8) | (cfg->slot << 3) | (cfg->func);
|
||||
args.ecx = data;
|
||||
args.edi = reg;
|
||||
bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
|
||||
}
|
||||
|
||||
/* determine whether there is a PCI BIOS present */
|
||||
|
||||
static int
|
||||
pcibios_cfgopen(void)
|
||||
{
|
||||
/* check for a found entrypoint */
|
||||
return(PCIbios.entry != 0);
|
||||
}
|
||||
|
||||
/* configuration space access using direct register operations */
|
||||
|
||||
/* enable configuration space accesses and return data port address */
|
||||
|
||||
@ -86,10 +193,8 @@ pci_cfgdisable(void)
|
||||
}
|
||||
}
|
||||
|
||||
/* read configuration space register */
|
||||
|
||||
int
|
||||
pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
static int
|
||||
pcireg_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
{
|
||||
int data = -1;
|
||||
int port;
|
||||
@ -113,10 +218,8 @@ pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
return (data);
|
||||
}
|
||||
|
||||
/* write configuration space register */
|
||||
|
||||
void
|
||||
pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
static void
|
||||
pcireg_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
{
|
||||
int port;
|
||||
|
||||
@ -182,7 +285,7 @@ pci_cfgcheck(int maxdev)
|
||||
}
|
||||
|
||||
static int
|
||||
pci_cfgopen(void)
|
||||
pcireg_cfgopen(void)
|
||||
{
|
||||
unsigned long mode1res,oldval1;
|
||||
unsigned char mode2res,oldval2;
|
||||
|
||||
@ -36,8 +36,115 @@
|
||||
#include <pci/pcireg.h>
|
||||
#include <i386/isa/pcibus.h>
|
||||
|
||||
#include <machine/segments.h>
|
||||
#include <machine/pc/bios.h>
|
||||
|
||||
static int cfgmech;
|
||||
static int devmax;
|
||||
static int usebios;
|
||||
|
||||
static int pcibios_cfgread(pcicfgregs *cfg, int reg, int bytes);
|
||||
static void pcibios_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes);
|
||||
static int pcibios_cfgopen(void);
|
||||
static int pcireg_cfgread(pcicfgregs *cfg, int reg, int bytes);
|
||||
static void pcireg_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes);
|
||||
static int pcireg_cfgopen(void);
|
||||
|
||||
/* read configuration space register */
|
||||
|
||||
int
|
||||
pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
{
|
||||
return(usebios ?
|
||||
pcibios_cfgread(cfg, reg, bytes) :
|
||||
pcireg_cfgread(cfg, reg, bytes));
|
||||
}
|
||||
|
||||
/* write configuration space register */
|
||||
|
||||
void
|
||||
pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
{
|
||||
return(usebios ?
|
||||
pcibios_cfgwrite(cfg, reg, data, bytes) :
|
||||
pcireg_cfgwrite(cfg, reg, data, bytes));
|
||||
}
|
||||
|
||||
/* initialise access to PCI configuration space */
|
||||
static int
|
||||
pci_cfgopen(void)
|
||||
{
|
||||
if (pcibios_cfgopen() != 0) {
|
||||
usebios = 1;
|
||||
} else if (pcireg_cfgopen() != 0) {
|
||||
usebios = 0;
|
||||
} else {
|
||||
return(0);
|
||||
}
|
||||
return(1);
|
||||
}
|
||||
|
||||
/* config space access using BIOS functions */
|
||||
|
||||
static int
|
||||
pcibios_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
{
|
||||
struct bios_regs args;
|
||||
|
||||
switch(bytes) {
|
||||
case 1:
|
||||
args.eax = PCIBIOS_READ_CONFIG_BYTE;
|
||||
break;
|
||||
case 2:
|
||||
args.eax = PCIBIOS_READ_CONFIG_WORD;
|
||||
break;
|
||||
case 4:
|
||||
args.eax = PCIBIOS_READ_CONFIG_DWORD;
|
||||
break;
|
||||
default:
|
||||
return(-1);
|
||||
}
|
||||
args.ebx = (cfg->bus << 8) | (cfg->slot << 3) | (cfg->func);
|
||||
args.edi = reg;
|
||||
bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
|
||||
/* check call results? */
|
||||
return(args.ecx);
|
||||
}
|
||||
|
||||
static void
|
||||
pcibios_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
{
|
||||
struct bios_regs args;
|
||||
|
||||
switch(bytes) {
|
||||
case 1:
|
||||
args.eax = PCIBIOS_WRITE_CONFIG_BYTE;
|
||||
break;
|
||||
case 2:
|
||||
args.eax = PCIBIOS_WRITE_CONFIG_WORD;
|
||||
break;
|
||||
case 4:
|
||||
args.eax = PCIBIOS_WRITE_CONFIG_DWORD;
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
args.ebx = (cfg->bus << 8) | (cfg->slot << 3) | (cfg->func);
|
||||
args.ecx = data;
|
||||
args.edi = reg;
|
||||
bios32(&args, PCIbios.ventry, GSEL(GCODE_SEL, SEL_KPL));
|
||||
}
|
||||
|
||||
/* determine whether there is a PCI BIOS present */
|
||||
|
||||
static int
|
||||
pcibios_cfgopen(void)
|
||||
{
|
||||
/* check for a found entrypoint */
|
||||
return(PCIbios.entry != 0);
|
||||
}
|
||||
|
||||
/* configuration space access using direct register operations */
|
||||
|
||||
/* enable configuration space accesses and return data port address */
|
||||
|
||||
@ -86,10 +193,8 @@ pci_cfgdisable(void)
|
||||
}
|
||||
}
|
||||
|
||||
/* read configuration space register */
|
||||
|
||||
int
|
||||
pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
static int
|
||||
pcireg_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
{
|
||||
int data = -1;
|
||||
int port;
|
||||
@ -113,10 +218,8 @@ pci_cfgread(pcicfgregs *cfg, int reg, int bytes)
|
||||
return (data);
|
||||
}
|
||||
|
||||
/* write configuration space register */
|
||||
|
||||
void
|
||||
pci_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
static void
|
||||
pcireg_cfgwrite(pcicfgregs *cfg, int reg, int data, int bytes)
|
||||
{
|
||||
int port;
|
||||
|
||||
@ -182,7 +285,7 @@ pci_cfgcheck(int maxdev)
|
||||
}
|
||||
|
||||
static int
|
||||
pci_cfgopen(void)
|
||||
pcireg_cfgopen(void)
|
||||
{
|
||||
unsigned long mode1res,oldval1;
|
||||
unsigned char mode2res,oldval2;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user