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Remove EOL whitespace.
This commit is contained in:
Joel Dahl
parent
5127efa399
commit
4a121e0748
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=248871
@ -201,60 +201,60 @@ Haswell programmable PMCs support the following events:
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.Bl -tag -width indent
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.It Li LD_BLOCKS.STORE_FORWARD
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.Pq Event 03H , Umask 02H
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Loads blocked by overlapping with store buffer that
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cannot be forwarded.
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Loads blocked by overlapping with store buffer that
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cannot be forwarded.
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.It Li MISALIGN_MEM_REF.LOADS
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.Pq Event 05H , Umask 01H
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Speculative cache-line split load uops dispatched to
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L1D.
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Speculative cache-line split load uops dispatched to
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L1D.
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.It Li MISALIGN_MEM_REF.STORES
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.Pq Event 05H , Umask 02H
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Speculative cache-line split Store-address uops
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dispatched to L1D.
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Speculative cache-line split Store-address uops
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dispatched to L1D.
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.It Li LD_BLOCKS_PARTIAL.ADDRESS_ALIAS
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.Pq Event 07H , Umask 01H
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False dependencies in MOB due to partial compare
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on address.
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False dependencies in MOB due to partial compare
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on address.
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.It Li DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK
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.Pq Event 08H , Umask 01H
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Misses in all TLB levels that cause a page walk of any
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page size.
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Misses in all TLB levels that cause a page walk of any
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page size.
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.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_4K
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.Pq Event 08H , Umask 02H
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Completed page walks due to demand load misses
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that caused 4K page walks in any TLB levels.
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Completed page walks due to demand load misses
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that caused 4K page walks in any TLB levels.
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.It Li DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4K
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.Pq Event 08H , Umask 02H
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Completed page walks due to demand load misses
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that caused 2M/4M page walks in any TLB levels.
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Completed page walks due to demand load misses
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that caused 2M/4M page walks in any TLB levels.
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.It Li DTLB_LOAD_MISSES.WALK_COMPLETED
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.Pq Event 08H , Umask 0EH
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Completed page walks in any TLB of any page size
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due to demand load misses
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Completed page walks in any TLB of any page size
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due to demand load misses
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.It Li DTLB_LOAD_MISSES.WALK_DURATION
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.Pq Event 08H , Umask 10H
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Cycle PMH is busy with a walk.
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Cycle PMH is busy with a walk.
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.It Li DTLB_LOAD_MISSES.STLB_HIT_4K
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.Pq Event 08H , Umask 20H
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Load misses that missed DTLB but hit STLB (4K).
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Load misses that missed DTLB but hit STLB (4K).
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.It Li DTLB_LOAD_MISSES.STLB_HIT_2M
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.Pq Event 08H , Umask 40H
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Load misses that missed DTLB but hit STLB (2M).
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Load misses that missed DTLB but hit STLB (2M).
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.It Li DTLB_LOAD_MISSES.STLB_HIT
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.Pq Event 08H , Umask 60H
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Number of cache load STLB hits. No page walk.
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.It Li DTLB_LOAD_MISSES.PDE_CACHE_MISS
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.Pq Event 08H , Umask 80H
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DTLB demand load misses with low part of linear-to-
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physical address translation missed
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DTLB demand load misses with low part of linear-to-
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physical address translation missed
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.It Li INT_MISC.RECOVERY_CYCLES
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.Pq Event 0DH , Umask 03H
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Cycles waiting to recover after Machine Clears
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except JEClear. Set Cmask= 1.
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Cycles waiting to recover after Machine Clears
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except JEClear. Set Cmask= 1.
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.It Li UOPS_ISSUED.ANY
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.Pq Event 0EH , Umask 01H
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ncrements each cycle the # of Uops issued by the
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RAT to RS.
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ncrements each cycle the # of Uops issued by the
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RAT to RS.
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Set Cmask = 1, Inv = 1, Any= 1to count stalled cycles
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of this core.
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.It Li UOPS_ISSUED.FLAGS_MERGE
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@ -278,7 +278,7 @@ rejects.
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.Pq Event 24H , Umask 41H
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Demand Data Read requests that hit L2 cache.
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.It Li L2_RQSTS.ALL_DEMAND_DATA_RD
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.Pq Event 24H , Umask E1H
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.Pq Event 24H , Umask E1H
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Counts any demand and L1 HW prefetch data load
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requests to L2.
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.It Li L2_RQSTS.RFO_HIT
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@ -348,9 +348,9 @@ Increments at the frequency of XCLK (100 MHz)
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when not halted.
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.It Li L1D_PEND_MISS.PENDING
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.Pq Event 48H , Umask 01H
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Increments the number of outstanding L1D misses
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every cycle. Set Cmaks = 1 and Edge =1 to count
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occurrences.
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Increments the number of outstanding L1D misses
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every cycle. Set Cmaks = 1 and Edge =1 to count
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occurrences.
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.It Li DTLB_STORE_MISSES.MISS_CAUSES_A_WALK
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.Pq Event 49H , Umask 01H
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Miss in all TLB levels causes an page walk of any
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@ -422,15 +422,15 @@ Unhalted core cycles when the thread is not in ring 0.
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Cycles the RS is empty for the thread.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD
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.Pq Event 60H , Umask 01H
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Offcore outstanding Demand Data Read transactions
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Offcore outstanding Demand Data Read transactions
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in SQ to uncore. Set Cmask=1 to count cycles.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CORE_RD
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.Pq Event 60H , Umask 02H
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Offcore outstanding Demand code Read transactions
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Offcore outstanding Demand code Read transactions
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in SQ to uncore. Set Cmask=1 to count cycles.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO
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.Pq Event 60H , Umask 04H
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Offcore outstanding RFO store transactions in SQ to
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Offcore outstanding RFO store transactions in SQ to
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uncore. Set Cmask=1 to count cycles.
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.It Li OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD
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.Pq Event 60H , Umask 08H
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@ -449,7 +449,7 @@ Cycles in which the L1D is locked.
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Counts cycles the IDQ is empty.
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.It Li IDQ.MITE_UOPS
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.Pq Event 79H , Umask 04H
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Increment each cycle # of uops delivered to IDQ from
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Increment each cycle # of uops delivered to IDQ from
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MITE path.
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Set Cmask = 1 to count cycles.
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.It Li IDQ.DSB_UOPS
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@ -459,14 +459,14 @@ from DSB path.
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Set Cmask = 1 to count cycles.
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.It Li IDQ.MS_DSB_UOPS
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.Pq Event 79H , Umask 10H
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Increment each cycle # of uops delivered to IDQ
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when MS_busy by DSB. Set Cmask = 1 to count
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cycles. Add Edge=1 to count # of delivery.
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Increment each cycle # of uops delivered to IDQ
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when MS_busy by DSB. Set Cmask = 1 to count
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cycles. Add Edge=1 to count # of delivery.
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.It Li IDQ.MS_MITE_UOPS
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.Pq Event 79H , Umask 20H
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ncrement each cycle # of uops delivered to IDQ
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when MS_busy by MITE. Set Cmask = 1 to count
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cycles.
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ncrement each cycle # of uops delivered to IDQ
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when MS_busy by MITE. Set Cmask = 1 to count
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cycles.
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.It Li IDQ.MS_UOPS
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.Pq Event 79H , Umask 30H
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Increment each cycle # of uops delivered to IDQ from
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@ -474,163 +474,163 @@ MS by either DSB or MITE. Set Cmask = 1 to count
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cycles.
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.It Li IDQ.ALL_DSB_CYCLES_ANY_UOPS
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.Pq Event 79H , Umask 18H
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Counts cycles DSB is delivered at least one uops. Set
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Cmask = 1.
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Counts cycles DSB is delivered at least one uops. Set
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Cmask = 1.
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.It Li IDQ.ALL_DSB_CYCLES_4_UOPS
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.Pq Event 79H , Umask 18H
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Counts cycles DSB is delivered four uops. Set Cmask
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Counts cycles DSB is delivered four uops. Set Cmask
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=4.
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.It Li IDQ.ALL_MITE_CYCLES_ANY_UOPS
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.Pq Event 79H , Umask 24H
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Counts cycles MITE is delivered at least one uops. Set
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Cmask = 1.
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Counts cycles MITE is delivered at least one uops. Set
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Cmask = 1.
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.It Li IDQ.ALL_MITE_CYCLES_4_UOPS
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.Pq Event 79H , Umask 24H
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Counts cycles MITE is delivered four uops. Set Cmask
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Counts cycles MITE is delivered four uops. Set Cmask
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=4.
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.It Li IDQ.MITE_ALL_UOPS
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.Pq Event 79H , Umask 3CH
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# of uops delivered to IDQ from any path.
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# of uops delivered to IDQ from any path.
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.It Li ICACHE.MISSES
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.Pq Event 80H , Umask 02H
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Number of Instruction Cache, Streaming Buffer and
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Victim Cache Misses. Includes UC accesses.
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Number of Instruction Cache, Streaming Buffer and
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Victim Cache Misses. Includes UC accesses.
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.It Li ITLB_MISSES.MISS_CAUSES_A_WALK
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.Pq Event 85H , Umask 01H
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Misses in ITLB that causes a page walk of any page
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size.
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Misses in ITLB that causes a page walk of any page
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size.
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.It Li ITLB_MISSES.WALK_COMPLETED_4K
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.Pq Event 85H , Umask 02H
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Completed page walks due to misses in ITLB 4K page
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entries.
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Completed page walks due to misses in ITLB 4K page
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entries.
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.It Li TLB_MISSES.WALK_COMPLETED_2M_4M
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.Pq Event 85H , Umask 04H
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Completed page walks due to misses in ITLB 2M/4M
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Completed page walks due to misses in ITLB 2M/4M
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page entries.
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.It Li ITLB_MISSES.WALK_COMPLETED
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.Pq Event 85H , Umask 0EH
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Completed page walks in ITLB of any page size.
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Completed page walks in ITLB of any page size.
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.It Li ITLB_MISSES.WALK_DURATION
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.Pq Event 85H , Umask 10H
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Cycle PMH is busy with a walk.
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Cycle PMH is busy with a walk.
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.It Li ITLB_MISSES.STLB_HIT_4K
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.Pq Event 85H , Umask 20H
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ITLB misses that hit STLB (4K).
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ITLB misses that hit STLB (4K).
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.It Li ITLB_MISSES.STLB_HIT_2M
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.Pq Event 85H , Umask 40H
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ITLB misses that hit STLB (2K).
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ITLB misses that hit STLB (2K).
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.It Li ITLB_MISSES.STLB_HIT
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.Pq Event 85H , Umask 60H
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TLB misses that hit STLB. No page walk.
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TLB misses that hit STLB. No page walk.
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.It Li ILD_STALL.LCP
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.Pq Event 87H , Umask 01H
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Stalls caused by changing prefix length of the
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Stalls caused by changing prefix length of the
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instruction.
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.It Li ILD_STALL.IQ_FULL
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.Pq Event 87H , Umask 04H
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Stall cycles due to IQ is full.
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Stall cycles due to IQ is full.
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.It Li BR_INST_EXEC.COND
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.Pq Event 88H , Umask 01H
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Qualify conditional near branch instructions
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executed, but not necessarily retired.
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Qualify conditional near branch instructions
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executed, but not necessarily retired.
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.It Li BR_INST_EXEC.DIRECT_JMP
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.Pq Event 88H , Umask 02H
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Qualify all unconditional near branch instructions
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excluding calls and indirect branches.
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Qualify all unconditional near branch instructions
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excluding calls and indirect branches.
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.It Li BR_INST_EXEC.INDIRECT_JMP_NON_CALL_RET
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.Pq Event 88H , Umask 04H
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Qualify executed indirect near branch instructions
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that are not calls nor returns.
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Qualify executed indirect near branch instructions
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that are not calls nor returns.
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.It Li BR_INST_EXEC.RETURN_NEAR
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.Pq Event 88H , Umask 08H
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Qualify indirect near branches that have a return
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mnemonic.
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Qualify indirect near branches that have a return
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mnemonic.
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.It Li BR_INST_EXEC.DIRECT_NEAR_CALL
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.Pq Event 88H , Umask 10H
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Qualify unconditional near call branch instructions,
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excluding non call branch, executed.
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Qualify unconditional near call branch instructions,
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excluding non call branch, executed.
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.It Li BR_INST_EXEC.INDIRECT_NEAR_CALL
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.Pq Event 88H , Umask 20H
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Qualify indirect near calls, including both register and
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memory indirect, executed.
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.It Li BR_INST_EXEC.NONTAKEN
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.Pq Event 88H , Umask 40H
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Qualify non-taken near branches executed.
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Qualify non-taken near branches executed.
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.It Li BR_INST_EXEC.TAKEN
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.Pq Event 88H , Umask 80H
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Qualify taken near branches executed. Must combine
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with 01H,02H, 04H, 08H, 10H, 20H.
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Qualify taken near branches executed. Must combine
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with 01H,02H, 04H, 08H, 10H, 20H.
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.It Li BR_INST_EXEC.ALL_BRANCHES
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.Pq Event 88H , Umask FFH
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Counts all near executed branches (not necessarily
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retired).
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Counts all near executed branches (not necessarily
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retired).
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.It Li BR_MISP_EXEC.COND
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.Pq Event 89H , Umask 01H
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Qualify conditional near branch instructions
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mispredicted.
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Qualify conditional near branch instructions
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mispredicted.
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.It Li BR_MISP_EXEC.INDIRECT_JMP_NON_CALL_RET
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.Pq Event 89H , Umask 04H
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Qualify mispredicted indirect near branch
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instructions that are not calls nor returns.
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Qualify mispredicted indirect near branch
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instructions that are not calls nor returns.
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.It Li BR_MISP_EXEC.RETURN_NEAR
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.Pq Event 89H , Umask 08H
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Qualify mispredicted indirect near branches that
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have a return mnemonic.
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Qualify mispredicted indirect near branches that
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have a return mnemonic.
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.It Li BR_MISP_EXEC.DIRECT_NEAR_CALL
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.Pq Event 89H , Umask 10H
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Qualify mispredicted unconditional near call branch
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instructions, excluding non call branch, executed.
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Qualify mispredicted unconditional near call branch
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instructions, excluding non call branch, executed.
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.It Li BR_MISP_EXEC.INDIRECT_NEAR_CALL
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.Pq Event 89H , Umask 20H
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Qualify mispredicted indirect near calls, including
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both register and memory indirect, executed.
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Qualify mispredicted indirect near calls, including
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both register and memory indirect, executed.
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.It Li BR_MISP_EXEC.NONTAKEN
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.Pq Event 89H , Umask 40H
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Qualify mispredicted non-taken near branches
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Qualify mispredicted non-taken near branches
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executed.
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.It Li BR_MISP_EXEC.TAKEN
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.Pq Event 89H , Umask 80H
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Qualify mispredicted taken near branches executed.
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Must combine with 01H,02H, 04H, 08H, 10H, 20H.
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Qualify mispredicted taken near branches executed.
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Must combine with 01H,02H, 04H, 08H, 10H, 20H.
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.It Li BR_MISP_EXEC.ALL_BRANCHES
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.Pq Event 89H , Umask FFH
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Counts all near executed branches (not necessarily
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retired).
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Counts all near executed branches (not necessarily
|
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retired).
|
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.It Li IDQ_UOPS_NOT_DELIVERED.CORE
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.Pq Event 9CH , Umask 01H
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Count number of non-delivered uops to RAT per
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thread.
|
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Count number of non-delivered uops to RAT per
|
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thread.
|
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.It Li UOPS_EXECUTED_PORT.PORT_0
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.Pq Event A1H , Umask 01H
|
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Cycles which a Uop is dispatched on port 0 in this
|
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thread.
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Cycles which a Uop is dispatched on port 0 in this
|
||||
thread.
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.It Li UOPS_EXECUTED_PORT.PORT_1
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.Pq Event A1H , Umask 02H
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Cycles which a Uop is dispatched on port 1 in this
|
||||
Cycles which a Uop is dispatched on port 1 in this
|
||||
thread.
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||||
.It Li UOPS_EXECUTED_PORT.PORT_2
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.Pq Event A1H , Umask 04H
|
||||
Cycles which a Uop is dispatched on port 2 in this
|
||||
Cycles which a Uop is dispatched on port 2 in this
|
||||
thread.
|
||||
.It Li UOPS_EXECUTED_PORT.PORT_3
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.Pq Event A1H , Umask 08H
|
||||
Cycles which a Uop is dispatched on port 3 in this
|
||||
Cycles which a Uop is dispatched on port 3 in this
|
||||
thread.
|
||||
.It Li UOPS_EXECUTED_PORT.PORT_4
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.Pq Event A1H , Umask 10H
|
||||
Cycles which a Uop is dispatched on port 4 in this
|
||||
Cycles which a Uop is dispatched on port 4 in this
|
||||
thread.
|
||||
.It Li UOPS_EXECUTED_PORT.PORT_5
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.Pq Event A1H , Umask 20H
|
||||
Cycles which a Uop is dispatched on port 5 in this
|
||||
Cycles which a Uop is dispatched on port 5 in this
|
||||
thread.
|
||||
.It Li UOPS_EXECUTED_PORT.PORT_6
|
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.Pq Event A1H , Umask 40H
|
||||
Cycles which a Uop is dispatched on port 6 in this
|
||||
Cycles which a Uop is dispatched on port 6 in this
|
||||
thread.
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.It Li UOPS_EXECUTED_PORT.PORT_7
|
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.Pq Event A1H , Umask 80H
|
||||
Cycles which a Uop is dispatched on port 7 in this
|
||||
Cycles which a Uop is dispatched on port 7 in this
|
||||
thread.
|
||||
.It Li RESOURCE_STALLS.ANY
|
||||
.Pq Event A2H , Umask 01H
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||||
@ -673,7 +673,7 @@ Demand data read requests sent to uncore.
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Demand code read requests sent to uncore.
|
||||
.It Li OFFCORE_REQUESTS.DEMAND_RFO
|
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.Pq Event B0H , Umask 04H
|
||||
Demand RFO read requests sent to uncore, including
|
||||
Demand RFO read requests sent to uncore, including
|
||||
regular RFOs, locks, ItoM.
|
||||
.It Li OFFCORE_REQUESTS.ALL_DATA_RD
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.Pq Event B0H , Umask 08H
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||||
@ -723,66 +723,66 @@ DTLB flush attempts of the thread-specific entries.
|
||||
Count number of STLB flush attempts.
|
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.It Li INST_RETIRED.ANY_P
|
||||
.Pq Event C0H , Umask 00H
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||||
Number of instructions at retirement.
|
||||
Number of instructions at retirement.
|
||||
.It Li INST_RETIRED.ALL
|
||||
.Pq Event C0H , Umask 01H
|
||||
Precise instruction retired event with HW to reduce
|
||||
effect of PEBS shadow in IP distribution.
|
||||
Precise instruction retired event with HW to reduce
|
||||
effect of PEBS shadow in IP distribution.
|
||||
.It Li OTHER_ASSISTS.AVX_TO_SSE
|
||||
.Pq Event C1H , Umask 08H
|
||||
Number of transitions from AVX-256 to legacy SSE
|
||||
when penalty applicable.
|
||||
Number of transitions from AVX-256 to legacy SSE
|
||||
when penalty applicable.
|
||||
.It Li OTHER_ASSISTS.SSE_TO_AVX
|
||||
.Pq Event C1H , Umask 10H
|
||||
Number of transitions from SSE to AVX-256 when
|
||||
penalty applicable.
|
||||
Number of transitions from SSE to AVX-256 when
|
||||
penalty applicable.
|
||||
.It Li OTHER_ASSISTS.ANY_WB_ASSIST
|
||||
.Pq Event C1H , Umask 40H
|
||||
Number of microcode assists invoked by HW upon
|
||||
uop writeback.
|
||||
Number of microcode assists invoked by HW upon
|
||||
uop writeback.
|
||||
.It Li UOPS_RETIRED.ALL
|
||||
.Pq Event C2H , Umask 01H
|
||||
Counts the number of micro-ops retired, Use
|
||||
cmask=1 and invert to count active cycles or stalled
|
||||
cycles.
|
||||
Counts the number of micro-ops retired, Use
|
||||
cmask=1 and invert to count active cycles or stalled
|
||||
cycles.
|
||||
.It Li UOPS_RETIRED.RETIRE_SLOTS
|
||||
.Pq Event C2H , Umask 02H
|
||||
Counts the number of retirement slots used each
|
||||
Counts the number of retirement slots used each
|
||||
cycle.
|
||||
.It Li MACHINE_CLEARS.MEMORY_ORDERING
|
||||
.Pq Event C3H , Umask 02H
|
||||
Counts the number of machine clears due to memory
|
||||
order conflicts.
|
||||
Counts the number of machine clears due to memory
|
||||
order conflicts.
|
||||
.It Li MACHINE_CLEARS.SMC
|
||||
.Pq Event C3H , Umask 04H
|
||||
Number of self-modifying-code machine clears
|
||||
Number of self-modifying-code machine clears
|
||||
detected.
|
||||
.It Li MACHINE_CLEARS.MASKMOV
|
||||
.Pq Event C3H , Umask 20H
|
||||
Counts the number of executed AVX masked load
|
||||
operations that refer to an illegal address range with
|
||||
the mask bits set to 0.
|
||||
Counts the number of executed AVX masked load
|
||||
operations that refer to an illegal address range with
|
||||
the mask bits set to 0.
|
||||
.It Li BR_INST_RETIRED.ALL_BRANCHES
|
||||
.Pq Event C4H , Umask 00H
|
||||
Branch instructions at retirement.
|
||||
Branch instructions at retirement.
|
||||
.It Li BR_INST_RETIRED.CONDITIONAL
|
||||
.Pq Event C4H , Umask 01H
|
||||
Counts the number of conditional branch instructions Supports PEBS
|
||||
retired.
|
||||
.It Li BR_INST_RETIRED.NEAR_CALL
|
||||
.Pq Event C4H , Umask 02H
|
||||
Direct and indirect near call instructions retired.
|
||||
Direct and indirect near call instructions retired.
|
||||
.It Li BR_INST_RETIRED.ALL_BRANCHES
|
||||
.Pq Event C4H , Umask 04H
|
||||
Counts the number of branch instructions retired.
|
||||
Counts the number of branch instructions retired.
|
||||
.It Li BR_INST_RETIRED.NEAR_RETURN
|
||||
.Pq Event C4H , Umask 08H
|
||||
Counts the number of near return instructions
|
||||
retired.
|
||||
Counts the number of near return instructions
|
||||
retired.
|
||||
.It Li BR_INST_RETIRED.NOT_TAKEN
|
||||
.Pq Event C4H , Umask 10H
|
||||
Counts the number of not taken branch instructions
|
||||
retired.
|
||||
Counts the number of not taken branch instructions
|
||||
retired.
|
||||
It Li BR_INST_RETIRED.NEAR_TAKEN
|
||||
.Pq Event C4H , Umask 20H
|
||||
Number of near taken branches retired.
|
||||
@ -847,10 +847,10 @@ Qualify any retired memory uops. Must combine with Supports PEBS and
|
||||
umask 01H, 02H, to produce counts.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.L1_HIT
|
||||
.Pq Event D1H , Umask 01H
|
||||
Retired load uops with L1 cache hits as data sources.
|
||||
Retired load uops with L1 cache hits as data sources.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.L2_HIT
|
||||
.Pq Event D1H , Umask 02H
|
||||
Retired load uops with L2 cache hits as data sources.
|
||||
Retired load uops with L2 cache hits as data sources.
|
||||
.It Li MEM_LOAD_UOPS_RETIRED.LLC_HIT
|
||||
.Pq Event D1H , Umask 04H
|
||||
Retired load uops with LLC cache hits as data
|
||||
@ -870,64 +870,64 @@ Retired load uops which data sources were LLC hit
|
||||
and cross-core snoop missed in on-pkg core cache.
|
||||
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HIT
|
||||
.Pq Event D2H , Umask 02H
|
||||
Retired load uops which data sources were LLC and
|
||||
cross-core snoop hits in on-pkg core cache.
|
||||
Retired load uops which data sources were LLC and
|
||||
cross-core snoop hits in on-pkg core cache.
|
||||
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_HITM
|
||||
.Pq Event D2H , Umask 04H
|
||||
Retired load uops which data sources were HitM
|
||||
responses from shared LLC.
|
||||
Retired load uops which data sources were HitM
|
||||
responses from shared LLC.
|
||||
.It Li MEM_LOAD_UOPS_LLC_HIT_RETIRED.XSNP_NONE
|
||||
.Pq Event D2H , Umask 08H
|
||||
Retired load uops which data sources were hits in
|
||||
LLC without snoops required.
|
||||
Retired load uops which data sources were hits in
|
||||
LLC without snoops required.
|
||||
.It Li MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM
|
||||
.Pq Event D3H , Umask 01H
|
||||
Retired load uops which data sources missed LLC but
|
||||
Retired load uops which data sources missed LLC but
|
||||
serviced from local dram.
|
||||
.It Li BACLEARS.ANY
|
||||
.Pq Event E6H , Umask 1FH
|
||||
Number of front end re-steers due to BPU
|
||||
misprediction.
|
||||
Number of front end re-steers due to BPU
|
||||
misprediction.
|
||||
.It Li L2_TRANS.DEMAND_DATA_RD
|
||||
.Pq Event F0H , Umask 01H
|
||||
Demand Data Read requests that access L2 cache.
|
||||
Demand Data Read requests that access L2 cache.
|
||||
.It Li L2_TRANS.RFO
|
||||
.Pq Event F0H , Umask 02H
|
||||
RFO requests that access L2 cache.
|
||||
RFO requests that access L2 cache.
|
||||
.It Li L2_TRANS.CODE_RD
|
||||
.Pq Event F0H , Umask 04H
|
||||
L2 cache accesses when fetching instructions.
|
||||
L2 cache accesses when fetching instructions.
|
||||
.It Li L2_TRANS.ALL_PF
|
||||
.Pq Event F0H , Umask 08H
|
||||
Any MLC or LLC HW prefetch accessing L2, including
|
||||
rejects.
|
||||
Any MLC or LLC HW prefetch accessing L2, including
|
||||
rejects.
|
||||
.It Li L2_TRANS.L1D_WB
|
||||
.Pq Event F0H , Umask 10H
|
||||
L1D writebacks that access L2 cache.
|
||||
L1D writebacks that access L2 cache.
|
||||
.It Li L2_TRANS.L2_FILL
|
||||
.Pq Event F0H , Umask 20H
|
||||
L2 fill requests that access L2 cache.
|
||||
L2 fill requests that access L2 cache.
|
||||
.It Li L2_TRANS.L2_WB
|
||||
.Pq Event F0H , Umask 40H
|
||||
L2 writebacks that access L2 cache.
|
||||
L2 writebacks that access L2 cache.
|
||||
.It Li L2_TRANS.ALL_REQUESTS
|
||||
.Pq Event F0H , Umask 80H
|
||||
Transactions accessing L2 pipe.
|
||||
Transactions accessing L2 pipe.
|
||||
.It Li L2_LINES_IN.I
|
||||
.Pq Event F1H , Umask 01H
|
||||
L2 cache lines in I state filling L2.
|
||||
L2 cache lines in I state filling L2.
|
||||
.It Li L2_LINES_IN.S
|
||||
.Pq Event F1H , Umask 02H
|
||||
L2 cache lines in S state filling L2.
|
||||
L2 cache lines in S state filling L2.
|
||||
.It Li L2_LINES_IN.E
|
||||
.Pq Event F1H , Umask 04H
|
||||
L2 cache lines in E state filling L2.
|
||||
L2 cache lines in E state filling L2.
|
||||
.It Li L2_LINES_IN.ALL
|
||||
.Pq Event F1H , Umask 07H
|
||||
L2 cache lines filling L2.
|
||||
L2 cache lines filling L2.
|
||||
.It Li L2_LINES_OUT.DEMAND_CLEAN
|
||||
.Pq Event F2H , Umask 05H
|
||||
Clean L2 cache lines evicted by demand.
|
||||
Clean L2 cache lines evicted by demand.
|
||||
.It Li L2_LINES_OUT.DEMAND_DIRTY
|
||||
.Pq Event F2H , Umask 06H
|
||||
Dirty L2 cache lines evicted by demand.
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com>
|
||||
.\" Copyright (c) 2013 Hiren Panchasara <hiren.panchasara@gmail.com>
|
||||
.\" All rights reserved.
|
||||
.\"
|
||||
.\" Redistribution and use in source and binary forms, with or without
|
||||
@ -141,7 +141,7 @@ Filter on cross-core snoops initiated by this Cbox due
|
||||
to LLC eviction.
|
||||
.It Li UNC_CBO_CACHE_LOOKUP.M
|
||||
.Pq Event 34H , Umask 01H
|
||||
LLC lookup request that access cache and found line in
|
||||
LLC lookup request that access cache and found line in
|
||||
M-state.
|
||||
.It Li UNC_CBO_CACHE_LOOKUP.ES
|
||||
.Pq Event 34H , Umask 06H
|
||||
@ -231,7 +231,7 @@ The
|
||||
library was written by
|
||||
.An "Joseph Koshy"
|
||||
.Aq jkoshy@FreeBSD.org .
|
||||
The support for the Haswell
|
||||
The support for the Haswell
|
||||
microarchitecture was added by
|
||||
.An "Hiren Panchasara"
|
||||
.Aq hiren.panchasara@gmail.com .
|
||||
|
||||
Loading…
Reference in New Issue
Block a user