mirror of
https://github.com/freebsd/freebsd-src.git
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- fix qset to port binding as a proper fix for the problems encountered on the 4-port
- fix the use after free seen when sending packets small enough to fit as an immediate and bpf peers are present - update to firmware rev 4.7 along with various small vendor fixes Supported by: Chelsio Approved by: re (blanket) MFC after: 3 days
This commit is contained in:
Kip Macy
parent
cd41628daf
commit
5c5df3da16
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=172096
@ -40,6 +40,7 @@ $FreeBSD$
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enum {
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MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */
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EEPROMSIZE = 8192, /* Serial EEPROM size */
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SERNUM_LEN = 16, /* Serial # length */
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RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
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TCB_SIZE = 128, /* TCB size */
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NMTUS = 16, /* size of MTU table */
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@ -98,7 +99,7 @@ enum {
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enum {
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FW_VERSION_MAJOR = 4,
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FW_VERSION_MINOR = 5,
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FW_VERSION_MINOR = 7,
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FW_VERSION_MICRO = 0
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};
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@ -348,6 +349,7 @@ struct vpd_params {
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unsigned int uclk;
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unsigned int mdc;
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unsigned int mem_timing;
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u8 sn[SERNUM_LEN + 1];
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u8 eth_base[6];
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u8 port_type[MAX_NPORTS];
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unsigned short xauicfg[2];
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@ -474,6 +476,7 @@ struct cmac {
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u64 rx_mcnt;
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unsigned int toggle_cnt;
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unsigned int txen;
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u64 rx_pause;
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struct mac_stats stats;
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};
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@ -35,13 +35,13 @@ enum {
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RDMA_CTRL_QP_SETUP,
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RDMA_GET_MEM,
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FAILOVER,
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FAILOVER_DONE,
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FAILOVER_CLEAR,
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FAILOVER = 30,
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FAILOVER_DONE = 31,
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FAILOVER_CLEAR = 32,
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GET_CPUIDX_OF_QSET,
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GET_CPUIDX_OF_QSET = 40,
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GET_RX_PAGE_INFO,
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GET_RX_PAGE_INFO = 50,
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};
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/*
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@ -136,6 +136,10 @@ $FreeBSD$
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#define V_CQ_GEN(x) ((x) << S_CQ_GEN)
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#define F_CQ_GEN V_CQ_GEN(1U)
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#define S_CQ_ERR 30
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#define V_CQ_ERR(x) ((x) << S_CQ_ERR)
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#define F_CQ_ERR V_CQ_ERR(1U)
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#define S_CQ_OVERFLOW_MODE 31
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#define V_CQ_OVERFLOW_MODE(x) ((x) << S_CQ_OVERFLOW_MODE)
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#define F_CQ_OVERFLOW_MODE V_CQ_OVERFLOW_MODE(1U)
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@ -28,7 +28,7 @@ POSSIBILITY OF SUCH DAMAGE.
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***************************************************************************/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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_FBSDID("$FreeBSD$");
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#ifdef CONFIG_DEFINED
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@ -40,7 +40,6 @@ __FBSDID("$FreeBSD$");
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#undef msleep
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#define msleep t3_os_sleep
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/**
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* t3_wait_op_done_val - wait until an operation is completed
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* @adapter: the adapter performing the operation
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@ -515,7 +514,7 @@ struct t3_vpd {
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u8 vpdr_len[2];
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VPD_ENTRY(pn, 16); /* part number */
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VPD_ENTRY(ec, 16); /* EC level */
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VPD_ENTRY(sn, 16); /* serial number */
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VPD_ENTRY(sn, SERNUM_LEN); /* serial number */
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VPD_ENTRY(na, 12); /* MAC address base */
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VPD_ENTRY(cclk, 6); /* core clock */
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VPD_ENTRY(mclk, 6); /* mem clock */
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@ -658,6 +657,7 @@ static int get_vpd_params(adapter_t *adapter, struct vpd_params *p)
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p->uclk = simple_strtoul(vpd.uclk_data, NULL, 10);
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p->mdc = simple_strtoul(vpd.mdc_data, NULL, 10);
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p->mem_timing = simple_strtoul(vpd.mt_data, NULL, 10);
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memcpy(p->sn, vpd.sn_data, SERNUM_LEN);
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/* Old eeproms didn't have port information */
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if (adapter->params.rev == 0 && !vpd.port0_data[0]) {
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@ -908,7 +908,7 @@ int t3_check_tpsram_version(adapter_t *adapter)
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if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR)
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return 0;
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CH_ERR(adapter, "found wrong TP version (%u.%u), "
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CH_WARN(adapter, "found wrong TP version (%u.%u), "
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"driver needs version %d.%d\n", major, minor,
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TP_VERSION_MAJOR, TP_VERSION_MINOR);
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return -EINVAL;
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@ -984,9 +984,9 @@ int t3_check_fw_version(adapter_t *adapter)
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minor == FW_VERSION_MINOR)
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return 0;
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CH_ERR(adapter, "found wrong FW version (%u.%u), "
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"driver needs version %d.%d\n", major, minor,
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FW_VERSION_MAJOR, FW_VERSION_MINOR);
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CH_WARN(adapter, "found wrong FW version (%u.%u), "
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"driver needs version %d.%d\n", major, minor,
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FW_VERSION_MAJOR, FW_VERSION_MINOR);
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return -EINVAL;
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}
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@ -1072,7 +1072,6 @@ out:
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/**
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* t3_cim_ctl_blk_read - read a block from CIM control region
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*
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* @adap: the adapter
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* @addr: the start address within the CIM control region
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* @n: number of words to read
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@ -1348,6 +1347,10 @@ static void pcie_intr_handler(adapter_t *adapter)
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{ 0 }
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};
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if (t3_read_reg(adapter, A_PCIE_INT_CAUSE) & F_PEXERR)
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CH_ALERT(adapter, "PEX error code 0x%x\n",
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t3_read_reg(adapter, A_PCIE_PEX_ERR));
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if (t3_handle_intr_status(adapter, A_PCIE_INT_CAUSE, PCIE_INTR_MASK,
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pcie_intr_info, adapter->irq_stats))
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t3_fatal_err(adapter);
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@ -1646,8 +1649,13 @@ int t3_phy_intr_handler(adapter_t *adapter)
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return 0;
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}
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/*
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* T3 slow path (non-data) interrupt handler.
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/**
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* t3_slow_intr_handler - control path interrupt handler
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* @adapter: the adapter
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*
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* T3 interrupt handler for non-data interrupt events, e.g., errors.
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* The designation 'slow' is because it involves register reads, while
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* data interrupts typically don't involve any MMIOs.
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*/
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int t3_slow_intr_handler(adapter_t *adapter)
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{
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@ -1803,6 +1811,8 @@ void t3_intr_clear(adapter_t *adapter)
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for (i = 0; i < ARRAY_SIZE(cause_reg_addr); ++i)
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t3_write_reg(adapter, cause_reg_addr[i], 0xffffffff);
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if (is_pcie(adapter))
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t3_write_reg(adapter, A_PCIE_PEX_ERR, 0xffffffff);
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t3_write_reg(adapter, A_PL_INT_CAUSE0, 0xffffffff);
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(void) t3_read_reg(adapter, A_PL_INT_CAUSE0); /* flush */
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}
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@ -1855,6 +1865,8 @@ void t3_port_intr_clear(adapter_t *adapter, int idx)
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pi->phy.ops->intr_clear(&pi->phy);
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}
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#define SG_CONTEXT_CMD_ATTEMPTS 100
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/**
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* t3_sge_write_context - write an SGE context
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* @adapter: the adapter
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@ -1874,7 +1886,7 @@ static int t3_sge_write_context(adapter_t *adapter, unsigned int id,
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t3_write_reg(adapter, A_SG_CONTEXT_CMD,
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V_CONTEXT_CMD_OPCODE(1) | type | V_CONTEXT(id));
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return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
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0, 5, 1);
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0, SG_CONTEXT_CMD_ATTEMPTS, 1);
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}
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/**
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@ -2030,7 +2042,8 @@ int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr,
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base_addr >>= 32;
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t3_write_reg(adapter, A_SG_CONTEXT_DATA2,
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V_CQ_BASE_HI((u32)base_addr) | V_CQ_RSPQ(rspq) |
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V_CQ_GEN(1) | V_CQ_OVERFLOW_MODE(ovfl_mode));
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V_CQ_GEN(1) | V_CQ_OVERFLOW_MODE(ovfl_mode) |
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V_CQ_ERR(ovfl_mode));
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t3_write_reg(adapter, A_SG_CONTEXT_DATA3, V_CQ_CREDITS(credits) |
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V_CQ_CREDIT_THRES(credit_thres));
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return t3_sge_write_context(adapter, id, F_CQ);
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@ -2058,7 +2071,7 @@ int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable)
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t3_write_reg(adapter, A_SG_CONTEXT_CMD,
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V_CONTEXT_CMD_OPCODE(1) | F_EGRESS | V_CONTEXT(id));
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return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
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0, 5, 1);
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0, SG_CONTEXT_CMD_ATTEMPTS, 1);
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}
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/**
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@ -2082,7 +2095,7 @@ int t3_sge_disable_fl(adapter_t *adapter, unsigned int id)
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t3_write_reg(adapter, A_SG_CONTEXT_CMD,
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V_CONTEXT_CMD_OPCODE(1) | F_FREELIST | V_CONTEXT(id));
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return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
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0, 5, 1);
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0, SG_CONTEXT_CMD_ATTEMPTS, 1);
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}
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/**
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@ -2106,7 +2119,7 @@ int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id)
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t3_write_reg(adapter, A_SG_CONTEXT_CMD,
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V_CONTEXT_CMD_OPCODE(1) | F_RESPONSEQ | V_CONTEXT(id));
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return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
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0, 5, 1);
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0, SG_CONTEXT_CMD_ATTEMPTS, 1);
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}
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/**
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@ -2130,7 +2143,7 @@ int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id)
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t3_write_reg(adapter, A_SG_CONTEXT_CMD,
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V_CONTEXT_CMD_OPCODE(1) | F_CQ | V_CONTEXT(id));
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return t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
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0, 5, 1);
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0, SG_CONTEXT_CMD_ATTEMPTS, 1);
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}
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/**
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@ -2138,10 +2151,14 @@ int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id)
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* @adapter: the adapter
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* @id: the context id
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* @op: the operation to perform
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* @credits: credits to return to the CQ
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*
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* Perform the selected operation on an SGE completion queue context.
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* The caller is responsible for ensuring only one context operation
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* occurs at a time.
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*
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* For most operations the function returns the current HW position in
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* the completion queue.
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*/
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int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
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unsigned int credits)
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@ -2155,7 +2172,7 @@ int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
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t3_write_reg(adapter, A_SG_CONTEXT_CMD, V_CONTEXT_CMD_OPCODE(op) |
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V_CONTEXT(id) | F_CQ);
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if (t3_wait_op_done_val(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY,
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0, 5, 1, &val))
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0, SG_CONTEXT_CMD_ATTEMPTS, 1, &val))
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return -EIO;
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if (op >= 2 && op < 7) {
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@ -2165,7 +2182,8 @@ int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
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t3_write_reg(adapter, A_SG_CONTEXT_CMD,
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V_CONTEXT_CMD_OPCODE(0) | F_CQ | V_CONTEXT(id));
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if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD,
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F_CONTEXT_CMD_BUSY, 0, 5, 1))
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F_CONTEXT_CMD_BUSY, 0,
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SG_CONTEXT_CMD_ATTEMPTS, 1))
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return -EIO;
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return G_CQ_INDEX(t3_read_reg(adapter, A_SG_CONTEXT_DATA0));
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}
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@ -2191,7 +2209,7 @@ static int t3_sge_read_context(unsigned int type, adapter_t *adapter,
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t3_write_reg(adapter, A_SG_CONTEXT_CMD,
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V_CONTEXT_CMD_OPCODE(0) | type | V_CONTEXT(id));
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if (t3_wait_op_done(adapter, A_SG_CONTEXT_CMD, F_CONTEXT_CMD_BUSY, 0,
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5, 1))
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SG_CONTEXT_CMD_ATTEMPTS, 1))
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return -EIO;
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data[0] = t3_read_reg(adapter, A_SG_CONTEXT_DATA0);
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data[1] = t3_read_reg(adapter, A_SG_CONTEXT_DATA1);
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@ -2354,6 +2372,15 @@ void t3_tp_set_offload_mode(adapter_t *adap, int enable)
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V_NICMODE(!enable));
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}
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/**
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* tp_wr_bits_indirect - set/clear bits in an indirect TP register
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* @adap: the adapter
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* @addr: the indirect TP register address
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* @mask: specifies the field within the register to modify
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* @val: new value for the field
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*
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* Sets a field of an indirect TP register to the given value.
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*/
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static void tp_wr_bits_indirect(adapter_t *adap, unsigned int addr,
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unsigned int mask, unsigned int val)
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{
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@ -2397,7 +2424,7 @@ static inline unsigned int pm_num_pages(unsigned int mem_size,
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t3_write_reg((adap), A_ ## reg, (start)); \
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start += size
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/*
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/**
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* partition_mem - partition memory and configure TP memory settings
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* @adap: the adapter
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* @p: the TP parameters
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@ -2646,8 +2673,12 @@ static void __devinit init_mtus(unsigned short mtus[])
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mtus[15] = 9600;
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}
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/*
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* Initial congestion control parameters.
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/**
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* init_cong_ctrl - initialize congestion control parameters
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* @a: the alpha values for congestion control
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* @b: the beta values for congestion control
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*
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* Initialize the congestion control parameters.
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*/
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static void __devinit init_cong_ctrl(unsigned short *a, unsigned short *b)
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{
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@ -2693,7 +2724,7 @@ static void __devinit init_cong_ctrl(unsigned short *a, unsigned short *b)
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* t3_load_mtus - write the MTU and congestion control HW tables
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* @adap: the adapter
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* @mtus: the unrestricted values for the MTU table
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* @alphs: the values for the congestion control alpha parameter
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* @alpha: the values for the congestion control alpha parameter
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* @beta: the values for the congestion control beta parameter
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* @mtu_cap: the maximum permitted effective MTU
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*
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@ -2860,7 +2891,7 @@ static void ulp_config(adapter_t *adap, const struct tp_params *p)
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int t3_set_proto_sram(adapter_t *adap, const u8 *data)
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{
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int i;
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u32 *buf = (u32 *)(uintptr_t)data;
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const u32 *buf = (const u32 *)data;
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for (i = 0; i < PROTO_SRAM_LINES; i++) {
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t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, cpu_to_be32(*buf++));
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@ -2877,6 +2908,16 @@ int t3_set_proto_sram(adapter_t *adap, const u8 *data)
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}
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#endif
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/**
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* t3_config_trace_filter - configure one of the tracing filters
|
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* @adapter: the adapter
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* @tp: the desired trace filter parameters
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* @filter_index: which filter to configure
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* @invert: if set non-matching packets are traced instead of matching ones
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* @enable: whether to enable or disable the filter
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*
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* Configures one of the tracing filters available in HW.
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*/
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void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
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int filter_index, int invert, int enable)
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{
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@ -3022,6 +3063,13 @@ void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps,
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}
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}
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/**
|
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* tp_init - configure TP
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* @adap: the adapter
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* @p: TP configuration parameters
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*
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* Initializes the TP HW module.
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*/
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static int tp_init(adapter_t *adap, const struct tp_params *p)
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{
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int busy = 0;
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@ -3043,6 +3091,13 @@ static int tp_init(adapter_t *adap, const struct tp_params *p)
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return busy;
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}
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/**
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* t3_mps_set_active_ports - configure port failover
|
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* @adap: the adapter
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* @port_mask: bitmap of active ports
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*
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* Sets the active ports according to the supplied bitmap.
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*/
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int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask)
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{
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if (port_mask & ~((1 << adap->params.nports) - 1))
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@ -3052,9 +3107,13 @@ int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask)
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return 0;
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}
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|
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/*
|
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* Perform the bits of HW initialization that are dependent on the Tx
|
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* channels being used.
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/**
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* chan_init_hw - channel-dependent HW initialization
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* @adap: the adapter
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* @chan_map: bitmap of Tx channels being used
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*
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* Perform the bits of HW initialization that are dependent on the Tx
|
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* channels being used.
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*/
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static void chan_init_hw(adapter_t *adap, unsigned int chan_map)
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{
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@ -3068,6 +3127,11 @@ static void chan_init_hw(adapter_t *adap, unsigned int chan_map)
|
||||
F_TPTXPORT1EN | F_PORT1ACTIVE));
|
||||
t3_write_reg(adap, A_PM1_TX_CFG,
|
||||
chan_map == 1 ? 0xffffffff : 0);
|
||||
if (chan_map == 2)
|
||||
t3_write_reg(adap, A_TP_TX_MOD_QUEUE_REQ_MAP,
|
||||
V_TX_MOD_QUEUE_REQ_MAP(0xff));
|
||||
t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (12 << 16) | 0xd9c8);
|
||||
t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (13 << 16) | 0xfbea);
|
||||
} else { /* two channels */
|
||||
t3_set_reg_field(adap, A_ULPRX_CTL, 0, F_ROUND_ROBIN);
|
||||
t3_set_reg_field(adap, A_ULPTX_CONFIG, 0, F_CFG_RR_ARB);
|
||||
@ -3083,6 +3147,8 @@ static void chan_init_hw(adapter_t *adap, unsigned int chan_map)
|
||||
for (i = 0; i < 16; i++)
|
||||
t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE,
|
||||
(i << 16) | 0x1010);
|
||||
t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (12 << 16) | 0xba98);
|
||||
t3_write_reg(adap, A_TP_TX_MOD_QUE_TABLE, (13 << 16) | 0xfedc);
|
||||
}
|
||||
}
|
||||
|
||||
@ -3320,13 +3386,18 @@ static void config_pcie(adapter_t *adap)
|
||||
t3_set_reg_field(adap, A_PCIE_CFG, F_PCIE_CLIDECEN, F_PCIE_CLIDECEN);
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize and configure T3 HW modules. This performs the
|
||||
* initialization steps that need to be done once after a card is reset.
|
||||
* MAC and PHY initialization is handled separarely whenever a port is enabled.
|
||||
/**
|
||||
* t3_init_hw - initialize and configure T3 HW modules
|
||||
* @adapter: the adapter
|
||||
* @fw_params: initial parameters to pass to firmware (optional)
|
||||
*
|
||||
* fw_params are passed to FW and their value is platform dependent. Only the
|
||||
* top 8 bits are available for use, the rest must be 0.
|
||||
* Initialize and configure T3 HW modules. This performs the
|
||||
* initialization steps that need to be done once after a card is reset.
|
||||
* MAC and PHY initialization is handled separarely whenever a port is
|
||||
* enabled.
|
||||
*
|
||||
* @fw_params are passed to FW and their value is platform dependent.
|
||||
* Only the top 8 bits are available for use, the rest must be 0.
|
||||
*/
|
||||
int t3_init_hw(adapter_t *adapter, u32 fw_params)
|
||||
{
|
||||
@ -3370,6 +3441,8 @@ int t3_init_hw(adapter_t *adapter, u32 fw_params)
|
||||
t3_set_reg_field(adapter, A_PCIX_CFG, 0, F_CLIDECEN);
|
||||
|
||||
t3_write_reg(adapter, A_PM1_RX_CFG, 0xffffffff);
|
||||
t3_write_reg(adapter, A_PM1_RX_MODE, 0);
|
||||
t3_write_reg(adapter, A_PM1_TX_MODE, 0);
|
||||
chan_init_hw(adapter, adapter->params.chan_map);
|
||||
t3_sge_init(adapter, &adapter->params.sge);
|
||||
|
||||
@ -3433,7 +3506,7 @@ static void __devinit get_pci_mode(adapter_t *adapter, struct pci_params *p)
|
||||
/**
|
||||
* init_link_config - initialize a link's SW state
|
||||
* @lc: structure holding the link state
|
||||
* @ai: information about the current card
|
||||
* @caps: link capabilities
|
||||
*
|
||||
* Initializes the SW state maintained for each link, including the link's
|
||||
* capabilities and default speed/duplex/flow-control/autonegotiation
|
||||
@ -3508,6 +3581,15 @@ void mac_prep(struct cmac *mac, adapter_t *adapter, int index)
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* early_hw_init - HW initialization done at card detection time
|
||||
* @adapter: the adapter
|
||||
* @ai: contains information about the adapter type and properties
|
||||
*
|
||||
* Perfoms the part of HW initialization that is done early on when the
|
||||
* driver first detecs the card. Most of the HW state is initialized
|
||||
* lazily later on when a port or an offload function are first used.
|
||||
*/
|
||||
void early_hw_init(adapter_t *adapter, const struct adapter_info *ai)
|
||||
{
|
||||
u32 val = V_PORTSPEED(is_10G(adapter) || adapter->params.nports > 2 ?
|
||||
@ -3534,9 +3616,11 @@ void early_hw_init(adapter_t *adapter, const struct adapter_info *ai)
|
||||
(void) t3_read_reg(adapter, A_XGM_PORT_CFG);
|
||||
}
|
||||
|
||||
/*
|
||||
* Reset the adapter. PCIe cards lose their config space during reset, PCI-X
|
||||
* ones don't.
|
||||
/**
|
||||
* t3_reset_adapter - reset the adapter
|
||||
* @adapter: the adapter
|
||||
*
|
||||
* Reset the adapter.
|
||||
*/
|
||||
static int t3_reset_adapter(adapter_t *adapter)
|
||||
{
|
||||
@ -3567,10 +3651,14 @@ static int t3_reset_adapter(adapter_t *adapter)
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize adapter SW state for the various HW modules, set initial values
|
||||
* for some adapter tunables, take PHYs out of reset, and initialize the MDIO
|
||||
* interface.
|
||||
/**
|
||||
* t3_prep_adapter - prepare SW and HW for operation
|
||||
* @adapter: the adapter
|
||||
* @ai: contains information about the adapter type and properties
|
||||
*
|
||||
* Initialize adapter SW state for the various HW modules, set initial
|
||||
* values for some adapter tunables, take PHYs out of reset, and
|
||||
* initialize the MDIO interface.
|
||||
*/
|
||||
int __devinit t3_prep_adapter(adapter_t *adapter,
|
||||
const struct adapter_info *ai, int reset)
|
||||
|
||||
@ -43,6 +43,11 @@ enum {
|
||||
ELMR_DATA_LO = 2,
|
||||
ELMR_DATA_HI = 3,
|
||||
|
||||
ELMR_THRES0 = 0xe000,
|
||||
ELMR_BW = 0xe00c,
|
||||
ELMR_FIFO_SZ = 0xe00d,
|
||||
ELMR_STATS = 0xf000,
|
||||
|
||||
ELMR_MDIO_ADDR = 10
|
||||
};
|
||||
|
||||
@ -74,7 +79,7 @@ static int elmr_write(adapter_t *adap, int addr, u32 val)
|
||||
|
||||
int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n)
|
||||
{
|
||||
int ret;
|
||||
int i, ret;
|
||||
unsigned int v;
|
||||
const struct mdio_ops *mo = adapter_info(adap)->mdio_ops;
|
||||
|
||||
@ -83,9 +88,15 @@ int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n)
|
||||
ret = mo->write(adap, ELMR_MDIO_ADDR, 0, ELMR_ADDR, start);
|
||||
if (ret)
|
||||
goto out;
|
||||
ret = mo->read(adap, ELMR_MDIO_ADDR, 0, ELMR_STAT, &v);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
for (i = 0; i < 5; i++) {
|
||||
ret = mo->read(adap, ELMR_MDIO_ADDR, 0, ELMR_STAT, &v);
|
||||
if (ret)
|
||||
goto out;
|
||||
if (v == 1)
|
||||
break;
|
||||
udelay(5);
|
||||
}
|
||||
if (v != 1) {
|
||||
ret = -ETIMEDOUT;
|
||||
goto out;
|
||||
@ -148,7 +159,7 @@ int t3_vsc7323_init(adapter_t *adap, int nports)
|
||||
(ret = elmr_write(adap, VSC_REG(2, 0, 0x10 + i),
|
||||
((ing_bot + ing_step) << 16) | ing_bot)) ||
|
||||
(ret = elmr_write(adap, VSC_REG(2, 0, 0x40 + i),
|
||||
0x6000a00)) ||
|
||||
0x6000bc0)) ||
|
||||
(ret = elmr_write(adap, VSC_REG(2, 0, 0x50 + i), 1)) ||
|
||||
(ret = elmr_write(adap, VSC_REG(2, 1, 0x10 + i),
|
||||
((egr_bot + egr_step) << 16) | egr_bot)) ||
|
||||
@ -175,8 +186,13 @@ int t3_vsc7323_init(adapter_t *adap, int nports)
|
||||
(ret = elmr_write(adap, VSC_REG(1, i, 5),
|
||||
(i << 12) | 0x63)) ||
|
||||
(ret = elmr_write(adap, VSC_REG(1, i, 0xb), 0x96)) ||
|
||||
(ret = elmr_write(adap, VSC_REG(1, i, 0x15), 0x21)))
|
||||
(ret = elmr_write(adap, VSC_REG(1, i, 0x15), 0x21)) ||
|
||||
(ret = elmr_write(adap, ELMR_THRES0 + i, 768)))
|
||||
return ret;
|
||||
|
||||
if ((ret = elmr_write(adap, ELMR_BW, 7)))
|
||||
return ret;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -269,6 +285,8 @@ int t3_vsc7323_disable(adapter_t *adap, int port, int which)
|
||||
#define NSTATS0 (0x1d - STATS0_START + 1)
|
||||
#define NSTATS1 (0x2a - STATS1_START + 1)
|
||||
|
||||
#define ELMR_STAT(port, reg) (ELMR_STATS + port * 0x40 + reg)
|
||||
|
||||
const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac)
|
||||
{
|
||||
int ret;
|
||||
@ -276,11 +294,11 @@ const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac)
|
||||
u32 stats0[NSTATS0], stats1[NSTATS1];
|
||||
|
||||
ret = t3_elmr_blk_read(mac->adapter,
|
||||
VSC_REG(4, mac->ext_port, STATS0_START),
|
||||
ELMR_STAT(mac->ext_port, STATS0_START),
|
||||
stats0, NSTATS0);
|
||||
if (!ret)
|
||||
ret = t3_elmr_blk_read(mac->adapter,
|
||||
VSC_REG(4, mac->ext_port, STATS1_START),
|
||||
ELMR_STAT(mac->ext_port, STATS1_START),
|
||||
stats1, NSTATS1);
|
||||
if (ret)
|
||||
goto out;
|
||||
|
||||
@ -492,9 +492,11 @@ int t3_mac_enable(struct cmac *mac, int which)
|
||||
A_XGM_TX_SPI4_SOP_EOP_CNT +
|
||||
oft)));
|
||||
mac->rx_mcnt = s->rx_frames;
|
||||
mac->rx_pause = s->rx_pause;
|
||||
mac->rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
|
||||
A_XGM_RX_SPI4_SOP_EOP_CNT +
|
||||
oft)));
|
||||
mac->rx_ocnt = s->rx_fifo_ovfl;
|
||||
mac->txen = F_TXEN;
|
||||
mac->toggle_cnt = 0;
|
||||
}
|
||||
@ -506,22 +508,21 @@ int t3_mac_enable(struct cmac *mac, int which)
|
||||
int t3_mac_disable(struct cmac *mac, int which)
|
||||
{
|
||||
adapter_t *adap = mac->adapter;
|
||||
int val;
|
||||
|
||||
if (mac->multiport)
|
||||
return t3_vsc7323_disable(adap, mac->ext_port, which);
|
||||
|
||||
if (which & MAC_DIRECTION_TX) {
|
||||
val = t3_read_reg(adap, A_MPS_CFG);
|
||||
t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
|
||||
mac->txen = 0;
|
||||
}
|
||||
if (which & MAC_DIRECTION_RX) {
|
||||
int val = F_MAC_RESET_;
|
||||
|
||||
t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
|
||||
F_PCS_RESET_, 0);
|
||||
msleep(100);
|
||||
t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
|
||||
val = F_MAC_RESET_;
|
||||
if (is_10G(adap))
|
||||
val |= F_PCS_RESET_;
|
||||
else if (uses_xaui(adap))
|
||||
@ -554,7 +555,7 @@ int t3b2_mac_watchdog_task(struct cmac *mac)
|
||||
tx_xcnt = 1; /* By default tx_xcnt is making progress*/
|
||||
tx_tcnt = mac->tx_tcnt; /* If tx_mcnt is progressing ignore tx_tcnt*/
|
||||
rx_xcnt = 1; /* By default rx_xcnt is making progress*/
|
||||
if (tx_mcnt == mac->tx_mcnt) {
|
||||
if (tx_mcnt == mac->tx_mcnt && mac->rx_pause == s->rx_pause) {
|
||||
tx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
|
||||
A_XGM_TX_SPI4_SOP_EOP_CNT +
|
||||
mac->offset)));
|
||||
@ -571,10 +572,7 @@ int t3b2_mac_watchdog_task(struct cmac *mac)
|
||||
goto rxcheck;
|
||||
}
|
||||
|
||||
if (((tx_tcnt != mac->tx_tcnt) &&
|
||||
(tx_xcnt == 0) && (mac->tx_xcnt == 0)) ||
|
||||
((mac->tx_mcnt == tx_mcnt) &&
|
||||
(tx_xcnt != 0) && (mac->tx_xcnt != 0))) {
|
||||
if ((tx_tcnt != mac->tx_tcnt) && (mac->tx_xcnt == 0)) {
|
||||
if (mac->toggle_cnt > 4) {
|
||||
status = 2;
|
||||
goto out;
|
||||
@ -609,6 +607,7 @@ out:
|
||||
mac->tx_mcnt = s->tx_frames;
|
||||
mac->rx_xcnt = rx_xcnt;
|
||||
mac->rx_mcnt = s->rx_frames;
|
||||
mac->rx_pause = s->rx_pause;
|
||||
if (status == 1) {
|
||||
t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
|
||||
t3_read_reg(adap, A_XGM_TX_CTRL + mac->offset); /* flush */
|
||||
|
||||
@ -174,6 +174,7 @@ struct t3_lro_session {
|
||||
struct mbuf *tail;
|
||||
uint32_t seq;
|
||||
uint16_t ip_len;
|
||||
uint16_t mss;
|
||||
uint16_t vtag;
|
||||
uint8_t npkts;
|
||||
};
|
||||
@ -510,7 +511,7 @@ void t3_sge_stop(adapter_t *);
|
||||
void t3b_intr(void *data);
|
||||
void t3_intr_msi(void *data);
|
||||
void t3_intr_msix(void *data);
|
||||
int t3_encap(struct port_info *, struct mbuf **);
|
||||
int t3_encap(struct port_info *, struct mbuf **, int *free);
|
||||
|
||||
int t3_sge_init_adapter(adapter_t *);
|
||||
int t3_sge_init_port(struct port_info *);
|
||||
|
||||
@ -224,7 +224,8 @@ enum {
|
||||
MIN_TXQ_ENTRIES = 4,
|
||||
MIN_CTRL_TXQ_ENTRIES = 4,
|
||||
MIN_RSPQ_ENTRIES = 32,
|
||||
MIN_FL_ENTRIES = 32
|
||||
MIN_FL_ENTRIES = 32,
|
||||
MIN_FL_JUMBO_ENTRIES = 32
|
||||
};
|
||||
|
||||
struct filter_info {
|
||||
@ -780,7 +781,10 @@ static int
|
||||
setup_hw_filters(struct adapter *adap)
|
||||
{
|
||||
int i, err;
|
||||
|
||||
|
||||
#ifndef USE_FILTERS
|
||||
return (0);
|
||||
#endif
|
||||
if (adap->filters == NULL)
|
||||
return 0;
|
||||
|
||||
@ -803,7 +807,7 @@ setup_hw_filters(struct adapter *adap)
|
||||
static int
|
||||
setup_sge_qsets(adapter_t *sc)
|
||||
{
|
||||
int i, j, err, irq_idx, qset_idx;
|
||||
int i, j, err, irq_idx = 0, qset_idx = 0;
|
||||
u_int ntxq = SGE_TXQ_PER_SET;
|
||||
|
||||
if ((err = t3_sge_alloc(sc)) != 0) {
|
||||
@ -813,15 +817,11 @@ setup_sge_qsets(adapter_t *sc)
|
||||
|
||||
if (sc->params.rev > 0 && !(sc->flags & USING_MSI))
|
||||
irq_idx = -1;
|
||||
else
|
||||
irq_idx = 0;
|
||||
|
||||
for (qset_idx = 0, i = 0; i < (sc)->params.nports; i++) {
|
||||
for (i = 0; i < (sc)->params.nports; i++) {
|
||||
struct port_info *pi = &sc->port[i];
|
||||
|
||||
for (j = 0; j < pi->nqsets; j++, qset_idx++) {
|
||||
printf("allocating qset_idx=%d for port_id=%d\n",
|
||||
qset_idx, pi->port_id);
|
||||
err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports,
|
||||
(sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx,
|
||||
&sc->params.sge.qset[qset_idx], ntxq, pi);
|
||||
@ -1111,7 +1111,15 @@ void
|
||||
t3_fatal_err(struct adapter *sc)
|
||||
{
|
||||
u_int fw_status[4];
|
||||
|
||||
|
||||
if (sc->flags & FULL_INIT_DONE) {
|
||||
t3_sge_stop(sc);
|
||||
t3_write_reg(sc, A_XGM_TX_CTRL, 0);
|
||||
t3_write_reg(sc, A_XGM_RX_CTRL, 0);
|
||||
t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0);
|
||||
t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0);
|
||||
t3_intr_disable(sc);
|
||||
}
|
||||
device_printf(sc->dev,"encountered fatal error, operation suspended\n");
|
||||
if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status))
|
||||
device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n",
|
||||
@ -1271,7 +1279,7 @@ cxgb_link_start(struct port_info *p)
|
||||
ifp = p->ifp;
|
||||
|
||||
t3_init_rx_mode(&rm, p);
|
||||
if (!mac->multiport)
|
||||
if (!mac->multiport)
|
||||
t3_mac_reset(mac);
|
||||
t3_mac_set_mtu(mac, ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
|
||||
t3_mac_set_address(mac, 0, p->hw_addr);
|
||||
@ -1298,6 +1306,10 @@ setup_rss(adapter_t *adap)
|
||||
u_int nq[2];
|
||||
uint8_t cpus[SGE_QSETS + 1];
|
||||
uint16_t rspq_map[RSS_TABLE_SIZE];
|
||||
|
||||
|
||||
if ((adap->flags & USING_MSIX) == 0)
|
||||
return;
|
||||
|
||||
for (i = 0; i < SGE_QSETS; ++i)
|
||||
cpus[i] = i;
|
||||
@ -1309,9 +1321,11 @@ setup_rss(adapter_t *adap)
|
||||
|
||||
nq[pi->tx_chan] += pi->nqsets;
|
||||
}
|
||||
nq[0] = max(nq[0], 1U);
|
||||
nq[1] = max(nq[1], 1U);
|
||||
for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) {
|
||||
rspq_map[i] = nq[0] ? i % nq[0] : 0;
|
||||
rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0;
|
||||
rspq_map[i] = i % nq[0];
|
||||
rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq[1]) + nq[0];
|
||||
}
|
||||
/* Calculate the reverse RSS map table */
|
||||
for (i = 0; i < RSS_TABLE_SIZE; ++i)
|
||||
@ -1320,7 +1334,7 @@ setup_rss(adapter_t *adap)
|
||||
|
||||
t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN |
|
||||
F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN |
|
||||
F_RRCPLMAPEN | V_RRCPLCPUSIZE(6), cpus, rspq_map);
|
||||
V_RRCPLCPUSIZE(6), cpus, rspq_map);
|
||||
|
||||
}
|
||||
|
||||
@ -1414,9 +1428,11 @@ bind_qsets(adapter_t *sc)
|
||||
for (i = 0; i < (sc)->params.nports; ++i) {
|
||||
const struct port_info *pi = adap2pinfo(sc, i);
|
||||
|
||||
for (j = 0; j < pi->nqsets; ++j)
|
||||
for (j = 0; j < pi->nqsets; ++j) {
|
||||
send_pktsched_cmd(sc, 1, pi->first_qset + j, -1,
|
||||
-1, i);
|
||||
-1, pi->tx_chan);
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1581,7 +1597,8 @@ cxgb_up(struct adapter *sc)
|
||||
t3_sge_start(sc);
|
||||
t3_intr_enable(sc);
|
||||
|
||||
if ((sc->flags & (USING_MSIX | QUEUES_BOUND)) == USING_MSIX) {
|
||||
if (!(sc->flags & QUEUES_BOUND)) {
|
||||
printf("bind qsets\n");
|
||||
bind_qsets(sc);
|
||||
setup_hw_filters(sc);
|
||||
sc->flags |= QUEUES_BOUND;
|
||||
@ -1748,7 +1765,7 @@ cxgb_init_locked(struct port_info *p)
|
||||
t3_link_changed(sc, p->port_id);
|
||||
ifp->if_baudrate = p->link_config.speed * 1000000;
|
||||
|
||||
printf("enabling interrupts on port=%d\n", p->port_id);
|
||||
device_printf(sc->dev, "enabling interrupts on port=%d\n", p->port_id);
|
||||
t3_port_intr_enable(sc, p->port_id);
|
||||
|
||||
callout_reset(&sc->cxgb_tick_ch, sc->params.stats_update_period * hz,
|
||||
@ -1921,7 +1938,7 @@ cxgb_start_tx(struct ifnet *ifp, uint32_t txmax)
|
||||
struct sge_txq *txq;
|
||||
struct port_info *p = ifp->if_softc;
|
||||
struct mbuf *m0, *m = NULL;
|
||||
int err, in_use_init, qsidx = 0;
|
||||
int err, in_use_init, free;
|
||||
|
||||
if (!p->link_config.link_ok)
|
||||
return (ENXIO);
|
||||
@ -1929,10 +1946,7 @@ cxgb_start_tx(struct ifnet *ifp, uint32_t txmax)
|
||||
if (IFQ_DRV_IS_EMPTY(&ifp->if_snd))
|
||||
return (ENOBUFS);
|
||||
|
||||
if (p->adapter->params.nports <= 2)
|
||||
qsidx = p->first_qset;
|
||||
|
||||
qs = &p->adapter->sge.qs[qsidx];
|
||||
qs = &p->adapter->sge.qs[p->first_qset];
|
||||
txq = &qs->txq[TXQ_ETH];
|
||||
err = 0;
|
||||
|
||||
@ -1944,6 +1958,7 @@ cxgb_start_tx(struct ifnet *ifp, uint32_t txmax)
|
||||
in_use_init = txq->in_use;
|
||||
while ((txq->in_use - in_use_init < txmax) &&
|
||||
(txq->size > txq->in_use + TX_MAX_DESC)) {
|
||||
free = 0;
|
||||
IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
|
||||
if (m == NULL)
|
||||
break;
|
||||
@ -1974,9 +1989,11 @@ cxgb_start_tx(struct ifnet *ifp, uint32_t txmax)
|
||||
break;
|
||||
}
|
||||
m = m0;
|
||||
if ((err = t3_encap(p, &m)) != 0)
|
||||
if ((err = t3_encap(p, &m, &free)) != 0)
|
||||
break;
|
||||
BPF_MTAP(ifp, m);
|
||||
if (free)
|
||||
m_freem(m);
|
||||
}
|
||||
txq->flags &= ~TXQ_TRANSMITTING;
|
||||
mtx_unlock(&txq->lock);
|
||||
|
||||
@ -44,7 +44,6 @@ __FBSDID("$FreeBSD$");
|
||||
#include <sys/sysctl.h>
|
||||
#include <sys/taskqueue.h>
|
||||
|
||||
|
||||
#include <sys/proc.h>
|
||||
#include <sys/sched.h>
|
||||
#include <sys/smp.h>
|
||||
@ -1160,7 +1159,7 @@ write_wr_hdr_sgl(unsigned int ndesc, struct tx_desc *txd, struct txq_state *txqs
|
||||
#define TCPPKTHDRSIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 20 + 20)
|
||||
|
||||
int
|
||||
t3_encap(struct port_info *p, struct mbuf **m)
|
||||
t3_encap(struct port_info *p, struct mbuf **m, int *free)
|
||||
{
|
||||
adapter_t *sc;
|
||||
struct mbuf *m0;
|
||||
@ -1169,7 +1168,7 @@ t3_encap(struct port_info *p, struct mbuf **m)
|
||||
struct tx_sw_desc *stx;
|
||||
struct txq_state txqs;
|
||||
unsigned int ndesc, flits, cntrl, mlen;
|
||||
int err, nsegs, tso_info = 0, qsidx = 0;
|
||||
int err, nsegs, tso_info = 0;
|
||||
|
||||
struct work_request_hdr *wrp;
|
||||
struct tx_sw_desc *txsd;
|
||||
@ -1182,12 +1181,12 @@ t3_encap(struct port_info *p, struct mbuf **m)
|
||||
|
||||
m0 = *m;
|
||||
sc = p->adapter;
|
||||
if (sc->params.nports <= 2)
|
||||
qsidx = p->first_qset;
|
||||
|
||||
DPRINTF("t3_encap qsidx=%d", qsidx);
|
||||
DPRINTF("t3_encap port_id=%d qsidx=%d ", p->port_id, p->first_qset);
|
||||
|
||||
qs = &sc->sge.qs[qsidx];
|
||||
/* port_id=1 qsid=1 txpkt_intf=2 tx_chan=0 */
|
||||
|
||||
qs = &sc->sge.qs[p->first_qset];
|
||||
|
||||
txq = &qs->txq[TXQ_ETH];
|
||||
stx = &txq->sdesc[txq->pidx];
|
||||
@ -1196,7 +1195,7 @@ t3_encap(struct port_info *p, struct mbuf **m)
|
||||
mlen = m0->m_pkthdr.len;
|
||||
cpl->len = htonl(mlen | 0x80000000);
|
||||
|
||||
DPRINTF("mlen=%d pktintf=%d\n", mlen, p->txpkt_intf);
|
||||
DPRINTF("mlen=%d txpkt_intf=%d tx_chan=%d\n", mlen, p->txpkt_intf, p->tx_chan);
|
||||
/*
|
||||
* XXX handle checksum, TSO, and VLAN here
|
||||
*
|
||||
@ -1259,7 +1258,7 @@ t3_encap(struct port_info *p, struct mbuf **m)
|
||||
else
|
||||
m_copydata(m0, 0, mlen, (caddr_t)&txd->flit[2]);
|
||||
|
||||
m_freem(m0);
|
||||
*free = 1;
|
||||
flits = (mlen + 7) / 8 + 2;
|
||||
cpl->wr.wr_hi = htonl(V_WR_BCNTLFLT(mlen & 7) |
|
||||
V_WR_OP(FW_WROPCODE_TUNNEL_TX_PKT) |
|
||||
@ -2541,7 +2540,7 @@ t3b_intr(void *data)
|
||||
|
||||
if (__predict_false(map & F_ERRINTR))
|
||||
taskqueue_enqueue(adap->tq, &adap->slow_intr_task);
|
||||
|
||||
|
||||
mtx_lock(&q0->lock);
|
||||
for_each_port(adap, i)
|
||||
if (map & (1 << i))
|
||||
@ -2561,7 +2560,7 @@ t3_intr_msi(void *data)
|
||||
adapter_t *adap = data;
|
||||
struct sge_rspq *q0 = &adap->sge.qs[0].rspq;
|
||||
int i, new_packets = 0;
|
||||
|
||||
|
||||
mtx_lock(&q0->lock);
|
||||
|
||||
for_each_port(adap, i)
|
||||
|
||||
@ -1,442 +0,0 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
$FreeBSD$
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
begin 644 t3fw-4.5.0.bin.gz
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||||
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|
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||||
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|
||||
*%P!M0DW?O%L`````
|
||||
`
|
||||
end
|
||||
451
sys/dev/cxgb/t3fw-4.7.0.bin.gz.uu
Normal file
451
sys/dev/cxgb/t3fw-4.7.0.bin.gz.uu
Normal file
@ -0,0 +1,451 @@
|
||||
/**************************************************************************
|
||||
|
||||
Copyright (c) 2007, Chelsio Inc.
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice,
|
||||
this list of conditions and the following disclaimer.
|
||||
|
||||
2. Neither the name of the Chelsio Corporation nor the names of its
|
||||
contributors may be used to endorse or promote products derived from
|
||||
this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
$FreeBSD$
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
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M#+3#H7F<SO-,"UB/?_LW(A@!W:W@'#V&'3,L"S@6O`35,B>L^].3;>+NK9A<
|
||||
MN,LF2\^`##:D^Z.E,R;%S40TZ5FQ[S(H+GO')S8]$T:6OCU;DYZ)1#.0\Z$7
|
||||
MW#^ZL02Z)CM=DYW!\50F9D.ZMAZE-BTVI?.I&4Z[Z%CZ=C1,#]]W+(0ID)Y0
|
||||
MC*1K-J03]2B_GZ;9E,ZB*DNMK'K]%<95738>V/T:P4&(6/3Y*I#/OWV#?"NT
|
||||
M^U7.ZQQY[=:3WRU=3SO'5VY_88?.G6P+Z1X5UOTR1@AW'EF7E94)',Q9F%FW
|
||||
M/-M0N*YASL;,)7?H6=D;,U/?_BPKNT$#(6%CYL8LV"+8FO_8#LCWL1%#KR0;
|
||||
MTND2FL3SG-HD11#XO$%*-6T\PYM0XLG]1RHX5A<<J3,N>),/?=O9+0OKEH1W
|
||||
M2X*Z)=2WG=V2D&[._\JWG8R0[G<PA7#7KISB$YG+\U:$=4_;O4?>G*%JSF2W
|
||||
M0O_[8\4&1'E,1VV?O<]5<E0'MH9TLU(`,Z+[KYW\U:=?WR7WGN5(63]\X79Z
|
||||
MI^-,5<H&P<G]BD-;X8Q+(O=U>$A)0/=$^E9:_K`(UTTL7\1KI:D.;?7\*P-#
|
||||
M2/O]<T?3VZZK.M`>XKIX!2=TB$3'9$WQ]WX\WH7#<0MS=6"O>PZ89++E7/GV
|
||||
MS*'O7,>'N,Z(76<QF7!G<NS<[%T$865MG4,=L$@(]4G`S/K7)',S`UU7H+]Z
|
||||
M6F*+#G8ULS)%S`3:DJD^IU[V?N".L#B3([N#BW#0S.=/W/5,==[!)CF:QU+E
|
||||
MW$R`<^NXBN3,?Z^GV+7W"A[KK6?BBTKF#&/_TV!VO,,^/3-EEBS"]24V71CE
|
||||
M^@I9SP!I$,@U#]&]K=`P:?Z!*ILSN4JNLH42_##<58%-$T:Z=A\I8[$FJZ^A
|
||||
ML/I[&A$RE.(T-U'%@4R.@JLX1#49]D/Q?^X'L2LGR&7#XH3;93(C:^>B6$DV
|
||||
M\B$#=D5"Z)+Q+(DD$_8`Q?6]?CUPSH^!"EQKQBNS!`&N%4&NRT"__6ME[3YN
|
||||
MR/B4DO"4#<*4]4R0R\Z*-R*B6([9B/@AL7_IHSX31-9^-SK0]8-R'$U16Z=R
|
||||
MULN=3@[GKXH]/[/L0CCOEMAC5,X#:N=!5JN0UXJN."TZ,D*I0.H3%DVM-"(:
|
||||
M*,1$-B/(P@^X/@4BS3A:;&^]NM>Y<#^74R0BH,S,@]K,`U?T2<^FF4@*$;W[
|
||||
MEU\$NISH5!'*FLBW">5O"JD1'AEZL@A)#97.]&>ETN&8^B:@TC?]O>W3`2<P
|
||||
MKA.$NQ("71-$KH23@]5"(S(!5KZ:7Y\,W5E+]2-@Y.Q"U^[XZ8K1)P6.H0HX
|
||||
MX1C"3NMP@/4G]R/V4(Z=+@^B_3#"C+_?B2MQYD5CN$M7((2,?O7.-[UYKAAA
|
||||
MG@Z'^=4KN<,XN2)&'<V,<_*BN7DB1B-MQ=%Q+L?\&D:!@;<7NZICKD)#74D^
|
||||
MRSB<*T2$:RV1/I97QX+9+5I')PZ<X:X0$^FH3T:,#`X;1F<C2)=S?CTCWX`=
|
||||
MPR)<?XUT+>)]3^QS1;H^5]]*,Y%;*;[LXH:XN.&N>6&N^<`*/C=Z_FDIR396
|
||||
M?9U\BX!;"A7`+-N0O;PY".#SY]ZB#IA+*`!>$KHTZ9*)[(>(E,4S">FQ(O,'
|
||||
M9R\8Z.J)\R[3R_`&2:?5-T$T;ZJD!"^)+HDID93$EDA+XDID)?(2HD19HBA1
|
||||
MEZA*M"4:B4IO(M<C2&37W;A;UKA;:=[Y*./0_+MZ0UP315V/`UQ38H:K%7I$
|
||||
MOF'?_*W4UCJQ9Y#-TZM"FY4<->_L:.4D@]F:DT2^$^AZ)=0U4OF7/LY?:(FT
|
||||
M5.5X`Z>1Z'0HWT02:=EY\(:EH`XC9(E<+ZNC4=5?^K"QA*^+VN+<HD^DK<[3
|
||||
MUS6"&A@1N33@>KA+`Q/!%'XO4BRA4B@X:")ML2(:!0W4)Z/4%[KP@176^WBK
|
||||
M:I+!1"X!-T-<>*`+CW)%1[BBP[OZPURX#9<UK)`UK)$UI&,V0M:0S6+Y[BW8
|
||||
M7_1EUBZ;)G./+'.W;/8]S>S[LD=*S2.5YOQGLO.?FD@%U1?''>!@$OG&\1IP
|
||||
MT+^+/*Z7RH+`ZU)9<!+Y.A@K[MIW?+U<%D18B1A9L-E:I.`,5W)H2>3$X[6>
|
||||
MZ_CCM:!>(0MJWA]#91G7E"[GU)P\"$XU=S23H%\K"XKJVJ>1!:ME0<<OJ&3!
|
||||
M3<>E,J%"XL^MHWD:J)#Y0W^#4TN5(0M6RH0:B3_%YV3^,(>*$DF(N^Z"S<V[
|
||||
MF[Y2<6I5LB"E+!B6)Y<%$S+!.3XL'M8^RD3.I]H2WE47UK51W-4=W-43U-43
|
||||
MV-4#W."\J&M[5-?'$@Y+^S,R3S'B"K@,5B6A_--8>%<UMH78>7Q[LV*D51&;
|
||||
MN:UY1ZM:FJ^4YFJD>?6-FI'5JI%5JI&5]7O"NZQA7=]#$?^6O^B/_$HJ?WVC
|
||||
M1P+,KH!"_L@/EH=TK0WK^BZ@ZYO0KF_$7=^*NJQ!7=\R'A'^7=\PDC&&CV_M
|
||||
MS)V)=>]LG56ADW^)Q&7F0BKWI2(S7YZ9%]QU2-SUU8ZW9",C9",C-2.C@KH.
|
||||
M!G0=W#Z',0(C9*<T2Q#U[#V:V;LUL^MB9+=B9#<ULMO>/;+@KKR`KF+IHG&2
|
||||
MX25KM=QY+!\"1HI0$_D+.`&<D5TCJ:]AV!^/EO<2\Q-H%YS`$-)5+.YZIU00
|
||||
MT14NZT6/$SU.7^UH;2\MJ"L_JFNY8M&D@O;@KNQ*8417ZKQ=D\X;#LY9D23J
|
||||
M-OAW35_R*:-0Z/<^AEXG]DLD%])^U`=T35[\*2/K_VGC;$.B",(XOCN[9WG>
|
||||
MY=QYB)QAXYY;ZKWLW%V<==&+YE46E:"]P$%OUZD'ZD*7*'V07(.*(CHU"*07
|
||||
M*DR+P/LLP0E)"D61%<'.ETBI_!`JH1#F-7MY*1@L[+/[W_DQL\/N\W\^S)AT
|
||||
M`0-74QP/].\8\#SV"KX[@N]N$7UCOGOVB6N.B>L64C^>751Q,(%YBV7T0-/:
|
||||
MC+A7B\I#R=D7U7GD%./FK20K$>]^R`Q9!X=Z'Y4H!VW*H6*E9GC?A<L%^F?`
|
||||
M\9ZY`>6)DV;"ZG8:)-%05&B41'V12+-*'JFZ<C%QIOTRV?B(N0JYC,,)M]R3
|
||||
M3^YGY%MHJ1#8JALRV$?H8;2/Z.TC6AXB]^EM*J]2"M3O_':#<](@?38Z)_72
|
||||
M9%8Z[^:I\SE$LA)WHEKLZQ?[!L2^)V+?TQ)/P**.95XQW-X53/::B=,E?%FO
|
||||
M?EIWPG+WI5.8U-8#C=J%UUE!2^\8_0R#R?SAP0TDU_&+VN%MI>5`\OF7_@,!
|
||||
M<)QI#RZ^#2X.B!N=P<7FI9QO)AX%`>78:&$HN6`F+NX;YG]@71QWHY["6T)J
|
||||
MRUI(2F-,%]L->C@3,2J0G<(/3.RT6W/RN=3?F8A-@;;]#">`+FA2YQ.%79!Z
|
||||
M\$M<)U#8#H9YAUF;MC\<)-9_''4AS9E9P3$I,$=]GN*L!(QCUIMJGQ5C.M@P
|
||||
MK.H`85C9P;W9D*9]3]-FEVGJ[__0$C#&Q4!,H[['[&[ZU/Q-&$K.0W5NN6\_
|
||||
M%:@-9+`3+@UIQJP.=\%E\E>-/+"JGQ\P6Y.:3]#LD3XBG<SS._GSP5)JUC0/
|
||||
M[+4*>J:IRA@-\5R=(2YD"R8NQQ(-`<%!C?JH7YL0JJ6J[;]>!H`IG#J_$KEI
|
||||
M6C5D,[*@XV9HI)-M.FY6\]U+.IA.^5)9X,$,C60;#V9QNG8`0*LE],SNAG!C
|
||||
M-"*C/<=09:#BR-[M&!57M$0:SZ/:EC`J;ZE'GBW([?5[R_P>+ZJNK$4>C,N0
|
||||
MW(SJPHV1-M?I:"1T-AR-U#>'ST5=(;G)+S7(36$II4JM4EWKR<TN7XD#':5Z
|
||||
FA#:K];:U(8PWNW"9"V/D1&YZ@<LPAOP:IG]3YMP?6%ULKS1=````
|
||||
`
|
||||
end
|
||||
@ -11,16 +11,18 @@ SRCS+= device_if.h bus_if.h pci_if.h opt_zero.h
|
||||
SRCS+= uipc_mvec.c
|
||||
|
||||
CFLAGS+= -DCONFIG_CHELSIO_T3_CORE -g -DCONFIG_DEFINED -DDEFAULT_JUMBO -I${CXGB}
|
||||
#CFLAGS+= -DINVARIANT_SUPPORT -DINVARIANTS
|
||||
#CFLAGS+= -DDEBUG -DDEBUG_PRINT
|
||||
#CFLAGS+= -DINVARIANT_SUPPORT -DINVARIANTS -DWITNESS
|
||||
|
||||
|
||||
.if ${MACHINE_ARCH} != "ia64"
|
||||
# ld is broken on ia64
|
||||
t3fw-4.5.0.bin: ${CXGB}/t3fw-4.5.0.bin.gz.uu
|
||||
uudecode -p < ${CXGB}/t3fw-4.5.0.bin.gz.uu \
|
||||
t3fw-4.7.0.bin: ${CXGB}/t3fw-4.7.0.bin.gz.uu
|
||||
uudecode -p < ${CXGB}/t3fw-4.7.0.bin.gz.uu \
|
||||
| gzip -dc > ${.TARGET}
|
||||
|
||||
FIRMWS= t3fw-4.5.0.bin:t3fw450
|
||||
CLEANFILES+= t3fw-4.5.0.bin
|
||||
FIRMWS= t3fw-4.7.0.bin:t3fw470
|
||||
CLEANFILES+= t3fw-4.7.0.bin
|
||||
|
||||
t3b_protocol_sram-1.1.0.bin: ${CXGB}/t3b_protocol_sram-1.1.0.bin.gz.uu
|
||||
uudecode -p < ${CXGB}/t3b_protocol_sram-1.1.0.bin.gz.uu \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user