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Implement pmap_sync_icache().

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This invokes "fence" on the hart performing the write followed by an IPI
to execute "fence.i" on all harts.

This is required to support userland debuggers setting breakpoints in
user processes.

Reviewed by:	br (earlier version), markj
Approved by:	re (gjb)
Sponsored by:	DARPA
Differential Revision:	https://reviews.freebsd.org/D17139
This commit is contained in:
John Baldwin 2018-09-24 17:41:29 +00:00
parent cf4a52cf67
commit 7a102e0463
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=338914
1 changed files with 17 additions and 1 deletions
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18
sys/riscv/riscv/pmap.c
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@ -3244,11 +3244,27 @@ pmap_activate(struct thread *td)
critical_exit();
}
static void
pmap_sync_icache_one(void *arg __unused)
{
__asm __volatile("fence.i");
}
void
pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
{
panic("RISCVTODO: pmap_sync_icache");
/*
* From the RISC-V User-Level ISA V2.2:
*
* "To make a store to instruction memory visible to all
* RISC-V harts, the writing hart has to execute a data FENCE
* before requesting that all remote RISC-V harts execute a
* FENCE.I."
*/
__asm __volatile("fence");
smp_rendezvous(NULL, pmap_sync_icache_one, NULL, NULL);
}
/*