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ok we now get so that the uart init's and we can print. We

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cannot set baud rate as they did in 6.4, this hoses things and
we loose our 38400 default term.

We now lock somewhere in tcinit.
This commit is contained in:
Randall Stewart 2009-11-05 18:14:25 +00:00
parent d6994d3b0e
commit 7a7f91f61b
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/projects/mips/; revision=198956
13 changed files with 941 additions and 143 deletions
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795
sys/mips/rmi/bus_space_rmi.c Normal file
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@ -0,0 +1,795 @@
/*-
* Copyright (c) 2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/malloc.h>
#include <sys/ktr.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_kern.h>
#include <vm/vm_extern.h>
#include <machine/bus.h>
#include <machine/cache.h>
void xlr_putc(char);
void xlr_print_int(uint32_t);
static int rmi_bus_space_map(void *t, bus_addr_t addr,
bus_size_t size, int flags,
bus_space_handle_t *bshp);
static void rmi_bus_space_unmap(void *t, bus_space_handle_t bsh,
bus_size_t size);
static int rmi_bus_space_subregion(void *t,
bus_space_handle_t bsh,
bus_size_t offset, bus_size_t size,
bus_space_handle_t *nbshp);
static u_int8_t rmi_bus_space_read_1(void *t,
bus_space_handle_t handle,
bus_size_t offset);
static u_int16_t rmi_bus_space_read_2(void *t,
bus_space_handle_t handle,
bus_size_t offset);
static u_int32_t rmi_bus_space_read_4(void *t,
bus_space_handle_t handle,
bus_size_t offset);
static void rmi_bus_space_read_multi_1(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int8_t *addr,
size_t count);
static void rmi_bus_space_read_multi_2(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int16_t *addr,
size_t count);
static void rmi_bus_space_read_multi_4(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int32_t *addr,
size_t count);
static void rmi_bus_space_read_region_1(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int8_t *addr,
size_t count);
static void rmi_bus_space_read_region_2(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int16_t *addr,
size_t count);
static void rmi_bus_space_read_region_4(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int32_t *addr,
size_t count);
static void rmi_bus_space_write_1(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int8_t value);
static void rmi_bus_space_write_2(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int16_t value);
static void rmi_bus_space_write_4(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int32_t value);
static void rmi_bus_space_write_multi_1(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int8_t *addr,
size_t count);
static void rmi_bus_space_write_multi_2(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int16_t *addr,
size_t count);
static void rmi_bus_space_write_multi_4(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int32_t *addr,
size_t count);
static void rmi_bus_space_write_region_2(void *t,
bus_space_handle_t bsh,
bus_size_t offset,
const u_int16_t *addr,
size_t count);
static void rmi_bus_space_write_region_4(void *t,
bus_space_handle_t bsh,
bus_size_t offset,
const u_int32_t *addr,
size_t count);
static void rmi_bus_space_set_region_2(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int16_t value,
size_t count);
static void rmi_bus_space_set_region_4(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int32_t value,
size_t count);
static void rmi_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
bus_size_t offset __unused, bus_size_t len __unused, int flags);
static void rmi_bus_space_copy_region_2(void *t,
bus_space_handle_t bsh1,
bus_size_t off1,
bus_space_handle_t bsh2,
bus_size_t off2, size_t count);
u_int8_t rmi_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
bus_size_t offset);
static u_int16_t rmi_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
bus_size_t offset);
static u_int32_t rmi_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
bus_size_t offset);
static void rmi_bus_space_read_multi_stream_1(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int8_t *addr,
size_t count);
static void rmi_bus_space_read_multi_stream_2(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int16_t *addr,
size_t count);
static void rmi_bus_space_read_multi_stream_4(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int32_t *addr,
size_t count);
void rmi_bus_space_write_stream_1(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t value);
static void rmi_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int16_t value);
static void rmi_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int32_t value);
static void rmi_bus_space_write_multi_stream_1(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int8_t *addr,
size_t count);
static void rmi_bus_space_write_multi_stream_2(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int16_t *addr,
size_t count);
static void rmi_bus_space_write_multi_stream_4(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int32_t *addr,
size_t count);
static struct bus_space local_rmi_bus_space = {
/* cookie */
(void *) 0,
/* mapping/unmapping */
rmi_bus_space_map,
rmi_bus_space_unmap,
rmi_bus_space_subregion,
/* allocation/deallocation */
NULL,
NULL,
/* barrier */
rmi_bus_space_barrier,
/* read (single) */
rmi_bus_space_read_1,
rmi_bus_space_read_2,
rmi_bus_space_read_4,
NULL,
/* read multiple */
rmi_bus_space_read_multi_1,
rmi_bus_space_read_multi_2,
rmi_bus_space_read_multi_4,
NULL,
/* read region */
rmi_bus_space_read_region_1,
rmi_bus_space_read_region_2,
rmi_bus_space_read_region_4,
NULL,
/* write (single) */
rmi_bus_space_write_1,
rmi_bus_space_write_2,
rmi_bus_space_write_4,
NULL,
/* write multiple */
rmi_bus_space_write_multi_1,
rmi_bus_space_write_multi_2,
rmi_bus_space_write_multi_4,
NULL,
/* write region */
NULL,
rmi_bus_space_write_region_2,
rmi_bus_space_write_region_4,
NULL,
/* set multiple */
NULL,
NULL,
NULL,
NULL,
/* set region */
NULL,
rmi_bus_space_set_region_2,
rmi_bus_space_set_region_4,
NULL,
/* copy */
NULL,
rmi_bus_space_copy_region_2,
NULL,
NULL,
/* read (single) stream */
rmi_bus_space_read_stream_1,
rmi_bus_space_read_stream_2,
rmi_bus_space_read_stream_4,
NULL,
/* read multiple stream */
rmi_bus_space_read_multi_stream_1,
rmi_bus_space_read_multi_stream_2,
rmi_bus_space_read_multi_stream_4,
NULL,
/* read region stream */
rmi_bus_space_read_region_1,
rmi_bus_space_read_region_2,
rmi_bus_space_read_region_4,
NULL,
/* write (single) stream */
rmi_bus_space_write_stream_1,
rmi_bus_space_write_stream_2,
rmi_bus_space_write_stream_4,
NULL,
/* write multiple stream */
rmi_bus_space_write_multi_stream_1,
rmi_bus_space_write_multi_stream_2,
rmi_bus_space_write_multi_stream_4,
NULL,
/* write region stream */
NULL,
rmi_bus_space_write_region_2,
rmi_bus_space_write_region_4,
NULL,
};
/* generic bus_space tag */
bus_space_tag_t rmi_bus_space = &local_rmi_bus_space;
#define MIPS_BUS_SPACE_IO 0 /* space is i/o space */
#define MIPS_BUS_SPACE_MEM 1 /* space is mem space */
#define MIPS_BUS_SPACE_PCI 10 /* avoid conflict with other spaces */
#define BUS_SPACE_UNRESTRICTED (~0)
#define SWAP32(x)\
(((x) & 0xff000000) >> 24) | \
(((x) & 0x000000ff) << 24) | \
(((x) & 0x0000ff00) << 8) | \
(((x) & 0x00ff0000) >> 8)
#define SWAP16(x)\
(((x) & 0xff00) >> 8) | \
(((x) & 0x00ff) << 8)
/*
* Map a region of device bus space into CPU virtual address space.
*/
static int
rmi_bus_space_map(void *t __unused, bus_addr_t addr,
bus_size_t size __unused, int flags __unused,
bus_space_handle_t *bshp)
{
*bshp = addr;
return (0);
}
/*
* Unmap a region of device bus space.
*/
static void
rmi_bus_space_unmap(void *t __unused, bus_space_handle_t bsh __unused,
bus_size_t size __unused)
{
}
/*
* Get a new handle for a subregion of an already-mapped area of bus space.
*/
static int
rmi_bus_space_subregion(void *t __unused, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t size __unused,
bus_space_handle_t *nbshp)
{
*nbshp = bsh + offset;
return (0);
}
/*
* Read a 1, 2, 4, or 8 byte quantity from bus space
* described by tag/handle/offset.
*/
static u_int8_t
rmi_bus_space_read_1(void *tag, bus_space_handle_t handle,
bus_size_t offset)
{
if ((int)tag == MIPS_BUS_SPACE_PCI)
return (u_int8_t)(*(volatile u_int8_t *)(handle + offset));
else
return (u_int8_t)(*(volatile u_int32_t *)(handle + offset));
}
static u_int16_t
rmi_bus_space_read_2(void *tag, bus_space_handle_t handle,
bus_size_t offset)
{
if ((int)tag == MIPS_BUS_SPACE_PCI)
return SWAP16((u_int16_t)(*(volatile u_int16_t *)(handle + offset)));
else
return *(volatile u_int16_t *)(handle + offset);
}
static u_int32_t
rmi_bus_space_read_4(void *tag, bus_space_handle_t handle,
bus_size_t offset)
{
if ((int)tag == MIPS_BUS_SPACE_PCI)
return SWAP32((*(volatile u_int32_t *)(handle + offset)));
else
return (*(volatile u_int32_t *)(handle + offset));
}
/*
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
* described by tag/handle/offset and copy into buffer provided.
*/
static void
rmi_bus_space_read_multi_1(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int8_t *addr, size_t count)
{
if ((int)tag != MIPS_BUS_SPACE_PCI)
return;
while (count--) {
*addr = (*(volatile u_int8_t *)(handle + offset));
addr++;
}
}
static void
rmi_bus_space_read_multi_2(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int16_t *addr, size_t count)
{
if ((int)tag != MIPS_BUS_SPACE_PCI)
return;
while (count--) {
*addr = *(volatile u_int16_t *)(handle + offset);
*addr = SWAP16(*addr);
addr++;
}
}
static void
rmi_bus_space_read_multi_4(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int32_t *addr, size_t count)
{
if ((int)tag != MIPS_BUS_SPACE_PCI)
return;
while (count--) {
*addr = *(volatile u_int32_t *)(handle + offset);
*addr = SWAP32(*addr);
addr++;
}
}
/*
* Write the 1, 2, 4, or 8 byte value `value' to bus space
* described by tag/handle/offset.
*/
static void
rmi_bus_space_write_1(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int8_t value)
{
mips_sync();
if ((int)tag == MIPS_BUS_SPACE_PCI)
*(volatile u_int8_t *)(handle + offset) = value;
else
*(volatile u_int32_t *)(handle + offset) = (u_int32_t)value;
}
static void
rmi_bus_space_write_2(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int16_t value)
{
mips_sync();
if ((int)tag == MIPS_BUS_SPACE_PCI) {
*(volatile u_int16_t *)(handle + offset) = SWAP16(value);
} else
*(volatile u_int16_t *)(handle + offset) = value;
}
static void
rmi_bus_space_write_4(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int32_t value)
{
mips_sync();
if ((int)tag == MIPS_BUS_SPACE_PCI) {
*(volatile u_int32_t *)(handle + offset) = SWAP32(value);
} else
*(volatile u_int32_t *)(handle + offset) = value;
}
/*
* Write `count' 1, 2, 4, or 8 byte quantities from the buffer
* provided to bus space described by tag/handle/offset.
*/
static void
rmi_bus_space_write_multi_1(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int8_t *addr, size_t count)
{
mips_sync();
if ((int)tag != MIPS_BUS_SPACE_PCI)
return;
while (count--) {
(*(volatile u_int8_t *)(handle + offset)) = *addr;
addr++;
}
}
static void
rmi_bus_space_write_multi_2(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int16_t *addr, size_t count)
{
mips_sync();
if ((int)tag != MIPS_BUS_SPACE_PCI)
return;
while (count--) {
(*(volatile u_int16_t *)(handle + offset)) = SWAP16(*addr);
addr++;
}
}
static void
rmi_bus_space_write_multi_4(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int32_t *addr, size_t count)
{
mips_sync();
if ((int)tag != MIPS_BUS_SPACE_PCI)
return;
while (count--) {
(*(volatile u_int32_t *)(handle + offset)) = SWAP32(*addr);
addr++;
}
}
/*
* Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
* by tag/handle starting at `offset'.
*/
static void
rmi_bus_space_set_region_2(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t value, size_t count)
{
bus_addr_t addr = bsh + offset;
for (; count != 0; count--, addr += 2)
(*(volatile u_int16_t *)(addr)) = value;
}
static void
rmi_bus_space_set_region_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int32_t value, size_t count)
{
bus_addr_t addr = bsh + offset;
for (; count != 0; count--, addr += 4)
(*(volatile u_int32_t *)(addr)) = value;
}
/*
* Copy `count' 1, 2, 4, or 8 byte values from bus space starting
* at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
*/
static void
rmi_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1,
bus_size_t off1, bus_space_handle_t bsh2,
bus_size_t off2, size_t count)
{
printf("bus_space_copy_region_2 - unimplemented\n");
}
/*
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
* described by tag/handle/offset and copy into buffer provided.
*/
u_int8_t
rmi_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
bus_size_t offset)
{
return *((volatile u_int8_t *)(handle + offset));
}
static u_int16_t
rmi_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
bus_size_t offset)
{
return *(volatile u_int16_t *)(handle + offset);
}
static u_int32_t
rmi_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
bus_size_t offset)
{
return (*(volatile u_int32_t *)(handle + offset));
}
static void
rmi_bus_space_read_multi_stream_1(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int8_t *addr, size_t count)
{
if ((int)tag != MIPS_BUS_SPACE_PCI)
return;
while (count--) {
*addr = (*(volatile u_int8_t *)(handle + offset));
addr++;
}
}
static void
rmi_bus_space_read_multi_stream_2(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int16_t *addr, size_t count)
{
if ((int)tag != MIPS_BUS_SPACE_PCI)
return;
while (count--) {
*addr = (*(volatile u_int16_t *)(handle + offset));
addr++;
}
}
static void
rmi_bus_space_read_multi_stream_4(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int32_t *addr, size_t count)
{
if ((int)tag != MIPS_BUS_SPACE_PCI)
return;
while (count--) {
*addr = (*(volatile u_int32_t *)(handle + offset));
addr++;
}
}
/*
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
* described by tag/handle and starting at `offset' and copy into
* buffer provided.
*/
void
rmi_bus_space_read_region_1(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t *addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--) {
*addr++ = (*(volatile u_int8_t *)(baddr));
baddr += 1;
}
}
void
rmi_bus_space_read_region_2(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t *addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--) {
*addr++ = (*(volatile u_int16_t *)(baddr));
baddr += 2;
}
}
void
rmi_bus_space_read_region_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int32_t *addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--) {
*addr++ = (*(volatile u_int32_t *)(baddr));
baddr += 4;
}
}
void
rmi_bus_space_write_stream_1(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int8_t value)
{
mips_sync();
*(volatile u_int8_t *)(handle + offset) = value;
}
static void
rmi_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int16_t value)
{
mips_sync();
*(volatile u_int16_t *)(handle + offset) = value;
}
static void
rmi_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int32_t value)
{
mips_sync();
*(volatile u_int32_t *)(handle + offset) = value;
}
static void
rmi_bus_space_write_multi_stream_1(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int8_t *addr, size_t count)
{
mips_sync();
if ((int)tag != MIPS_BUS_SPACE_PCI)
return;
while (count--) {
(*(volatile u_int8_t *)(handle + offset)) = *addr;
addr++;
}
}
static void
rmi_bus_space_write_multi_stream_2(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int16_t *addr, size_t count)
{
mips_sync();
if ((int)tag != MIPS_BUS_SPACE_PCI)
return;
while (count--) {
(*(volatile u_int16_t *)(handle + offset)) = *addr;
addr++;
}
}
static void
rmi_bus_space_write_multi_stream_4(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int32_t *addr, size_t count)
{
mips_sync();
if ((int)tag != MIPS_BUS_SPACE_PCI)
return;
while (count--) {
(*(volatile u_int32_t *)(handle + offset)) = *addr;
addr++;
}
}
void
rmi_bus_space_write_region_2(void *t,
bus_space_handle_t bsh,
bus_size_t offset,
const u_int16_t *addr,
size_t count)
{
bus_addr_t baddr = (bus_addr_t)bsh + offset;
while (count--) {
(*(volatile u_int16_t *)(baddr)) = *addr;
addr++;
baddr += 2;
}
}
void
rmi_bus_space_write_region_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, const u_int32_t *addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--) {
(*(volatile u_int32_t *)(baddr)) = *addr;
addr++;
baddr += 4;
}
}
static void
rmi_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
bus_size_t offset __unused, bus_size_t len __unused, int flags)
{
}

24
sys/mips/rmi/clock.c
View File

@ -162,6 +162,24 @@ pic_timecounthandler(struct trapframe *tf)
return (FILTER_HANDLED);
}
void
rmi_early_counter_init()
{
int cpu = PCPU_GET(cpuid);
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
/* We do this to get the PIC time counter running right
* after system start. Otherwise the DELAY() function will
* not be able to work since it won't have a TC to read.
*/
xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_0, (0xffffffff & 0xffffffff));
xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_1, (0xffffffff & 0xffffffff));
xlr_write_reg(mmio, PIC_IRT_0_TIMER_6, (1 << cpu));
xlr_write_reg(mmio, PIC_IRT_1_TIMER_6, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_6_IRQ));
pic_update_control(1 << (8 + 6));
}
void
platform_initclocks(void)
{
@ -204,7 +222,8 @@ platform_initclocks(void)
/* Setup PIC Interrupt */
mtx_lock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe)
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_0, (maxval & 0xffffffff)); /* 0x100 + 7 */
xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_1, (maxval >> 32) & 0xffffffff); /* 0x110 + 7 */
/* 0x40 + 8 */
@ -221,7 +240,8 @@ platform_initclocks(void)
xlr_write_reg(mmio, PIC_IRT_0_TIMER_6, (1 << cpu));
xlr_write_reg(mmio, PIC_IRT_1_TIMER_6, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_6_IRQ));
pic_update_control(1 << (8 + 6));
mtx_unlock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe)
mtx_unlock_spin(&xlr_pic_lock);
} else {
/* Setup count-compare interrupt for vcpu[1-31] */
mips_wr_compare((xlr_boot1_info.cpu_frequency) / hz);

2
sys/mips/rmi/clock.h
View File

@ -36,5 +36,5 @@
void count_compare_clockhandler(struct trapframe *);
void pic_hardclockhandler(struct trapframe *);
int pic_timecounthandler(struct trapframe *);
void rmi_early_counter_init(void);
#endif /* _RMI_CLOCK_H_ */

1
sys/mips/rmi/files.xlr
View File

@ -18,6 +18,7 @@ mips/rmi/pcibus.c optional pci
mips/rmi/xlr_pci.c optional pci
#mips/rmi/xls_ehci.c optional usb ehci
dev/rmi/xlr/rge.c optional rge
mips/rmi/bus_space_rmi.c standard
dev/iicbus/xlr_rtc.c optional xlr_rtc
dev/iicbus/xlr_temperature.c optional xlr_temperature
dev/iicbus/xlr_eeprom.c optional xlr_eeprom

15
sys/mips/rmi/iodi.c
View File

@ -99,6 +99,7 @@ static void pic_usb_ack(void *arg)
}
*/
static int
iodi_setup_intr(device_t dev, device_t child,
struct resource *ires, int flags, driver_filter_t * filt, driver_intr_t * intr, void *arg,
@ -111,11 +112,13 @@ iodi_setup_intr(device_t dev, device_t child,
/* FIXME is this the right place to fiddle with PIC? */
if (strcmp(device_get_name(child), "uart") == 0) {
/* FIXME uart 1? */
mtx_lock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe)
mtx_lock_spin(&xlr_pic_lock);
level = PIC_IRQ_IS_EDGE_TRIGGERED(PIC_IRT_UART_0_INDEX);
xlr_write_reg(mmio, PIC_IRT_0_UART_0, 0x01);
xlr_write_reg(mmio, PIC_IRT_1_UART_0, ((1 << 31) | (level << 30) | (1 << 6) | (PIC_UART_0_IRQ)));
mtx_unlock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe)
mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr("uart", NULL,
(driver_intr_t *) intr, (void *)arg, PIC_UART_0_IRQ, flags, cookiep);
@ -123,16 +126,20 @@ iodi_setup_intr(device_t dev, device_t child,
int irq;
irq = rman_get_rid(ires);
mtx_lock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe)
mtx_lock_spin(&xlr_pic_lock);
reg = xlr_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
xlr_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, reg | (1 << 6) | (1 << 30) | (1 << 31));
mtx_unlock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe)
mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr("rge", NULL, (driver_intr_t *) intr, (void *)arg, irq, flags, cookiep);
} else if (strcmp(device_get_name(child), "ehci") == 0) {
if (rmi_spin_mutex_safe)
mtx_lock_spin(&xlr_pic_lock);
reg = xlr_read_reg(mmio, PIC_IRT_1_BASE + PIC_USB_IRQ - PIC_IRQ_BASE);
xlr_write_reg(mmio, PIC_IRT_1_BASE + PIC_USB_IRQ - PIC_IRQ_BASE, reg | (1 << 6) | (1 << 30) | (1 << 31));
if (rmi_spin_mutex_safe)
mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr("ehci", NULL, (driver_intr_t *) intr, (void *)arg, PIC_USB_IRQ, flags, cookiep);
}

5
sys/mips/rmi/iomap.h
View File

@ -31,7 +31,7 @@
#define _RMI_IOMAP_H_
#include <machine/endian.h>
#define XLR_DEVICE_REGISTER_BASE 0x1EF00000
#define DEFAULT_XLR_IO_BASE 0xffffffffbef00000ULL
#define XLR_IO_SIZE 0x1000
@ -65,6 +65,9 @@
#define XLR_IO_UART_0_OFFSET 0x14000
#define XLR_IO_UART_1_OFFSET 0x15000
#define XLR_UART0ADDR (XLR_IO_UART_0_OFFSET+XLR_DEVICE_REGISTER_BASE)
#define XLR_IO_I2C_0_OFFSET 0x16000
#define XLR_IO_I2C_1_OFFSET 0x17000

5
sys/mips/rmi/msgring.h
View File

@ -469,14 +469,15 @@ extern struct stn_cc xls_cc_table_pcie;
extern struct stn_cc xls_cc_table_dma;
extern struct stn_cc xls_cc_table_sec;
#define msgrng_access_save(lock, mflags) do { \
mtx_lock_spin(lock); \
if (rmi_spin_mutex_safe) mtx_lock_spin(lock); \
msgrng_flags_save(mflags); \
}while(0)
#define msgrng_access_restore(lock, mflags) do { \
msgrng_flags_restore(mflags); \
mtx_unlock_spin(lock); \
if (rmi_spin_mutex_safe) mtx_unlock_spin(lock); \
}while(0)
#define msgrng_access_enable(mflags) do { \

7
sys/mips/rmi/on_chip.c
View File

@ -262,10 +262,12 @@ register_msgring_handler(int major,
//dbg_msg("major=%d, action=%p, dev_id=%p\n", major, action, dev_id);
mtx_lock_spin(&msgrng_lock);
if (rmi_spin_mutex_safe)
mtx_lock_spin(&msgrng_lock);
tx_stn_handlers[major].action = action;
tx_stn_handlers[major].dev_id = dev_id;
mtx_unlock_spin(&msgrng_lock);
if (rmi_spin_mutex_safe)
mtx_unlock_spin(&msgrng_lock);
if (xlr_test_and_set(&msgring_int_enabled)) {
platform_prep_smp_launch();
@ -301,6 +303,7 @@ pic_init(void)
*/
xlr_write_reg(mmio, PIC_IRT_1_BASE + i, (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i));
}
dbg_msg("PIC init now done\n");
}
void

10
sys/mips/rmi/pcibus.c
View File

@ -148,7 +148,6 @@ static void pic_pcie_ack(void *arg)
*/
int
mips_platform_pci_setup_intr(device_t dev, device_t child,
struct resource *irq, int flags,
@ -174,21 +173,22 @@ mips_platform_pci_setup_intr(device_t dev, device_t child,
return 0;
if (xlr_board_info.is_xls == 0) {
mtx_lock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe) mtx_lock_spin(&xlr_pic_lock);
level = PIC_IRQ_IS_EDGE_TRIGGERED(PIC_IRT_PCIX_INDEX);
xlr_write_reg(mmio, PIC_IRT_0_PCIX, 0x01);
xlr_write_reg(mmio, PIC_IRT_1_PCIX, ((1 << 31) | (level << 30) |
(1 << 6) | (PIC_PCIX_IRQ)));
mtx_unlock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe) mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr(device_get_name(child), filt,
(driver_intr_t *) intr, (void *)arg, PIC_PCIX_IRQ, flags, cookiep);
} else {
mtx_lock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe) mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_IRT_0_BASE + xlrirq - PIC_IRQ_BASE, 0x01);
xlr_write_reg(mmio, PIC_IRT_1_BASE + xlrirq - PIC_IRQ_BASE,
((1 << 31) | (1 << 30) | (1 << 6) | xlrirq));
mtx_unlock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe) mtx_unlock_spin(&xlr_pic_lock);
if (flags & INTR_FAST)
cpu_establish_hardintr(device_get_name(child), filt,

29
sys/mips/rmi/pic.h
View File

@ -30,6 +30,7 @@
#ifndef _RMI_PIC_H_
#define _RMI_PIC_H_
extern int rmi_spin_mutex_safe;
#include <sys/lock.h>
#include <sys/mutex.h>
@ -206,9 +207,11 @@ pic_read_control(void)
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
__uint32_t reg;
mtx_lock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe)
mtx_lock_spin(&xlr_pic_lock);
xlr_read_reg(mmio, PIC_CTRL);
mtx_unlock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe)
mtx_unlock_spin(&xlr_pic_lock);
return reg;
}
@ -217,18 +220,22 @@ pic_write_control(__uint32_t control)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
mtx_lock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe)
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_CTRL, control);
mtx_unlock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe)
mtx_unlock_spin(&xlr_pic_lock);
}
static __inline__ void
pic_update_control(__uint32_t control)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
mtx_lock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe)
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_CTRL, (control | xlr_read_reg(mmio, PIC_CTRL)));
mtx_unlock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe)
mtx_unlock_spin(&xlr_pic_lock);
}
static __inline__ void
@ -241,8 +248,10 @@ pic_ack(int irq)
return;
if (PIC_IRQ_IS_EDGE_TRIGGERED(irq)) {
if (rmi_spin_mutex_safe)
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
if (rmi_spin_mutex_safe)
mtx_unlock_spin(&xlr_pic_lock);
return;
}
@ -258,9 +267,11 @@ pic_delayed_ack(int irq)
return;
if (!PIC_IRQ_IS_EDGE_TRIGGERED(irq)) {
mtx_lock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe)
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
mtx_unlock_spin(&xlr_pic_lock);
if (rmi_spin_mutex_safe)
mtx_unlock_spin(&xlr_pic_lock);
return;
}
}

13
sys/mips/rmi/uart_bus_xlr_iodi.c
View File

@ -38,9 +38,10 @@ __FBSDID("$FreeBSD: src/sys/dev/uart/uart_bus_iodi.c,v 1.6.2.5 2006/02/15 09:16:
#include <machine/bus.h>
#include <sys/rman.h>
#include <machine/resource.h>
#include <mips/rmi/iomap.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_bus.h>
#include <dev/uart/uart_cpu.h>
static int uart_iodi_probe(device_t dev);
@ -58,14 +59,20 @@ static driver_t uart_iodi_driver = {
sizeof(struct uart_softc),
};
extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
static int
uart_iodi_probe(device_t dev)
{
struct uart_softc *sc;
sc = device_get_softc(dev);
sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
sc->sc_class = &uart_ns8250_class;
bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
sc->sc_sysdev->bas.bst = rmi_bus_space;
sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(XLR_UART0ADDR);
sc->sc_bas.bst = rmi_bus_space;
sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(XLR_UART0ADDR);
/* regshft = 2, rclk = 66000000, rid = 0, chan = 0 */
return (uart_bus_probe(dev, 2, 66000000, 0, 0));
}

116
sys/mips/rmi/uart_cpu_mips_xlr.c
View File

@ -50,102 +50,11 @@ __FBSDID("$FreeBSD$");
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/mutex.h>
static int xlr_uart_probe(struct uart_bas *bas);
static void xlr_uart_init(struct uart_bas *bas, int, int, int, int);
static void xlr_uart_term(struct uart_bas *bas);
static void xlr_uart_putc(struct uart_bas *bas, int);
/*static int xlr_uart_poll(struct uart_bas *bas);*/
static int xlr_uart_getc(struct uart_bas *bas, struct mtx *hwmtx);
struct mtx xlr_uart_mtx; /* UartLock */
extern struct uart_ops uart_ns8250_ops;
struct uart_ops xlr_uart_ns8250_ops = {
.probe = xlr_uart_probe,
.init = xlr_uart_init,
.term = xlr_uart_term,
.putc = xlr_uart_putc,
/* .poll = xlr_uart_poll, ?? */
.getc = xlr_uart_getc,
};
#include <mips/rmi/iomap.h>
bus_space_tag_t uart_bus_space_io;
bus_space_tag_t uart_bus_space_mem;
static __inline void
xlr_uart_lock(struct mtx *hwmtx)
{
if (!mtx_initialized(hwmtx))
return;
if (!kdb_active && hwmtx != NULL)
mtx_lock_spin(hwmtx);
}
static __inline void
xlr_uart_unlock(struct mtx *hwmtx)
{
if (!mtx_initialized(hwmtx))
return;
if (!kdb_active && hwmtx != NULL)
mtx_unlock_spin(hwmtx);
}
static int
xlr_uart_probe(struct uart_bas *bas)
{
int res;
xlr_uart_lock(&xlr_uart_mtx);
res = uart_ns8250_ops.probe(bas);
xlr_uart_unlock(&xlr_uart_mtx);
return res;
}
static void
xlr_uart_init(struct uart_bas *bas, int baudrate, int databits,
int stopbits, int parity)
{
xlr_uart_lock(&xlr_uart_mtx);
uart_ns8250_ops.init(bas, baudrate, databits, stopbits, parity);
xlr_uart_unlock(&xlr_uart_mtx);
}
static void
xlr_uart_term(struct uart_bas *bas)
{
xlr_uart_lock(&xlr_uart_mtx);
uart_ns8250_ops.term(bas);
xlr_uart_unlock(&xlr_uart_mtx);
}
static void
xlr_uart_putc(struct uart_bas *bas, int c)
{
xlr_uart_lock(&xlr_uart_mtx);
uart_ns8250_ops.putc(bas, c);
xlr_uart_unlock(&xlr_uart_mtx);
}
/*
static int xlr_uart_poll(struct uart_bas *bas)
{
int res;
xlr_uart_lock(&xlr_uart_mtx);
res = uart_ns8250_ops.poll(bas);
xlr_uart_unlock(&xlr_uart_mtx);
return res;
}
*/
static int
xlr_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
{
return uart_ns8250_ops.getc(bas, hwmtx);
}
int
uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
{
@ -156,29 +65,20 @@ uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
int
uart_cpu_getdev(int devtype, struct uart_devinfo *di)
{
di->ops = &xlr_uart_ns8250_ops;
di->ops = uart_getops(&uart_ns8250_class);
di->bas.chan = 0;
di->bas.bst = uart_bus_space_mem;
/* TODO Need to call bus_space_map() here */
di->bas.bsh = 0xbef14000; /* Try with UART0 */
di->bas.bst = rmi_bus_space;
di->bas.bsh = MIPS_PHYS_TO_KSEG1(XLR_UART0ADDR);
di->bas.regshft = 2;
/* divisor = rclk / (baudrate * 16); */
di->bas.rclk = 66000000;
di->baudrate = 38400;
di->baudrate = 0;
di->databits = 8;
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
/* TODO: Read env variables for all console parameters */
uart_bus_space_io = NULL;
uart_bus_space_mem = rmi_bus_space;
return (0);
}
static void
xlr_uart_mtx_init(void *dummy __unused)
{
mtx_init(&xlr_uart_mtx, "uart lock", NULL, MTX_SPIN);
}
SYSINIT(xlr_init_uart_mtx, SI_SUB_LOCK, SI_ORDER_ANY, xlr_uart_mtx_init, NULL);

62
sys/mips/rmi/xlr_machdep.c
View File

@ -24,8 +24,10 @@
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/conf.h>
@ -92,7 +94,7 @@ unsigned long xlr_io_base = (unsigned long)(DEFAULT_XLR_IO_BASE);
the dynamic kenv is setup */
char boot1_env[4096];
extern unsigned long _gp;
int rmi_spin_mutex_safe=0;
/*
* Parameters from boot loader
*/
@ -366,8 +368,48 @@ mips_init(void)
#endif
}
void tick_init(void);
void (*xlr_putchar)(char)=NULL;
static void
xlr_putc_init(void)
{
uint32_t addr;
addr = (uint32_t)(xlr_boot1_info.uart_putchar & 0x00000000ffffffff);
xlr_putchar = (void (*)(char))(addr);
}
void xlr_putc(char);
void xlr_print_int(uint32_t val);
void
xlr_putc(char c)
{
(*xlr_putchar)(c);
DELAY(1000);
}
void
xlr_print_int(uint32_t val)
{
int i;
int idx;
char ary[16] = {
'0', '1', '2', '3',
'4', '5', '6', '7',
'8', '9', 'a', 'b',
'c', 'd', 'e', 'f'
};
xlr_putc('0');
xlr_putc('x');
for(i=7;i>=0;i--) {
idx = (val >> (i*4)) & 0x0000000f;
xlr_putc(ary[idx]);
}
xlr_putc(' ');
xlr_putc(015);
xlr_putc(012);
}
void tick_init(void);
void
platform_start(__register_t a0 __unused,
__register_t a1 __unused,
@ -377,7 +419,6 @@ platform_start(__register_t a0 __unused,
vm_size_t physsz = 0;
int i, j;
struct xlr_boot1_mem_map *boot_map;
#ifdef SMP
uint32_t tmp;
void (*wakeup) (void *, void *, unsigned int);
@ -411,10 +452,14 @@ platform_start(__register_t a0 __unused,
* xlr_boot1_info.cpu_frequency here.
*/
mips_timer_early_init(platform_get_frequency());
mips_timer_init_params(platform_get_frequency(), 0);
/* Init the time counter in the PIC and local putc routine*/
xlr_putc_init();
rmi_early_counter_init();
/* Init console please */
cninit();
init_static_kenv(boot1_env, sizeof(boot1_env));
printf("Environment (from %d args):\n", xlr_argc - 1);
if (xlr_argc == 1)
printf("\tNone\n");
@ -538,7 +583,12 @@ platform_start(__register_t a0 __unused,
* mips_init() XXX NOTE: We may need to move this to SMP based init
* code for each CPU, later.
*/
printf("Here\n");
rmi_spin_mutex_safe = 1;
on_chip_init();
printf("there\n");
mips_timer_init_params(platform_get_frequency(), 0);
printf("ok\n");
tick_init();
}