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- integrate most recent changes from vendor branch and upgrade to firmware revision 4.5.5

Browse Source 
- add filter support
	- further improvements for T304
- recover gracefully from spurious immediate packets

Approved by: re(blanket)
Supported by: Chelsio
MFC after: 3 days
This commit is contained in:
Kip Macy 2007-07-17 06:50:35 +00:00
parent 8870f0e16b
commit ac3a6d9cef
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=171471
20 changed files with 1497 additions and 697 deletions
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27
sys/dev/cxgb/common/cxgb_common.h
View File

@ -38,8 +38,6 @@ $FreeBSD$
#endif
enum {
MAX_NPORTS = 4,
TP_TMR_RES = 200, /* TP timer resolution in usec */
MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */
EEPROMSIZE = 8192, /* Serial EEPROM size */
RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */
@ -48,6 +46,10 @@ enum {
NCCTRL_WIN = 32, /* # of congestion control windows */
NTX_SCHED = 8, /* # of HW Tx scheduling queues */
PROTO_SRAM_LINES = 128, /* size of protocol sram */
MAX_NPORTS = 4,
TP_TMR_RES = 200,
TP_SRAM_OFFSET = 4096, /* TP SRAM content offset in eeprom */
TP_SRAM_LEN = 2112, /* TP SRAM content offset in eeprom */
};
#define MAX_RX_COALESCING_LEN 12288U
@ -72,8 +74,8 @@ enum { /* adapter interrupt-maintained statistics */
enum {
TP_VERSION_MAJOR = 1,
TP_VERSION_MINOR = 0,
TP_VERSION_MICRO = 44
TP_VERSION_MINOR = 1,
TP_VERSION_MICRO = 0
};
#define S_TP_VERSION_MAJOR 16
@ -96,7 +98,7 @@ enum {
enum {
FW_VERSION_MAJOR = 4,
FW_VERSION_MINOR = 1,
FW_VERSION_MINOR = 5,
FW_VERSION_MICRO = 0
};
@ -393,6 +395,7 @@ enum { /* chip revisions */
T3_REV_A = 0,
T3_REV_B = 2,
T3_REV_B2 = 3,
T3_REV_C = 4,
};
struct trace_params {
@ -467,6 +470,7 @@ struct cmac {
unsigned int tx_xcnt;
u64 tx_mcnt;
unsigned int rx_xcnt;
unsigned int rx_ocnt;
u64 rx_mcnt;
unsigned int toggle_cnt;
unsigned int txen;
@ -562,6 +566,9 @@ static inline void cphy_init(struct cphy *phy, adapter_t *adapter,
/* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */
#define MAC_STATS_ACCUM_SECS 180
/* The external MAC needs accumulation every 30 seconds */
#define VSC_STATS_ACCUM_SECS 30
#define XGM_REG(reg_addr, idx) \
((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
@ -656,9 +663,10 @@ int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data);
int t3_seeprom_wp(adapter_t *adapter, int enable);
int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
u32 *data, int byte_oriented);
int t3_get_tp_version(adapter_t *adapter, u32 *vers);
int t3_check_tpsram_version(adapter_t *adapter);
int t3_check_tpsram(adapter_t *adapter, u8 *tp_ram, unsigned int size);
int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size);
int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size);
int t3_load_fw(adapter_t *adapter, const const u8 *fw_data, unsigned int size);
int t3_get_fw_version(adapter_t *adapter, u32 *vers);
int t3_check_fw_version(adapter_t *adapter);
int t3_init_hw(adapter_t *adapter, u32 fw_params);
@ -668,10 +676,11 @@ int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset
void t3_led_ready(adapter_t *adapter);
void t3_fatal_err(adapter_t *adapter);
void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
void t3_enable_filters(adapter_t *adap);
void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
const u16 *rspq);
int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);
int t3_set_proto_sram(adapter_t *adap, u8 *data);
int t3_set_proto_sram(adapter_t *adap, const u8 *data);
int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask);
void t3_port_failover(adapter_t *adapter, int port);
void t3_failover_done(adapter_t *adapter, int port);
@ -753,8 +762,8 @@ int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n);
int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n);
int t3_vsc7323_init(adapter_t *adap, int nports);
int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port);
int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port);
int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port);
int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port);
int t3_vsc7323_enable(adapter_t *adap, int port, int which);
int t3_vsc7323_disable(adapter_t *adap, int port, int which);
const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac);

24
sys/dev/cxgb/common/cxgb_ctl_defs.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (C) 2003-2007 Chelsio Communications. All rights reserved.
* Copyright (C) 2003-2006 Chelsio Communications. All rights reserved.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
@ -12,7 +12,6 @@
#ifndef _CXGB3_OFFLOAD_CTL_DEFS_H
#define _CXGB3_OFFLOAD_CTL_DEFS_H
enum {
GET_MAX_OUTSTANDING_WR,
GET_TX_MAX_CHUNK,
@ -25,9 +24,6 @@ enum {
GET_IFF_FROM_MAC,
GET_DDP_PARAMS,
GET_PORTS,
FAILOVER,
FAILOVER_DONE,
FAILOVER_CLEAR,
ULP_ISCSI_GET_PARAMS,
ULP_ISCSI_SET_PARAMS,
@ -38,6 +34,14 @@ enum {
RDMA_CQ_DISABLE,
RDMA_CTRL_QP_SETUP,
RDMA_GET_MEM,
FAILOVER,
FAILOVER_DONE,
FAILOVER_CLEAR,
GET_CPUIDX_OF_QSET,
GET_RX_PAGE_INFO,
};
/*
@ -81,7 +85,7 @@ struct ddp_params {
struct adap_ports {
unsigned int nports; /* number of ports on this adapter */
struct ifnet *lldevs[4];
struct net_device *lldevs[2];
};
/*
@ -101,6 +105,14 @@ struct ulp_iscsi_info {
struct pci_dev *pdev;
};
/*
* Offload TX/RX page information.
*/
struct ofld_page_info {
unsigned int page_size; /* Page size, should be a power of 2 */
unsigned int num; /* Number of pages */
};
/*
* Structure used to return information to the RDMA layer.
*/

45
sys/dev/cxgb/common/cxgb_mc5.c
View File

@ -165,16 +165,26 @@ static int init_mask_data_array(struct mc5 *mc5, u32 mask_array_base,
return -1;
/* Initialize the mask array. */
dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
for (i = 0; i < size72; i++) {
if (i == server_base) /* entering server or routing region */
t3_write_reg(adap, A_MC5_DB_DBGI_REQ_DATA0,
mc5->mode == MC5_MODE_144_BIT ?
0xfffffff9 : 0xfffffffd);
for (i = 0; i < server_base; i++) {
dbgi_wr_data3(adap, 0x3fffffff, 0xfff80000, 0xff);
if (mc5_write(adap, mask_array_base + (i << addr_shift),
write_cmd))
return -1;
i++;
dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff);
if (mc5_write(adap, mask_array_base + (i << addr_shift),
write_cmd))
return -1;
}
dbgi_wr_data3(adap,
mc5->mode == MC5_MODE_144_BIT ? 0xfffffff9 : 0xfffffffd,
0xffffffff, 0xff);
for (; i < size72; i++)
if (mc5_write(adap, mask_array_base + (i << addr_shift),
write_cmd))
return -1;
return 0;
}
@ -305,17 +315,15 @@ static int init_idt43102(struct mc5 *mc5)
/* Put MC5 in DBGI mode. */
static inline void mc5_dbgi_mode_enable(const struct mc5 *mc5)
{
t3_write_reg(mc5->adapter, A_MC5_DB_CONFIG,
V_TMMODE(mc5->mode == MC5_MODE_72_BIT) | F_DBGIEN);
t3_set_reg_field(mc5->adapter, A_MC5_DB_CONFIG, F_PRTYEN | F_MBUSEN,
F_DBGIEN);
}
/* Put MC5 in M-Bus mode. */
static void mc5_dbgi_mode_disable(const struct mc5 *mc5)
{
t3_write_reg(mc5->adapter, A_MC5_DB_CONFIG,
V_TMMODE(mc5->mode == MC5_MODE_72_BIT) |
V_COMPEN(mc5->mode == MC5_MODE_72_BIT) |
V_PRTYEN(mc5->parity_enabled) | F_MBUSEN);
t3_set_reg_field(mc5->adapter, A_MC5_DB_CONFIG, F_DBGIEN,
V_PRTYEN(mc5->parity_enabled) | F_MBUSEN);
}
/*
@ -325,9 +333,9 @@ static void mc5_dbgi_mode_disable(const struct mc5 *mc5)
int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
unsigned int nroutes)
{
u32 cfg;
int err;
unsigned int tcam_size = mc5->tcam_size;
unsigned int mode72 = mc5->mode == MC5_MODE_72_BIT;
adapter_t *adap = mc5->adapter;
if (!tcam_size)
@ -336,10 +344,12 @@ int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
if (nroutes > MAX_ROUTES || nroutes + nservers + nfilters > tcam_size)
return -EINVAL;
if (nfilters && adap->params.rev < T3_REV_C)
mc5->parity_enabled = 0;
/* Reset the TCAM */
cfg = t3_read_reg(adap, A_MC5_DB_CONFIG) & ~F_TMMODE;
cfg |= V_TMMODE(mc5->mode == MC5_MODE_72_BIT) | F_TMRST;
t3_write_reg(adap, A_MC5_DB_CONFIG, cfg);
t3_set_reg_field(adap, A_MC5_DB_CONFIG, F_TMMODE | F_COMPEN,
V_COMPEN(mode72) | V_TMMODE(mode72) | F_TMRST);
if (t3_wait_op_done(adap, A_MC5_DB_CONFIG, F_TMRDY, 1, 500, 0)) {
CH_ERR(adap, "TCAM reset timed out\n");
return -1;
@ -351,8 +361,6 @@ int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
t3_write_reg(adap, A_MC5_DB_SERVER_INDEX,
tcam_size - nroutes - nfilters - nservers);
mc5->parity_enabled = 1;
/* All the TCAM addresses we access have only the low 32 bits non 0 */
t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR1, 0);
t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR2, 0);
@ -467,6 +475,7 @@ void __devinit t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode)
u32 cfg = t3_read_reg(adapter, A_MC5_DB_CONFIG);
mc5->adapter = adapter;
mc5->parity_enabled = 1;
mc5->mode = (unsigned char) mode;
mc5->part_type = (unsigned char) G_TMTYPE(cfg);
if (cfg & F_TMTYPEHI)

36
sys/dev/cxgb/common/cxgb_t3_cpl.h
View File

@ -31,10 +31,6 @@ $FreeBSD$
#ifndef T3_CPL_H
#define T3_CPL_H
#if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD)
# include <asm/byteorder.h>
#endif
enum CPL_opcode {
CPL_PASS_OPEN_REQ = 0x1,
CPL_PASS_ACCEPT_RPL = 0x2,
@ -133,6 +129,7 @@ enum CPL_error {
enum {
CPL_CONN_POLICY_AUTO = 0,
CPL_CONN_POLICY_ASK = 1,
CPL_CONN_POLICY_FILTER = 2,
CPL_CONN_POLICY_DENY = 3
};
@ -259,16 +256,16 @@ struct work_request_hdr {
/* Applicable to BYPASS WRs only: the uP will added a CPL_BARRIER before
* and after the BYPASS WR if the ATOMIC bit is set.
*/
#define S_WR_ATOMIC 16
#define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC)
#define F_WR_ATOMIC V_WR_ATOMIC(1U)
#define S_WR_ATOMIC 16
#define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC)
#define F_WR_ATOMIC V_WR_ATOMIC(1U)
/* Applicable to BYPASS WRs only: the uP will flush buffered non abort
* related WRs.
*/
#define S_WR_FLUSH 17
#define V_WR_FLUSH(x) ((x) << S_WR_FLUSH)
#define F_WR_FLUSH V_WR_FLUSH(1U)
#define S_WR_FLUSH 17
#define V_WR_FLUSH(x) ((x) << S_WR_FLUSH)
#define F_WR_FLUSH V_WR_FLUSH(1U)
#define S_WR_DATATYPE 20
#define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
@ -415,6 +412,11 @@ struct work_request_hdr {
#define V_CPU_IDX(x) ((x) << S_CPU_IDX)
#define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)
#define S_OPT1_VLAN 6
#define M_OPT1_VLAN 0xFFF
#define V_OPT1_VLAN(x) ((x) << S_OPT1_VLAN)
#define G_OPT1_VLAN(x) (((x) >> S_OPT1_VLAN) & M_OPT1_VLAN)
#define S_MAC_MATCH_VALID 18
#define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
#define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U)
@ -808,6 +810,12 @@ struct tx_data_wr {
__be32 param;
};
/* tx_data_wr.flags fields */
#define S_TX_ACK_PAGES 21
#define M_TX_ACK_PAGES 0x7
#define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES)
#define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
/* tx_data_wr.param fields */
#define S_TX_PORT 0
#define M_TX_PORT 0x7
@ -1009,7 +1017,7 @@ struct cpl_rx_data_ddp {
union {
__be32 nxt_seq;
__be32 ddp_report;
} __U;
} u;
__be32 ulp_crc;
__be32 ddpvld_status;
};
@ -1515,7 +1523,7 @@ struct ulp_mem_io {
__be32 len;
};
/* ulp_mem_io.cmd_lock_addr fields */
/* ulp_mem_io.cmd_lock_addr fields */
#define S_ULP_MEMIO_ADDR 0
#define M_ULP_MEMIO_ADDR 0x7FFFFFF
#define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
@ -1524,7 +1532,7 @@ struct ulp_mem_io {
#define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
#define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
/* ulp_mem_io.len fields */
/* ulp_mem_io.len fields */
#define S_ULP_MEMIO_DATA_LEN 28
#define M_ULP_MEMIO_DATA_LEN 0xF
#define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
@ -1534,7 +1542,7 @@ struct ulp_txpkt {
__be32 len;
};
/* ulp_txpkt.cmd_dest fields */
/* ulp_txpkt.cmd_dest fields */
#define S_ULP_TXPKT_DEST 24
#define M_ULP_TXPKT_DEST 0xF
#define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)

145
sys/dev/cxgb/common/cxgb_t3_hw.c
View File

@ -37,8 +37,8 @@ __FBSDID("$FreeBSD$");
#include <dev/cxgb/cxgb_include.h>
#endif
#define DENTER() printf("entered %s\n", __FUNCTION__);
#define DEXIT() printf("exiting %s\n", __FUNCTION__);
#undef msleep
#define msleep t3_os_sleep
/**
@ -355,7 +355,7 @@ int t3_phy_reset(struct cphy *phy, int mmd, int wait)
return err;
ctl &= BMCR_RESET;
if (ctl)
t3_os_sleep(1);
msleep(1);
} while (ctl && --wait);
return ctl ? -1 : 0;
@ -482,7 +482,7 @@ const struct adapter_info *t3_get_adapter_info(unsigned int id)
#define CAPS_10G (SUPPORTED_10000baseT_Full | SUPPORTED_AUI)
static struct port_type_info port_types[] = {
{ NULL, 0, NULL },
{ NULL },
{ t3_ael1002_phy_prep, CAPS_10G | SUPPORTED_FIBRE,
"10GBASE-XR" },
{ t3_vsc8211_phy_prep, CAPS_1G | SUPPORTED_TP | SUPPORTED_IRQ,
@ -594,7 +594,7 @@ int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data)
t3_os_pci_write_config_2(adapter, base + PCI_VPD_ADDR,
(u16)addr | PCI_VPD_ADDR_F);
do {
t3_os_sleep(1);
msleep(1);
t3_os_pci_read_config_2(adapter, base + PCI_VPD_ADDR, &val);
} while ((val & PCI_VPD_ADDR_F) && --attempts);
@ -770,7 +770,7 @@ static int flash_wait_op(adapter_t *adapter, int attempts, int delay)
if (--attempts == 0)
return -EAGAIN;
if (delay)
t3_os_sleep(delay);
msleep(delay);
}
}
@ -859,11 +859,33 @@ static int t3_write_flash(adapter_t *adapter, unsigned int addr,
return 0;
}
/**
* t3_get_tp_version - read the tp sram version
* @adapter: the adapter
* @vers: where to place the version
*
* Reads the protocol sram version from sram.
*/
int t3_get_tp_version(adapter_t *adapter, u32 *vers)
{
int ret;
/* Get version loaded in SRAM */
t3_write_reg(adapter, A_TP_EMBED_OP_FIELD0, 0);
ret = t3_wait_op_done(adapter, A_TP_EMBED_OP_FIELD0,
1, 1, 5, 1);
if (ret)
return ret;
*vers = t3_read_reg(adapter, A_TP_EMBED_OP_FIELD1);
return 0;
}
/**
* t3_check_tpsram_version - read the tp sram version
* @adapter: the adapter
*
* Reads the protocol sram version from serial eeprom.
*/
int t3_check_tpsram_version(adapter_t *adapter)
{
@ -886,6 +908,9 @@ int t3_check_tpsram_version(adapter_t *adapter)
if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR)
return 0;
CH_ERR(adapter, "found wrong TP version (%u.%u), "
"driver needs version %d.%d\n", major, minor,
TP_VERSION_MAJOR, TP_VERSION_MINOR);
return -EINVAL;
}
@ -899,7 +924,7 @@ int t3_check_tpsram_version(adapter_t *adapter)
* Checks if an adapter's tp sram is compatible with the driver.
* Returns 0 if the versions are compatible, a negative error otherwise.
*/
int t3_check_tpsram(adapter_t *adapter, u8 *tp_sram, unsigned int size)
int t3_check_tpsram(adapter_t *adapter, const u8 *tp_sram, unsigned int size)
{
u32 csum;
unsigned int i;
@ -960,8 +985,8 @@ int t3_check_fw_version(adapter_t *adapter)
return 0;
CH_ERR(adapter, "found wrong FW version (%u.%u), "
"driver needs version %d.%d\n", major, minor,
FW_VERSION_MAJOR, FW_VERSION_MINOR);
"driver needs version %d.%d\n", major, minor,
FW_VERSION_MAJOR, FW_VERSION_MINOR);
return -EINVAL;
}
@ -2329,6 +2354,28 @@ void t3_tp_set_offload_mode(adapter_t *adap, int enable)
V_NICMODE(!enable));
}
static void tp_wr_bits_indirect(adapter_t *adap, unsigned int addr,
unsigned int mask, unsigned int val)
{
t3_write_reg(adap, A_TP_PIO_ADDR, addr);
val |= t3_read_reg(adap, A_TP_PIO_DATA) & ~mask;
t3_write_reg(adap, A_TP_PIO_DATA, val);
}
/**
* t3_enable_filters - enable the HW filters
* @adap: the adapter
*
* Enables the HW filters for NIC traffic.
*/
void t3_enable_filters(adapter_t *adap)
{
t3_set_reg_field(adap, A_TP_IN_CONFIG, F_NICMODE, 0);
t3_set_reg_field(adap, A_MC5_DB_CONFIG, 0, F_FILTEREN);
t3_set_reg_field(adap, A_TP_GLOBAL_CONFIG, 0, V_FIVETUPLELOOKUP(3));
tp_wr_bits_indirect(adap, A_TP_INGRESS_CONFIG, 0, F_LOOKUPEVERYPKT);
}
/**
* pm_num_pages - calculate the number of pages of the payload memory
* @mem_size: the size of the payload memory
@ -2422,14 +2469,6 @@ static inline void tp_wr_indirect(adapter_t *adap, unsigned int addr, u32 val)
t3_write_reg(adap, A_TP_PIO_DATA, val);
}
static void tp_wr_bits_indirect(adapter_t *adap, unsigned int addr,
unsigned int mask, unsigned int val)
{
t3_write_reg(adap, A_TP_PIO_ADDR, addr);
val |= t3_read_reg(adap, A_TP_PIO_DATA) & ~mask;
t3_write_reg(adap, A_TP_PIO_DATA, val);
}
static void tp_config(adapter_t *adap, const struct tp_params *p)
{
t3_write_reg(adap, A_TP_GLOBAL_CONFIG, F_TXPACINGENABLE | F_PATHMTU |
@ -2459,10 +2498,12 @@ static void tp_config(adapter_t *adap, const struct tp_params *p)
if (adap->params.rev > 0) {
tp_wr_indirect(adap, A_TP_EGRESS_CONFIG, F_REWRITEFORCETOSIZE);
t3_set_reg_field(adap, A_TP_PARA_REG3, F_TXPACEAUTO,
F_TXPACEAUTO);
t3_set_reg_field(adap, A_TP_PARA_REG3, 0,
F_TXPACEAUTO | F_TXPACEAUTOSTRICT);
t3_set_reg_field(adap, A_TP_PC_CONFIG, F_LOCKTID, F_LOCKTID);
t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEAUTOSTRICT);
tp_wr_indirect(adap, A_TP_VLAN_PRI_MAP, 0xfa50);
tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP0, 0xfac688);
tp_wr_indirect(adap, A_TP_MAC_MATCH_MAP1, 0xfac688);
} else
t3_set_reg_field(adap, A_TP_PARA_REG3, 0, F_TXPACEFIXED);
@ -2816,17 +2857,17 @@ static void ulp_config(adapter_t *adap, const struct tp_params *p)
*
* Write the contents of the protocol SRAM.
*/
int t3_set_proto_sram(adapter_t *adap, u8 *data)
int t3_set_proto_sram(adapter_t *adap, const u8 *data)
{
int i;
u32 *buf = (u32 *)data;
u32 *buf = (u32 *)(uintptr_t)data;
for (i = 0; i < PROTO_SRAM_LINES; i++) {
t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, htobe32(*buf++));
t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, htobe32(*buf++));
t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, htobe32(*buf++));
t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, htobe32(*buf++));
t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, htobe32(*buf++));
t3_write_reg(adap, A_TP_EMBED_OP_FIELD5, cpu_to_be32(*buf++));
t3_write_reg(adap, A_TP_EMBED_OP_FIELD4, cpu_to_be32(*buf++));
t3_write_reg(adap, A_TP_EMBED_OP_FIELD3, cpu_to_be32(*buf++));
t3_write_reg(adap, A_TP_EMBED_OP_FIELD2, cpu_to_be32(*buf++));
t3_write_reg(adap, A_TP_EMBED_OP_FIELD1, cpu_to_be32(*buf++));
t3_write_reg(adap, A_TP_EMBED_OP_FIELD0, i << 1 | 1 << 31);
if (t3_wait_op_done(adap, A_TP_EMBED_OP_FIELD0, 1, 1, 5, 1))
@ -3053,7 +3094,7 @@ static int calibrate_xgm(adapter_t *adapter)
for (i = 0; i < 5; ++i) {
t3_write_reg(adapter, A_XGM_XAUI_IMP, 0);
(void) t3_read_reg(adapter, A_XGM_XAUI_IMP);
t3_os_sleep(1);
msleep(1);
v = t3_read_reg(adapter, A_XGM_XAUI_IMP);
if (!(v & (F_XGM_CALFAULT | F_CALBUSY))) {
t3_write_reg(adapter, A_XGM_XAUI_IMP,
@ -3140,12 +3181,12 @@ static int mc7_init(struct mc7 *mc7, unsigned int mc7_clock, int mem_type)
t3_write_reg(adapter, mc7->offset + A_MC7_CFG, val | F_IFEN);
val = t3_read_reg(adapter, mc7->offset + A_MC7_CFG); /* flush */
t3_os_sleep(1);
msleep(1);
if (!slow) {
t3_write_reg(adapter, mc7->offset + A_MC7_CAL, F_SGL_CAL_EN);
(void) t3_read_reg(adapter, mc7->offset + A_MC7_CAL);
t3_os_sleep(1);
msleep(1);
if (t3_read_reg(adapter, mc7->offset + A_MC7_CAL) &
(F_BUSY | F_SGL_CAL_EN | F_CAL_FAULT)) {
CH_ERR(adapter, "%s MC7 calibration timed out\n",
@ -3211,7 +3252,7 @@ static int mc7_init(struct mc7 *mc7, unsigned int mc7_clock, int mem_type)
attempts = 50;
do {
t3_os_sleep(250);
msleep(250);
val = t3_read_reg(adapter, mc7->offset + A_MC7_BIST_OP);
} while ((val & F_BUSY) && --attempts);
if (val & F_BUSY) {
@ -3297,11 +3338,8 @@ int t3_init_hw(adapter_t *adapter, u32 fw_params)
else if (calibrate_xgm(adapter))
goto out_err;
if (adapter->params.nports > 2) {
if (adapter->params.nports > 2)
t3_mac_reset(&adap2pinfo(adapter, 0)->mac);
if ((err = t3_vsc7323_init(adapter, adapter->params.nports)))
goto out_err;
}
if (vpd->mclk) {
partition_mem(adapter, &adapter->params.tp);
@ -3341,7 +3379,7 @@ int t3_init_hw(adapter_t *adapter, u32 fw_params)
(void) t3_read_reg(adapter, A_CIM_BOOT_CFG); /* flush */
do { /* wait for uP to initialize */
t3_os_sleep(20);
msleep(20);
} while (t3_read_reg(adapter, A_CIM_HOST_ACC_DATA) && --attempts);
if (!attempts) {
CH_ERR(adapter, "uP initialization timed out\n");
@ -3453,7 +3491,6 @@ void mac_prep(struct cmac *mac, adapter_t *adapter, int index)
{
mac->adapter = adapter;
mac->multiport = adapter->params.nports > 2;
if (mac->multiport) {
mac->ext_port = (unsigned char)index;
mac->nucast = 8;
@ -3516,7 +3553,7 @@ static int t3_reset_adapter(adapter_t *adapter)
* XXX The delay time should be modified.
*/
for (i = 0; i < 10; i++) {
t3_os_sleep(50);
msleep(50);
t3_os_pci_read_config_2(adapter, 0x00, &devid);
if (devid == 0x1425)
break;
@ -3548,16 +3585,18 @@ int __devinit t3_prep_adapter(adapter_t *adapter,
adapter->params.chan_map = !!ai->nports0 | (!!ai->nports1 << 1);
adapter->params.rev = t3_read_reg(adapter, A_PL_REV);
adapter->params.linkpoll_period = 0;
adapter->params.stats_update_period = is_10G(adapter) ?
MAC_STATS_ACCUM_SECS : (MAC_STATS_ACCUM_SECS * 10);
if (adapter->params.nports > 2)
adapter->params.stats_update_period = VSC_STATS_ACCUM_SECS;
else
adapter->params.stats_update_period = is_10G(adapter) ?
MAC_STATS_ACCUM_SECS : (MAC_STATS_ACCUM_SECS * 10);
adapter->params.pci.vpd_cap_addr =
t3_os_find_pci_capability(adapter, PCI_CAP_ID_VPD);
ret = get_vpd_params(adapter, &adapter->params.vpd);
if (ret < 0) {
printf("failed to get VPD params\n");
if (ret < 0)
return ret;
}
if (reset && t3_reset_adapter(adapter))
return -1;
@ -3606,24 +3645,18 @@ int __devinit t3_prep_adapter(adapter_t *adapter,
early_hw_init(adapter, ai);
if (adapter->params.nports > 2 &&
(ret = t3_vsc7323_init(adapter, adapter->params.nports)))
return ret;
for_each_port(adapter, i) {
u8 hw_addr[6];
struct port_info *p = adap2pinfo(adapter, i);
while (adapter->params.vpd.port_type[j] == 0) {
while (!adapter->params.vpd.port_type[j])
++j;
}
if (adapter->params.vpd.port_type[j] > sizeof(port_types)/sizeof(port_types[0])) {
printf("bad port type idx=%d\n", adapter->params.vpd.port_type[j]);
printf("port types: ");
for (i = 0; i < j; i++)
printf("port[%d]=%d ", i, adapter->params.vpd.port_type[i]);
printf("\n");
return -1;
}
p->port_type = &port_types[adapter->params.vpd.port_type[j]];
p->port_type = &port_types[adapter->params.vpd.port_type[j]];
p->port_type->phy_prep(&p->phy, adapter, ai->phy_base_addr + j,
ai->mdio_ops);
mac_prep(&p->mac, adapter, j);

37
sys/dev/cxgb/common/cxgb_vsc7323.c
View File

@ -115,13 +115,16 @@ int t3_vsc7323_init(adapter_t *adap, int nports)
{ VSC_REG(2, 0, 0x2f), 0 },
{ VSC_REG(2, 0, 0xf), 0xa0010291 },
{ VSC_REG(2, 1, 0x2f), 1 },
{ VSC_REG(2, 1, 0xf), 0xa0026301 }
{ VSC_REG(2, 1, 0xf), 0xa026301 }
};
static struct addr_val_pair xg_avp[] = {
{ VSC_REG(1, 10, 0), 0x600b },
{ VSC_REG(1, 10, 2), 0x4000 },
{ VSC_REG(1, 10, 1), 0x70600 }, //QUANTA = 96*1024*8/512
{ VSC_REG(1, 10, 2), 0x2710 },
{ VSC_REG(1, 10, 5), 0x65 },
{ VSC_REG(1, 10, 7), 3 },
{ VSC_REG(1, 10, 7), 0x23 },
{ VSC_REG(1, 10, 0x23), 0x800007bf },
{ VSC_REG(1, 10, 0x23), 0x000007bf },
{ VSC_REG(1, 10, 0x23), 0x800007bf },
{ VSC_REG(1, 10, 0x24), 4 }
};
@ -130,10 +133,9 @@ int t3_vsc7323_init(adapter_t *adap, int nports)
for (i = 0; i < ARRAY_SIZE(sys_avp); i++)
if ((ret = t3_elmr_blk_write(adap, sys_avp[i].reg_addr,
&sys_avp[i].val, 1)))
&sys_avp[i].val, 1)))
return ret;
ing_step = 0xc0 / nports;
egr_step = 0x40 / nports;
ing_bot = egr_bot = 0;
@ -141,22 +143,27 @@ int t3_vsc7323_init(adapter_t *adap, int nports)
// egr_wm = egr_step * 64;
/* {ING,EGR}_CONTROL.CLR = 1 here */
for (i = 0; i < nports; i++)
if ((ret = elmr_write(adap, VSC_REG(2, 0, 0x10 + i),
for (i = 0; i < nports; i++) {
if (
(ret = elmr_write(adap, VSC_REG(2, 0, 0x10 + i),
((ing_bot + ing_step) << 16) | ing_bot)) ||
(ret = elmr_write(adap, VSC_REG(2, 0, 0x50 + i), 0)) ||
(ret = elmr_write(adap, VSC_REG(2, 0, 0x40 + i),
0x6000a00)) ||
(ret = elmr_write(adap, VSC_REG(2, 0, 0x50 + i), 1)) ||
(ret = elmr_write(adap, VSC_REG(2, 1, 0x10 + i),
((egr_bot + egr_step) << 16) | egr_bot)) ||
(ret = elmr_write(adap, VSC_REG(2, 1, 0x40 + i),
0x2000280)) ||
(ret = elmr_write(adap, VSC_REG(2, 1, 0x50 + i), 0)))
return ret;
ing_bot += ing_step;
egr_bot += egr_step;
}
for (i = 0; i < ARRAY_SIZE(fifo_avp); i++)
if ((ret = t3_elmr_blk_write(adap, fifo_avp[i].reg_addr,
&fifo_avp[i].val, 1)))
return ret;
&fifo_avp[i].val, 1)))
return ret;
for (i = 0; i < ARRAY_SIZE(xg_avp); i++)
if ((ret = t3_elmr_blk_write(adap, xg_avp[i].reg_addr,
@ -198,7 +205,7 @@ int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port)
return r;
}
r = (fc & PAUSE_RX) ? 0x6ffff : 0x2ffff;
r = (fc & PAUSE_RX) ? 0x60200 : 0x20200; //QUANTA = 32*1024*8/512
if (fc & PAUSE_TX)
r |= (1 << 19);
return elmr_write(adap, VSC_REG(1, port, 1), r);
@ -212,12 +219,12 @@ int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port)
int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port)
{
int ret;
ret = elmr_write(adap, VSC_REG(1, port, 3),
(addr[0] << 16) | (addr[1] << 8) | addr[2]);
(addr[0] << 16) | (addr[1] << 8) | addr[2]);
if (!ret)
ret = elmr_write(adap, VSC_REG(1, port, 4),
(addr[3] << 16) | (addr[4] << 8) | addr[5]);
(addr[3] << 16) | (addr[4] << 8) | addr[5]);
return ret;
}

55
sys/dev/cxgb/common/cxgb_xgmac.c
View File

@ -37,6 +37,9 @@ __FBSDID("$FreeBSD$");
#include <dev/cxgb/cxgb_include.h>
#endif
#undef msleep
#define msleep t3_os_sleep
/*
* # of exact address filters. The first one is used for the station address,
* the rest are available for multicast addresses.
@ -154,7 +157,7 @@ int t3_mac_reset(struct cmac *mac)
t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
(void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
if ((val & F_PCS_RESET_) && adap->params.rev) {
t3_os_sleep(1);
msleep(1);
t3b_pcs_reset(mac);
}
@ -179,7 +182,7 @@ static int t3b2_mac_reset(struct cmac *mac)
t3_write_reg(adap, A_XGM_RESET_CTRL + oft, F_MAC_RESET_);
(void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
t3_os_sleep(10);
msleep(10);
/* Check for xgm Rx fifo empty */
if (t3_wait_op_done(adap, A_XGM_RX_MAX_PKT_SIZE_ERR_CNT + oft,
@ -202,7 +205,7 @@ static int t3b2_mac_reset(struct cmac *mac)
t3_write_reg(adap, A_XGM_RESET_CTRL + oft, val);
(void) t3_read_reg(adap, A_XGM_RESET_CTRL + oft); /* flush */
if ((val & F_PCS_RESET_) && adap->params.rev) {
t3_os_sleep(1);
msleep(1);
t3b_pcs_reset(mac);
}
t3_write_reg(adap, A_XGM_RX_CFG + oft,
@ -243,7 +246,6 @@ int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6])
set_addr_filter(mac, idx, addr);
if (mac->multiport && idx < mac->adapter->params.nports)
t3_vsc7323_set_addr(mac->adapter, addr, idx);
return 0;
}
@ -425,8 +427,17 @@ int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc)
if (duplex >= 0 && duplex != DUPLEX_FULL)
return -EINVAL;
if (mac->multiport)
if (mac->multiport) {
val = t3_read_reg(adap, A_XGM_RXFIFO_CFG + oft);
val &= ~V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM);
val |= V_RXFIFOPAUSEHWM(rx_fifo_hwm(t3_read_reg(adap,
A_XGM_RX_MAX_PKT_SIZE + oft)) / 8);
t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
F_TXPAUSEEN);
return t3_vsc7323_set_speed_fc(adap, speed, fc, mac->ext_port);
}
if (speed >= 0) {
if (speed == SPEED_10)
val = V_PORTSPEED(0);
@ -451,7 +462,7 @@ int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, int fc)
t3_write_reg(adap, A_XGM_RXFIFO_CFG + oft, val);
t3_set_reg_field(adap, A_XGM_TX_CFG + oft, F_TXPAUSEEN,
(fc & PAUSE_RX) ? F_TXPAUSEEN : 0);
(fc & PAUSE_RX) ? F_TXPAUSEEN : 0);
return 0;
}
@ -466,12 +477,13 @@ int t3_mac_enable(struct cmac *mac, int which)
return t3_vsc7323_enable(adap, mac->ext_port, which);
if (which & MAC_DIRECTION_TX) {
t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
t3_write_reg(adap, A_TP_PIO_DATA, 0xc0ede401);
t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
t3_write_reg(adap, A_XGM_TX_CTRL + oft, F_TXEN);
t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CNT_CH0 + idx);
mac->tx_mcnt = s->tx_frames;
mac->tx_tcnt = (G_TXDROPCNTCH0RCVD(t3_read_reg(adap,
@ -493,7 +505,6 @@ int t3_mac_enable(struct cmac *mac, int which)
int t3_mac_disable(struct cmac *mac, int which)
{
int idx = macidx(mac);
adapter_t *adap = mac->adapter;
int val;
@ -501,17 +512,14 @@ int t3_mac_disable(struct cmac *mac, int which)
return t3_vsc7323_disable(adap, mac->ext_port, which);
if (which & MAC_DIRECTION_TX) {
val = t3_read_reg(adap, A_MPS_CFG);
t3_write_reg(adap, A_XGM_TX_CTRL + mac->offset, 0);
t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_CFG_CH0 + idx);
t3_write_reg(adap, A_TP_PIO_DATA, 0xc000001f);
t3_write_reg(adap, A_TP_PIO_ADDR, A_TP_TX_DROP_MODE);
t3_set_reg_field(adap, A_TP_PIO_DATA, 1 << idx, 1 << idx);
mac->txen = 0;
}
if (which & MAC_DIRECTION_RX) {
t3_set_reg_field(mac->adapter, A_XGM_RESET_CTRL + mac->offset,
F_PCS_RESET_, 0);
t3_os_sleep(100);
msleep(100);
t3_write_reg(adap, A_XGM_RX_CTRL + mac->offset, 0);
val = F_MAC_RESET_;
if (is_10G(adap))
@ -535,6 +543,13 @@ int t3b2_mac_watchdog_task(struct cmac *mac)
unsigned int rx_mcnt = (unsigned int)s->rx_frames;
unsigned int rx_xcnt;
if (mac->multiport) {
tx_mcnt = t3_read_reg(adap, A_XGM_STAT_TX_FRAME_LOW);
rx_mcnt = t3_read_reg(adap, A_XGM_STAT_RX_FRAMES_LOW);
} else {
tx_mcnt = (unsigned int)s->tx_frames;
rx_mcnt = (unsigned int)s->rx_frames;
}
status = 0;
tx_xcnt = 1; /* By default tx_xcnt is making progress*/
tx_tcnt = mac->tx_tcnt; /* If tx_mcnt is progressing ignore tx_tcnt*/
@ -573,15 +588,18 @@ int t3b2_mac_watchdog_task(struct cmac *mac)
}
rxcheck:
if (rx_mcnt != mac->rx_mcnt)
if (rx_mcnt != mac->rx_mcnt) {
rx_xcnt = (G_TXSPI4SOPCNT(t3_read_reg(adap,
A_XGM_RX_SPI4_SOP_EOP_CNT +
mac->offset)));
else
mac->offset))) +
(s->rx_fifo_ovfl - mac->rx_ocnt);
mac->rx_ocnt = s->rx_fifo_ovfl;
} else
goto out;
if (mac->rx_mcnt != s->rx_frames && rx_xcnt == 0 && mac->rx_xcnt == 0) {
status = 2;
if (!mac->multiport)
status = 2;
goto out;
}
@ -622,6 +640,9 @@ const struct mac_stats *t3_mac_update_stats(struct cmac *mac)
u32 v, lo;
if (mac->multiport)
return t3_vsc7323_update_stats(mac);
RMON_UPDATE64(mac, rx_octets, RX_BYTES_LOW, RX_BYTES_HIGH);
RMON_UPDATE64(mac, rx_frames, RX_FRAMES_LOW, RX_FRAMES_HIGH);
RMON_UPDATE(mac, rx_mcast_frames, RX_MCAST_FRAMES);

9
sys/dev/cxgb/cxgb_adapter.h
View File

@ -138,6 +138,7 @@ enum { /* adapter flags */
USING_MSIX = (1 << 2),
QUEUES_BOUND = (1 << 3),
FW_UPTODATE = (1 << 4),
TPS_UPTODATE = (1 << 5),
};
@ -239,7 +240,7 @@ struct sge_fl {
struct tx_desc;
struct tx_sw_desc;
#define TXQ_TRANSMITTING 0x1
#define TXQ_TRANSMITTING 0x1
struct sge_txq {
uint64_t flags;
@ -301,6 +302,8 @@ struct sge {
struct mtx reg_lock;
};
struct filter_info;
struct adapter {
device_t dev;
int flags;
@ -331,7 +334,11 @@ struct adapter {
struct resource *msix_irq_res[SGE_QSETS];
int msix_irq_rid[SGE_QSETS];
void *msix_intr_tag[SGE_QSETS];
uint8_t rxpkt_map[8]; /* maps RX_PKT interface values to port ids */
uint8_t rrss_map[SGE_QSETS]; /* revers RSS map table */
struct filter_info *filters;
/* Tasks */
struct task ext_intr_task;
struct task slow_intr_task;

27
sys/dev/cxgb/cxgb_ioctl.h
View File

@ -66,6 +66,7 @@ enum {
CH_SETMIIREGS,
CH_SET_FILTER,
CH_SET_HW_SCHED,
CH_DEL_FILTER,
};
struct ch_reg {
@ -130,6 +131,30 @@ struct ch_hw_sched {
int32_t flow_ipg; /* usec */
};
struct ch_filter_tuple {
uint32_t sip;
uint32_t dip;
uint16_t sport;
uint16_t dport;
uint16_t vlan:12;
uint16_t vlan_prio:3;
};
struct ch_filter {
uint32_t cmd;
uint32_t filter_id;
struct ch_filter_tuple val;
struct ch_filter_tuple mask;
uint16_t mac_addr_idx;
uint8_t mac_hit:1;
uint8_t proto:2;
uint8_t want_filter_id:1; /* report filter TID instead of RSS hash */
uint8_t pass:1; /* whether to pass or drop packets */
uint8_t rss:1; /* use RSS or specified qset */
uint8_t qset;
};
#ifndef TCB_SIZE
# define TCB_SIZE 128
#endif
@ -232,5 +257,7 @@ struct mii_data {
#define SIOCGMIIREG _IOWR('f', CH_GETMIIREGS, struct mii_data)
#define SIOCSMIIREG _IOWR('f', CH_SETMIIREGS, struct mii_data)
#define CHELSIO_SET_HW_SCHED _IOWR('f', CH_SET_HW_SCHED, struct ch_hw_sched)
#define CHELSIO_SET_FILTER _IOW('f', CH_SET_FILTER, struct ch_filter)
#define CHELSIO_DEL_FILTER _IOW('f', CH_DEL_FILTER, struct ch_filter)
#define CHELSIO_DEVUP _IO('f', CH_DEVUP)
#endif

585
sys/dev/cxgb/cxgb_main.c
View File

@ -225,6 +225,28 @@ enum {
MIN_FL_ENTRIES = 32
};
struct filter_info {
u32 sip;
u32 sip_mask;
u32 dip;
u16 sport;
u16 dport;
u32 vlan:12;
u32 vlan_prio:3;
u32 mac_hit:1;
u32 mac_idx:4;
u32 mac_vld:1;
u32 pkt_type:2;
u32 report_filter_id:1;
u32 pass:1;
u32 rss:1;
u32 qset:3;
u32 locked:1;
u32 valid:1;
};
enum { FILTER_NO_VLAN_PRI = 7 };
#define PORT_MASK ((1 << MAX_NPORTS) - 1)
/* Table for probing the cards. The desc field isn't actually used */
@ -248,6 +270,29 @@ struct cxgb_ident {
{0, 0, 0, NULL}
};
static int set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset);
static inline char
t3rev2char(struct adapter *adapter)
{
char rev = 'z';
switch(adapter->params.rev) {
case T3_REV_A:
rev = 'a';
break;
case T3_REV_B:
case T3_REV_B2:
rev = 'b';
break;
case T3_REV_C:
rev = 'c';
break;
}
return rev;
}
static struct cxgb_ident *
cxgb_get_ident(device_t dev)
{
@ -299,6 +344,10 @@ cxgb_controller_probe(device_t dev)
return (BUS_PROBE_DEFAULT);
}
#define FW_FNAME "t3fw%d%d%d"
#define TPEEPROM_NAME "t3%ctpe%d%d%d"
#define TPSRAM_NAME "t3%cps%d%d%d"
static int
upgrade_fw(adapter_t *sc)
{
@ -310,7 +359,7 @@ upgrade_fw(adapter_t *sc)
#endif
int status;
snprintf(&buf[0], sizeof(buf), "t3fw%d%d%d", FW_VERSION_MAJOR,
snprintf(&buf[0], sizeof(buf), FW_FNAME, FW_VERSION_MAJOR,
FW_VERSION_MINOR, FW_VERSION_MICRO);
fw = firmware_get(buf);
@ -318,9 +367,12 @@ upgrade_fw(adapter_t *sc)
if (fw == NULL) {
device_printf(sc->dev, "Could not find firmware image %s\n", buf);
return (ENOENT);
}
} else
device_printf(sc->dev, "updating firmware on card with %s\n", buf);
status = t3_load_fw(sc, (const uint8_t *)fw->data, fw->datasize);
device_printf(sc->dev, "firmware update returned %s %d\n", (status == 0) ? "success" : "fail", status);
firmware_put(fw, FIRMWARE_UNLOAD);
return (status);
@ -350,7 +402,10 @@ cxgb_controller_attach(device_t dev)
pectl = (pectl & ~0x7000) | (5 << 12);
pci_write_config(dev, reg + 0x8, pectl, 2);
}
if (sc->link_width != 0 && sc->link_width <= 4) {
ai = cxgb_get_adapter_info(dev);
if (sc->link_width != 0 && sc->link_width <= 4 &&
(ai->nports0 + ai->nports1) <= 2) {
device_printf(sc->dev,
"PCIe x%d Link, expect reduced performance\n",
sc->link_width);
@ -387,7 +442,6 @@ cxgb_controller_attach(device_t dev)
sc->bh = rman_get_bushandle(sc->regs_res);
sc->mmio_len = rman_get_size(sc->regs_res);
ai = cxgb_get_adapter_info(dev);
if (t3_prep_adapter(sc, ai, 1) < 0) {
printf("prep adapter failed\n");
error = ENODEV;
@ -475,6 +529,17 @@ cxgb_controller_attach(device_t dev)
} else {
sc->flags |= FW_UPTODATE;
}
if (t3_check_tpsram_version(sc) != 0) {
/*
* Warn user that a firmware update will be attempted in init.
*/
device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n",
t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
sc->flags &= ~TPS_UPTODATE;
} else {
sc->flags |= TPS_UPTODATE;
}
if ((sc->flags & USING_MSIX) && !singleq)
port_qsets = min((SGE_QSETS/(sc)->params.nports), mp_ncpus);
@ -489,11 +554,11 @@ cxgb_controller_attach(device_t dev)
error = EINVAL;
goto out;
}
sc->portdev[i] = child;
sc->port[i].adapter = sc;
sc->port[i].nqsets = port_qsets;
sc->port[i].first_qset = i*port_qsets;
sc->port[i].port = i;
sc->portdev[i] = child;
device_set_softc(child, &sc->port[i]);
}
if ((error = bus_generic_attach(dev)) != 0)
@ -590,6 +655,7 @@ cxgb_free(struct adapter *sc)
}
#endif
t3_free_sge_resources(sc);
free(sc->filters, M_DEVBUF);
t3_sge_free(sc);
cxgb_offload_exit();
@ -606,6 +672,113 @@ cxgb_free(struct adapter *sc)
return;
}
static int
alloc_filters(struct adapter *adap)
{
struct filter_info *p;
int nfilters;
if ((nfilters = adap->params.mc5.nfilters) == 0)
return (0);
adap->filters = malloc(nfilters*sizeof(struct filter_info),
M_DEVBUF, M_ZERO|M_WAITOK);
if (adap->filters == NULL)
return (ENOMEM);
/* Set the default filters, only need to set non-0 fields here. */
p = &adap->filters[nfilters - 1];
p->vlan = 0xfff;
p->vlan_prio = FILTER_NO_VLAN_PRI;
p->pass = p->rss = p->valid = p->locked = 1;
return (0);
}
static inline void
set_tcb_field_ulp(struct cpl_set_tcb_field *req,
unsigned int tid, unsigned int word,
uint64_t mask, uint64_t val)
{
struct ulp_txpkt *txpkt = (struct ulp_txpkt *)req;
txpkt->cmd_dest = htonl(V_ULPTX_CMD(ULP_TXPKT));
txpkt->len = htonl(V_ULPTX_NFLITS(sizeof(*req) / 8));
OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, tid));
req->reply = V_NO_REPLY(1);
req->cpu_idx = 0;
req->word = htons(word);
req->mask = htobe64(mask);
req->val = htobe64(val);
}
static int
set_filter(struct adapter *adap, int id, const struct filter_info *f)
{
int len;
struct mbuf *m;
struct ulp_txpkt *txpkt;
struct work_request_hdr *wr;
struct cpl_pass_open_req *oreq;
struct cpl_set_tcb_field *sreq;
len = sizeof(*wr) + sizeof(*oreq) + 2 * sizeof(*sreq);
id += t3_mc5_size(&adap->mc5) - adap->params.mc5.nroutes -
adap->params.mc5.nfilters;
m = m_gethdr(M_TRYWAIT, MT_DATA);
wr = mtod(m, struct work_request_hdr *);
wr->wr_hi = htonl(V_WR_OP(FW_WROPCODE_BYPASS) | F_WR_ATOMIC);
m->m_len = m->m_pkthdr.len = len;
oreq = (struct cpl_pass_open_req *)(wr + 1);
txpkt = (struct ulp_txpkt *)oreq;
txpkt->cmd_dest = htonl(V_ULPTX_CMD(ULP_TXPKT));
txpkt->len = htonl(V_ULPTX_NFLITS(sizeof(*oreq) / 8));
OPCODE_TID(oreq) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ, id));
oreq->local_port = htons(f->dport);
oreq->peer_port = htons(f->sport);
oreq->local_ip = htonl(f->dip);
oreq->peer_ip = htonl(f->sip);
oreq->peer_netmask = htonl(f->sip_mask);
oreq->opt0h = 0;
oreq->opt0l = htonl(F_NO_OFFLOAD);
oreq->opt1 = htonl(V_MAC_MATCH_VALID(f->mac_vld) |
V_CONN_POLICY(CPL_CONN_POLICY_FILTER) |
V_VLAN_PRI(f->vlan_prio >> 1) |
V_VLAN_PRI_VALID(f->vlan_prio != FILTER_NO_VLAN_PRI) |
V_PKT_TYPE(f->pkt_type) | V_OPT1_VLAN(f->vlan) |
V_MAC_MATCH(f->mac_idx | (f->mac_hit << 4)));
sreq = (struct cpl_set_tcb_field *)(oreq + 1);
set_tcb_field_ulp(sreq, id, 1, 0x1800808000ULL,
(f->report_filter_id << 15) | (1 << 23) |
((u64)f->pass << 35) | ((u64)!f->rss << 36));
set_tcb_field_ulp(sreq + 1, id, 25, 0x3f80000,
(u64)adap->rrss_map[f->qset] << 19);
t3_mgmt_tx(adap, m);
return 0;
}
static int
setup_hw_filters(struct adapter *adap)
{
int i, err;
if (adap->filters == NULL)
return 0;
t3_enable_filters(adap);
for (i = err = 0; i < adap->params.mc5.nfilters && !err; i++)
if (adap->filters[i].locked)
err = set_filter(adap, i, &adap->filters[i]);
return err;
}
/**
* setup_sge_qsets - configure SGE Tx/Rx/response queues
* @sc: the controller softc
@ -807,11 +980,21 @@ cxgb_port_attach(device_t dev)
ifp->if_capabilities |= CXGB_CAP;
ifp->if_capenable |= CXGB_CAP_ENABLE;
ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO);
/*
* disable TSO on 4-port - it isn't supported by the firmware yet
*/
if (p->adapter->params.nports > 2) {
ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6);
ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6);
ifp->if_hwassist &= ~CSUM_TSO;
}
ether_ifattach(ifp, p->hw_addr);
#ifdef DEFAULT_JUMBO
ifp->if_mtu = 9000;
#endif
/*
* Only default to jumbo frames on 10GigE
*/
if (p->adapter->params.nports <= 2)
ifp->if_mtu = 9000;
if ((err = cxgb_makedev(p)) != 0) {
printf("makedev failed %d\n", err);
return (err);
@ -1089,23 +1272,30 @@ static void
setup_rss(adapter_t *adap)
{
int i;
u_int nq0 = adap->port[0].nqsets;
u_int nq1 = max((u_int)adap->port[1].nqsets, 1U);
u_int nq[2];
uint8_t cpus[SGE_QSETS + 1];
uint16_t rspq_map[RSS_TABLE_SIZE];
nq[0] = adap->port[0].nqsets;
nq[1] = max((u_int)adap->port[1].nqsets, 1U);
for (i = 0; i < SGE_QSETS; ++i)
cpus[i] = i;
cpus[SGE_QSETS] = 0xff;
for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) {
rspq_map[i] = i % nq0;
rspq_map[i + RSS_TABLE_SIZE / 2] = (i % nq1) + nq0;
rspq_map[i] = nq[0] ? i % nq[0] : 0;
rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0;
}
/* Calculate the reverse RSS map table */
for (i = 0; i < RSS_TABLE_SIZE; ++i)
if (adap->rrss_map[rspq_map[i]] == 0xff)
adap->rrss_map[rspq_map[i]] = i;
t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN |
F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN |
V_RRCPLCPUSIZE(6), cpus, rspq_map);
F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN |
F_RRCPLMAPEN | V_RRCPLCPUSIZE(6), cpus, rspq_map);
}
/*
@ -1175,7 +1365,7 @@ send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo,
struct mbuf *m;
struct mngt_pktsched_wr *req;
m = m_gethdr(M_NOWAIT, MT_DATA);
m = m_gethdr(M_DONTWAIT, MT_DATA);
if (m) {
req = mtod(m, struct mngt_pktsched_wr *);
req->wr_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT));
@ -1204,6 +1394,101 @@ bind_qsets(adapter_t *sc)
}
}
static void
update_tpeeprom(struct adapter *adap)
{
const struct firmware *tpeeprom;
char buf[64];
uint32_t version;
unsigned int major, minor;
int ret, len;
char rev;
t3_seeprom_read(adap, TP_SRAM_OFFSET, &version);
major = G_TP_VERSION_MAJOR(version);
minor = G_TP_VERSION_MINOR(version);
if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR)
return;
rev = t3rev2char(adap);
snprintf(buf, sizeof(buf), TPEEPROM_NAME, rev,
TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
tpeeprom = firmware_get(buf);
if (tpeeprom == NULL) {
device_printf(adap->dev, "could not load TP EEPROM: unable to load %s\n",
buf);
return;
}
len = tpeeprom->datasize - 4;
ret = t3_check_tpsram(adap, tpeeprom->data, tpeeprom->datasize);
if (ret)
goto release_tpeeprom;
if (len != TP_SRAM_LEN) {
device_printf(adap->dev, "%s length is wrong len=%d expected=%d\n", buf, len, TP_SRAM_LEN);
return;
}
ret = set_eeprom(&adap->port[0], tpeeprom->data, tpeeprom->datasize,
TP_SRAM_OFFSET);
if (!ret) {
device_printf(adap->dev,
"Protocol SRAM image updated in EEPROM to %d.%d.%d\n",
TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
} else
device_printf(adap->dev, "Protocol SRAM image update in EEPROM failed\n");
release_tpeeprom:
firmware_put(tpeeprom, FIRMWARE_UNLOAD);
return;
}
static int
update_tpsram(struct adapter *adap)
{
const struct firmware *tpsram;
char buf[64];
int ret;
char rev;
rev = t3rev2char(adap);
if (!rev)
return 0;
update_tpeeprom(adap);
snprintf(buf, sizeof(buf), TPSRAM_NAME, rev,
TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
tpsram = firmware_get(buf);
if (tpsram == NULL){
device_printf(adap->dev, "could not load TP SRAM: unable to load %s\n",
buf);
return (EINVAL);
} else
device_printf(adap->dev, "updating TP SRAM with %s\n", buf);
ret = t3_check_tpsram(adap, tpsram->data, tpsram->datasize);
if (ret)
goto release_tpsram;
ret = t3_set_proto_sram(adap, tpsram->data);
if (ret)
device_printf(adap->dev, "loading protocol SRAM failed\n");
release_tpsram:
firmware_put(tpsram, FIRMWARE_UNLOAD);
return ret;
}
/**
* cxgb_up - enable the adapter
* @adap: adapter being enabled
@ -1221,11 +1506,11 @@ cxgb_up(struct adapter *sc)
if ((sc->flags & FULL_INIT_DONE) == 0) {
if ((sc->flags & FW_UPTODATE) == 0)
err = upgrade_fw(sc);
if (err)
goto out;
if ((err = upgrade_fw(sc)))
goto out;
if ((sc->flags & TPS_UPTODATE) == 0)
if ((err = update_tpsram(sc)))
goto out;
err = t3_init_hw(sc, 0);
if (err)
goto out;
@ -1236,6 +1521,7 @@ cxgb_up(struct adapter *sc)
if (err)
goto out;
alloc_filters(sc);
setup_rss(sc);
sc->flags |= FULL_INIT_DONE;
}
@ -1268,9 +1554,11 @@ cxgb_up(struct adapter *sc)
t3_sge_start(sc);
t3_intr_enable(sc);
if ((sc->flags & (USING_MSIX | QUEUES_BOUND)) == USING_MSIX)
if ((sc->flags & (USING_MSIX | QUEUES_BOUND)) == USING_MSIX) {
bind_qsets(sc);
sc->flags |= QUEUES_BOUND;
setup_hw_filters(sc);
sc->flags |= QUEUES_BOUND;
}
out:
return (err);
irq_err:
@ -1334,7 +1622,7 @@ offload_open(struct port_info *pi)
if (!adap_up)
err = cxgb_up(adapter);
ADAPTER_UNLOCK(pi->adapter);
if (err < 0)
if (err)
return (err);
t3_tp_set_offload_mode(adapter, 1);
@ -1407,7 +1695,7 @@ cxgb_init_locked(struct port_info *p)
ifp = p->ifp;
ADAPTER_LOCK(p->adapter);
if ((sc->open_device_map == 0) && ((err = cxgb_up(sc)) < 0)) {
if ((sc->open_device_map == 0) && (err = cxgb_up(sc))) {
ADAPTER_UNLOCK(p->adapter);
cxgb_stop_locked(p);
return;
@ -1866,10 +2154,170 @@ cxgb_tick_handler(void *arg, int count)
*/
ADAPTER_UNLOCK(sc);
if (p->rev == T3_REV_B2)
if (p->rev == T3_REV_B2 && p->nports < 4)
check_t3b2_mac(sc);
}
#if 0
static void *
filter_get_idx(struct seq_file *seq, loff_t pos)
{
int i;
struct adapter *adap = seq->private;
struct filter_info *p = adap->filters;
if (!p)
return NULL;
for (i = 0; i < adap->params.mc5.nfilters; i++, p++)
if (p->valid) {
if (!pos)
return p;
pos--;
}
return NULL;
}
static void *filter_get_nxt_idx(struct seq_file *seq, struct filter_info *p)
{
struct adapter *adap = seq->private;
struct filter_info *end = &adap->filters[adap->params.mc5.nfilters];
while (++p < end && !p->valid)
;
return p < end ? p : NULL;
}
static void *filter_seq_start(struct seq_file *seq, loff_t *pos)
{
return *pos ? filter_get_idx(seq, *pos - 1) : SEQ_START_TOKEN;
}
static void *filter_seq_next(struct seq_file *seq, void *v, loff_t *pos)
{
v = *pos ? filter_get_nxt_idx(seq, v) : filter_get_idx(seq, 0);
if (v)
++*pos;
return v;
}
static void filter_seq_stop(struct seq_file *seq, void *v)
{
}
static int filter_seq_show(struct seq_file *seq, void *v)
{
static const char *pkt_type[] = { "any", "tcp", "udp", "frag" };
if (v == SEQ_START_TOKEN)
seq_puts(seq, "index SIP DIP sport "
"dport VLAN PRI MAC type Q\n");
else {
char sip[20], dip[20];
struct filter_info *f = v;
struct adapter *adap = seq->private;
sprintf(sip, NIPQUAD_FMT "/%-2u", HIPQUAD(f->sip),
f->sip_mask ? 33 - ffs(f->sip_mask) : 0);
sprintf(dip, NIPQUAD_FMT, HIPQUAD(f->dip));
seq_printf(seq, "%5zu %18s %15s ", f - adap->filters, sip, dip);
seq_printf(seq, f->sport ? "%5u " : " * ", f->sport);
seq_printf(seq, f->dport ? "%5u " : " * ", f->dport);
seq_printf(seq, f->vlan != 0xfff ? "%4u " : " * ", f->vlan);
seq_printf(seq, f->vlan_prio == FILTER_NO_VLAN_PRI ?
" * " : "%1u/%1u ", f->vlan_prio, f->vlan_prio | 1);
if (!f->mac_vld)
seq_printf(seq, " * ");
else if (f->mac_hit)
seq_printf(seq, "%3u ", f->mac_idx);
else
seq_printf(seq, " -1 ");
seq_printf(seq, "%4s ", pkt_type[f->pkt_type]);
if (!f->pass)
seq_printf(seq, "-\n");
else if (f->rss)
seq_printf(seq, "*\n");
else
seq_printf(seq, "%1u\n", f->qset);
}
return 0;
}
static struct seq_operations filter_seq_ops = {
.start = filter_seq_start,
.next = filter_seq_next,
.stop = filter_seq_stop,
.show = filter_seq_show
};
static int filter_seq_open(struct inode *inode, struct file *file)
{
int rc = seq_open(file, &filter_seq_ops);
if (!rc) {
struct proc_dir_entry *dp = PDE(inode);
struct seq_file *seq = file->private_data;
seq->private = dp->data;
}
return rc;
}
static struct file_operations filter_seq_fops = {
.owner = THIS_MODULE,
.open = filter_seq_open,
.read = seq_read,
.llseek = seq_lseek,
.release = seq_release
};
#endif
static int
set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset)
{
uint8_t *buf;
int err = 0;
u32 aligned_offset, aligned_len, *p;
struct adapter *adapter = pi->adapter;
aligned_offset = offset & ~3;
aligned_len = (len + (offset & 3) + 3) & ~3;
if (aligned_offset != offset || aligned_len != len) {
buf = malloc(aligned_len, M_DEVBUF, M_WAITOK|M_ZERO);
if (!buf)
return (ENOMEM);
err = t3_seeprom_read(adapter, aligned_offset, (u32 *)buf);
if (!err && aligned_len > 4)
err = t3_seeprom_read(adapter,
aligned_offset + aligned_len - 4,
(u32 *)&buf[aligned_len - 4]);
if (err)
goto out;
memcpy(buf + (offset & 3), data, len);
} else
buf = (uint8_t *)(uintptr_t)data;
err = t3_seeprom_wp(adapter, 0);
if (err)
goto out;
for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
err = t3_seeprom_write(adapter, aligned_offset, *p);
aligned_offset += 4;
}
if (!err)
err = t3_seeprom_wp(adapter, 1);
out:
if (buf != data)
free(buf, M_DEVBUF);
return err;
}
static int
in_range(int val, int lo, int hi)
{
@ -1923,7 +2371,7 @@ cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data,
if (!mmd)
mmd = MDIO_DEV_PCS;
else if (mmd > MDIO_DEV_XGXS)
return -EINVAL;
return (EINVAL);
error = phy->mdio_read(sc, mid->phy_id & 0x1f, mmd,
mid->reg_num, &val);
@ -2013,7 +2461,7 @@ cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data,
struct ch_qset_params *t = (struct ch_qset_params *)data;
if (t->qset_idx >= SGE_QSETS)
return -EINVAL;
return (EINVAL);
if (!in_range(t->intr_lat, 0, M_NEWTIMER) ||
!in_range(t->cong_thres, 0, 255) ||
!in_range(t->txq_size[0], MIN_TXQ_ENTRIES,
@ -2026,13 +2474,13 @@ cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data,
!in_range(t->fl_size[1], MIN_FL_ENTRIES,
MAX_RX_JUMBO_BUFFERS) ||
!in_range(t->rspq_size, MIN_RSPQ_ENTRIES, MAX_RSPQ_ENTRIES))
return -EINVAL;
return (EINVAL);
if ((sc->flags & FULL_INIT_DONE) &&
(t->rspq_size >= 0 || t->fl_size[0] >= 0 ||
t->fl_size[1] >= 0 || t->txq_size[0] >= 0 ||
t->txq_size[1] >= 0 || t->txq_size[2] >= 0 ||
t->polling >= 0 || t->cong_thres >= 0))
return -EBUSY;
return (EBUSY);
q = &sc->params.sge.qset[t->qset_idx];
@ -2141,6 +2589,79 @@ cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data,
memcpy(m->mtus, sc->params.mtus, sizeof(m->mtus));
m->nmtus = NMTUS;
break;
}
case CHELSIO_SET_FILTER: {
struct ch_filter *f = (struct ch_filter *)data;
struct filter_info *p;
int ret;
if (sc->params.mc5.nfilters == 0)
return (EOPNOTSUPP);
if (!(sc->flags & FULL_INIT_DONE))
return (EAGAIN); /* can still change nfilters */
if (sc->filters == NULL)
return (ENOMEM);
if (f->filter_id >= sc->params.mc5.nfilters ||
(f->val.dip && f->mask.dip != 0xffffffff) ||
(f->val.sport && f->mask.sport != 0xffff) ||
(f->val.dport && f->mask.dport != 0xffff) ||
(f->mask.vlan && f->mask.vlan != 0xfff) ||
(f->mask.vlan_prio && f->mask.vlan_prio != 7) ||
(f->mac_addr_idx != 0xffff && f->mac_addr_idx > 15) ||
f->qset >= SGE_QSETS ||
sc->rrss_map[f->qset] >= RSS_TABLE_SIZE)
return (EINVAL);
p = &sc->filters[f->filter_id];
if (p->locked)
return (EPERM);
p->sip = f->val.sip;
p->sip_mask = f->mask.sip;
p->dip = f->val.dip;
p->sport = f->val.sport;
p->dport = f->val.dport;
p->vlan = f->mask.vlan ? f->val.vlan : 0xfff;
p->vlan_prio = f->mask.vlan_prio ? (f->val.vlan_prio & 6) :
FILTER_NO_VLAN_PRI;
p->mac_hit = f->mac_hit;
p->mac_vld = f->mac_addr_idx != 0xffff;
p->mac_idx = f->mac_addr_idx;
p->pkt_type = f->proto;
p->report_filter_id = f->want_filter_id;
p->pass = f->pass;
p->rss = f->rss;
p->qset = f->qset;
ret = set_filter(sc, f->filter_id, p);
if (ret)
return ret;
p->valid = 1;
break;
}
case CHELSIO_DEL_FILTER: {
struct ch_filter *f = (struct ch_filter *)data;
struct filter_info *p;
if (sc->params.mc5.nfilters == 0)
return (EOPNOTSUPP);
if (!(sc->flags & FULL_INIT_DONE))
return (EAGAIN); /* can still change nfilters */
if (sc->filters == NULL)
return (ENOMEM);
if (f->filter_id >= sc->params.mc5.nfilters)
return (EINVAL);
p = &sc->filters[f->filter_id];
if (p->locked)
return (EPERM);
memset(p, 0, sizeof(*p));
p->sip_mask = 0xffffffff;
p->vlan = 0xfff;
p->vlan_prio = FILTER_NO_VLAN_PRI;
p->pkt_type = 1;
return set_filter(sc, f->filter_id, p);
}
case CHELSIO_DEVUP:
if (!is_offload(sc))
@ -2199,6 +2720,8 @@ cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data,
if (!is_offload(sc))
return (EOPNOTSUPP);
if (!(sc->flags & FULL_INIT_DONE))
return (EIO); /* need MC5 */
return -t3_read_mc5_range(&sc->mc5, t->addr, 1, t->buf);
break;
}

28
sys/dev/cxgb/cxgb_offload.c
View File

@ -272,7 +272,7 @@ cxgb_ulp_iscsi_ctl(adapter_t *adapter, unsigned int req, void *data)
t3_write_reg(adapter, A_ULPRX_ISCSI_TAGMASK, uiip->tagmask);
break;
default:
ret = -EOPNOTSUPP;
ret = (EOPNOTSUPP);
}
return ret;
}
@ -315,7 +315,7 @@ cxgb_rdma_ctl(adapter_t *adapter, unsigned int req, void *data)
struct mc7 *mem;
if ((t->addr & 7) || (t->len & 7))
return -EINVAL;
return (EINVAL);
if (t->mem_id == MEM_CM)
mem = &adapter->cm;
else if (t->mem_id == MEM_PMRX)
@ -323,11 +323,11 @@ cxgb_rdma_ctl(adapter_t *adapter, unsigned int req, void *data)
else if (t->mem_id == MEM_PMTX)
mem = &adapter->pmtx;
else
return -EINVAL;
return (EINVAL);
ret = t3_mc7_bd_read(mem, t->addr/8, t->len/8, (u64 *)t->buf);
if (ret)
return ret;
return (ret);
break;
}
case RDMA_CQ_SETUP: {
@ -358,9 +358,9 @@ cxgb_rdma_ctl(adapter_t *adapter, unsigned int req, void *data)
break;
}
default:
ret = -EOPNOTSUPP;
ret = EOPNOTSUPP;
}
return ret;
return (ret);
}
static int
@ -439,7 +439,7 @@ cxgb_offload_ctl(struct toedev *tdev, unsigned int req, void *data)
case ULP_ISCSI_GET_PARAMS:
case ULP_ISCSI_SET_PARAMS:
if (!offload_running(adapter))
return -EAGAIN;
return (EAGAIN);
return cxgb_ulp_iscsi_ctl(adapter, req, data);
case RDMA_GET_PARAMS:
case RDMA_CQ_OP:
@ -448,10 +448,10 @@ cxgb_offload_ctl(struct toedev *tdev, unsigned int req, void *data)
case RDMA_CTRL_QP_SETUP:
case RDMA_GET_MEM:
if (!offload_running(adapter))
return -EAGAIN;
return (EAGAIN);
return cxgb_rdma_ctl(adapter, req, data);
default:
return -EOPNOTSUPP;
return (EOPNOTSUPP);
}
return 0;
}
@ -464,8 +464,8 @@ cxgb_offload_ctl(struct toedev *tdev, unsigned int req, void *data)
static int
rx_offload_blackhole(struct toedev *dev, struct mbuf **m, int n)
{
CH_ERR(tdev2adap(dev), "%d unexpected offload packets, first data %u\n",
n, ntohl(*mtod(m[0], uint32_t *)));
CH_ERR(tdev2adap(dev), "%d unexpected offload packets, first data 0x%x\n",
n, *mtod(m[0], uint32_t *));
while (n--)
m_freem(m[n]);
return 0;
@ -1308,7 +1308,7 @@ init_tid_tabs(struct tid_info *t, unsigned int ntids,
t->tid_tab = cxgb_alloc_mem(size);
if (!t->tid_tab)
return -ENOMEM;
return (ENOMEM);
t->stid_tab = (union listen_entry *)&t->tid_tab[ntids];
t->atid_tab = (union active_open_entry *)&t->stid_tab[nstids];
@ -1598,11 +1598,11 @@ offload_info_proc_setup(struct proc_dir_entry *dir,
struct proc_dir_entry *p;
if (!dir)
return -EINVAL;
return (EINVAL);
p = create_proc_read_entry("info", 0, dir, offload_info_read_proc, d);
if (!p)
return -ENOMEM;
return (ENOMEM);
p->owner = THIS_MODULE;
return 0;

6
sys/dev/cxgb/cxgb_offload.h
View File

@ -10,11 +10,7 @@ modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. Neither the name of the Chelsio Corporation nor the names of its
2. Neither the name of the Chelsio Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.

14
sys/dev/cxgb/cxgb_osdep.h
View File

@ -38,8 +38,13 @@ $FreeBSD$
#include <dev/mii/mii.h>
#ifdef CONFIG_DEFINED
#include <common/cxgb_version.h>
#include <cxgb_config.h>
#else
#include <dev/cxgb/common/cxgb_version.h>
#include <dev/cxgb/cxgb_config.h>
#endif
#ifndef _CXGB_OSDEP_H_
#define _CXGB_OSDEP_H_
@ -95,8 +100,16 @@ struct sge_rspq;
#define TX_MAX_SIZE (1 << 16) /* 64KB */
#define TX_MAX_SEGS 36 /* maximum supported by card */
#define TX_MAX_DESC 4 /* max descriptors per packet */
#define TX_START_MIN_DESC (TX_MAX_DESC << 2)
#if 0
#define TX_START_MAX_DESC (TX_ETH_Q_SIZE >> 2) /* maximum number of descriptors */
#endif
#define TX_START_MAX_DESC (TX_MAX_DESC << 3) /* maximum number of descriptors
* call to start used per */
#define TX_CLEAN_MAX_DESC (TX_MAX_DESC << 4) /* maximum tx descriptors
* to clean per iteration */
@ -159,6 +172,7 @@ static const int debug_flags = DBG_RX;
#define max_t(type, a, b) (type)max((a), (b))
#define net_device ifnet
#define cpu_to_be32 htobe32

109
sys/dev/cxgb/cxgb_sge.c
View File

@ -69,7 +69,7 @@ uint32_t mb_free_vec_free = 0;
int txq_fills = 0;
int collapse_mbufs = 0;
static int recycle_enable = 1;
static int bogus_imm = 0;
/*
* XXX GC
@ -292,20 +292,23 @@ sgl_len(unsigned int n)
*
* Return a packet containing the immediate data of the given response.
*/
static __inline void
get_imm_packet(adapter_t *sc, const struct rsp_desc *resp, struct mbuf *m, void *cl)
static int
get_imm_packet(adapter_t *sc, const struct rsp_desc *resp, struct mbuf *m, void *cl, uint32_t flags)
{
int len;
uint32_t flags = ntohl(resp->flags);
int len, error;
uint8_t sopeop = G_RSPD_SOP_EOP(flags);
/*
* would be a firmware bug
*/
if (sopeop == RSPQ_NSOP_NEOP || sopeop == RSPQ_SOP)
return;
len = G_RSPD_LEN(ntohl(resp->len_cq));
if (sopeop == RSPQ_NSOP_NEOP || sopeop == RSPQ_SOP) {
if (cxgb_debug)
device_printf(sc->dev, "unexpected value sopeop=%d flags=0x%x len=%din get_imm_packet\n", sopeop, flags, len);
bogus_imm++;
return (EINVAL);
}
error = 0;
switch (sopeop) {
case RSPQ_SOP_EOP:
m->m_len = m->m_pkthdr.len = len;
@ -315,7 +318,12 @@ get_imm_packet(adapter_t *sc, const struct rsp_desc *resp, struct mbuf *m, void
memcpy(cl, resp->imm_data, len);
m_iovappend(m, cl, MSIZE, len, 0);
break;
default:
bogus_imm++;
error = EINVAL;
}
return (error);
}
@ -362,8 +370,11 @@ t3_sge_prep(adapter_t *adap, struct sge_params *p)
q->polling = adap->params.rev > 0;
q->coalesce_nsecs = 5000;
if (adap->params.nports > 2)
q->coalesce_nsecs = 50000;
else
q->coalesce_nsecs = 5000;
q->rspq_size = RSPQ_Q_SIZE;
q->fl_size = FL_Q_SIZE;
q->jumbo_size = JUMBO_Q_SIZE;
@ -664,6 +675,35 @@ sge_slow_intr_handler(void *arg, int ncount)
t3_slow_intr_handler(sc);
}
/**
* sge_timer_cb - perform periodic maintenance of an SGE qset
* @data: the SGE queue set to maintain
*
* Runs periodically from a timer to perform maintenance of an SGE queue
* set. It performs two tasks:
*
* a) Cleans up any completed Tx descriptors that may still be pending.
* Normal descriptor cleanup happens when new packets are added to a Tx
* queue so this timer is relatively infrequent and does any cleanup only
* if the Tx queue has not seen any new packets in a while. We make a
* best effort attempt to reclaim descriptors, in that we don't wait
* around if we cannot get a queue's lock (which most likely is because
* someone else is queueing new packets and so will also handle the clean
* up). Since control queues use immediate data exclusively we don't
* bother cleaning them up here.
*
* b) Replenishes Rx queues that have run out due to memory shortage.
* Normally new Rx buffers are added when existing ones are consumed but
* when out of memory a queue can become empty. We try to add only a few
* buffers here, the queue will be replenished fully as these new buffers
* are used up if memory shortage has subsided.
*
* c) Return coalesced response queue credits in case a response queue is
* starved.
*
* d) Ring doorbells for T304 tunnel queues since we have seen doorbell
* fifo overflows and the FW doesn't implement any recovery scheme yet.
*/
static void
sge_timer_cb(void *arg)
{
@ -688,6 +728,17 @@ sge_timer_cb(void *arg)
break;
}
}
if (sc->params.nports > 2) {
int i;
for_each_port(sc, i) {
struct port_info *pi = &sc->port[i];
t3_write_reg(sc, A_SG_KDOORBELL,
F_SELEGRCNTX |
(FW_TUNNEL_SGEEC_START + pi->first_qset));
}
}
if (sc->open_device_map != 0)
callout_reset(&sc->sge_timer_ch, TX_RECLAIM_PERIOD, sge_timer_cb, sc);
}
@ -920,7 +971,7 @@ busdma_map_mbufs(struct mbuf **m, struct sge_txq *txq,
#endif
if (err == EFBIG) {
/* Too many segments, try to defrag */
m0 = m_defrag(m0, M_NOWAIT);
m0 = m_defrag(m0, M_DONTWAIT);
if (m0 == NULL) {
m_freem(*m);
*m = NULL;
@ -2051,6 +2102,7 @@ t3_sge_alloc_qset(adapter_t *sc, u_int id, int nports, int irq_vec_idx,
q->fl[1].size = p->jumbo_size;
q->rspq.gen = 1;
q->rspq.cidx = 0;
q->rspq.size = p->rspq_size;
q->txq[TXQ_ETH].stop_thres = nports *
@ -2211,7 +2263,7 @@ get_packet(adapter_t *adap, unsigned int drop_thres, struct sge_qset *qs,
int ret = 0;
prefetch(sd->cl);
fl->credits--;
bus_dmamap_sync(fl->entry_tag, sd->map, BUS_DMASYNC_POSTREAD);
@ -2328,7 +2380,7 @@ process_responses(adapter_t *adap, struct sge_qset *qs, int budget)
int ngathered = 0;
#ifdef DEBUG
static int last_holdoff = 0;
if (rspq->holdoff_tmr != last_holdoff) {
if (cxgb_debug && rspq->holdoff_tmr != last_holdoff) {
printf("next_holdoff=%d\n", rspq->holdoff_tmr);
last_holdoff = rspq->holdoff_tmr;
}
@ -2349,26 +2401,31 @@ process_responses(adapter_t *adap, struct sge_qset *qs, int budget)
} else if (flags & F_RSPD_IMM_DATA_VALID) {
struct mbuf *m = NULL;
if (cxgb_debug)
printf("IMM DATA VALID\n");
if (rspq->m == NULL)
rspq->m = m_gethdr(M_NOWAIT, MT_DATA);
else
m = m_gethdr(M_NOWAIT, MT_DATA);
if (rspq->m == NULL || m == NULL) {
if (cxgb_debug)
printf("IMM DATA VALID opcode=0x%x rspq->cidx=%d\n", r->rss_hdr.opcode, rspq->cidx);
if (rspq->m == NULL)
rspq->m = m_gethdr(M_DONTWAIT, MT_DATA);
else
m = m_gethdr(M_DONTWAIT, MT_DATA);
/*
* XXX revisit me
*/
if (rspq->m == NULL && m == NULL) {
rspq->next_holdoff = NOMEM_INTR_DELAY;
budget_left--;
break;
}
get_imm_packet(adap, r, rspq->m, m);
if (get_imm_packet(adap, r, rspq->m, m, flags))
goto skip;
eop = 1;
rspq->imm_data++;
} else if (r->len_cq) {
int drop_thresh = eth ? SGE_RX_DROP_THRES : 0;
if (rspq->m == NULL)
rspq->m = m_gethdr(M_NOWAIT, MT_DATA);
rspq->m = m_gethdr(M_DONTWAIT, MT_DATA);
if (rspq->m == NULL) {
log(LOG_WARNING, "failed to get mbuf for packet\n");
break;
@ -2385,7 +2442,7 @@ process_responses(adapter_t *adap, struct sge_qset *qs, int budget)
sleeping |= flags & RSPD_GTS_MASK;
handle_rsp_cntrl_info(qs, flags);
}
skip:
r++;
if (__predict_false(++rspq->cidx == rspq->size)) {
rspq->cidx = 0;
@ -2661,6 +2718,10 @@ t3_add_sysctls(adapter_t *sc)
"txq_overrun",
CTLFLAG_RD, &txq_fills,
0, "#times txq overrun");
SYSCTL_ADD_INT(ctx, children, OID_AUTO,
"bogus_imm",
CTLFLAG_RD, &bogus_imm,
0, "#times a bogus immediate response was seen");
}
/**

7
sys/dev/cxgb/sys/mvec.h
View File

@ -134,13 +134,18 @@ m_free_vec(struct mbuf *m)
mb_free_ext(m);
else
uma_zfree(zone_mbuf, m);
if (n)
n->m_flags &= ~M_PKTHDR;
return (n);
}
static __inline void
m_freem_vec(struct mbuf *m)
{
while (m != NULL)
while (m != NULL)
m = m_free_vec(m);
}

46
sys/dev/cxgb/t3b_protocol_sram-1.1.0.bin.gz.uu Normal file
View File

@ -0,0 +1,46 @@
/**************************************************************************
Copyright (c) 2007, Chelsio Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Neither the name of the Chelsio Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
$FreeBSD$
***************************************************************************/
begin 644 t3b_protocol_sram-1.1.0.bin.gz
M'XL(".):ED8``W0S8E]P<F]T;V-O;%]S<F%M+3$N,2XP+F)I;@#EECU+PT`8
MQY]<VAA*D?@R:%4(%$L4!X,5<2NZ.91^A([2*?@%3%L<%(6`XN"NLQ_A?"O%
MJ3B(DX-"$:>S=K!5J,]=J20Q@U#:#AXD>>[/O?SRSSUW:;5:7]`NLKA+$K3\
M&I9_J'U6DG+53LRON[0/L$1(\,J70@/G>[*-N;B;3P&R(MU0&#L*Y4MA2V@%
M(,J*K`:-1W0;\@?UGO`UKDT,C(6B2V-IB\P`\F&1+B8&ZM\;!?R^AA$/:$?0
M/R2T!LG7U)+`(=P:RP(HNJP27(;,GCUQ>N%+V21*!,@:5O-V6VN43;D4.9YW
M:RQD<KZ0AT\_%R'W3[J8]/C'BP2@=<O'\('SIF`SJO/QN`<-:EY5(9%+N>9H
M:G6!XLG?;$85L175._XQ171*!?$18U^S=VC7S('OD?ZMX9HDCZ#$.$S!6:9]
MRX5;\^HR<ISS>)7.C*].WU"_][WV)4A[OUV*WP_[^'`9*'K%^WVATJE!T3'[
MYA_R/?OY&&1B&BSZ^'`OQOSEQTC#&=GK1?[^>7^FF:DSN//PL120(4P!OK^\
M.,F-0?)A_A(5J)>O$V_MEQ\.=T7NLX(C.O:;CP5H-:SJD!CU>RIK6O_/MX#_
6EYJ:)(M`PS_MK-?3[6^9;',3!`H`````
`
end

46
sys/dev/cxgb/t3b_tp_eeprom-1.1.0.bin.gz.uu Normal file
View File

@ -0,0 +1,46 @@
/**************************************************************************
Copyright (c) 2007, Chelsio Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Neither the name of the Chelsio Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
$FreeBSD$
***************************************************************************/
begin 644 t3b_tp_eeprom-1.1.0.bin.gz
M'XL(".):ED8``W0S8E]T<%]E97!R;VTM,2XQ+C`N8FEN`-V5,4O#0!3'_[FK
M[;5634&PZ(&I%8VBT(J@A5J#=7`JW43H$!W$T8\0+8@.@DXBN+4(^0#N410<
M'(I?0'%0W%W<O*MI(@41(77P$=Z1X\][O[R\=P=%@32*3XN[:\9='7?])X+B
MY)CU3&<;W3!,S@#M<SMB_2%#>D*WGIH,JR9?,7(**GP[#=-G8'0N3+#+8#PD
M&=A(\`S5*5WX['445H(W=RKQ1@HOH>!2_%P'71?_`HZ"`<`P<JG@4_PL$-T?
MPJP:L]<(ZP/&K0PVQ'XXD!36CG!+!+$PR=[*.4O*EJMOV&9>K9YY$4*2(2O\
M28+[=>@F4`$%OOV>X4A&T.);,&0*:8H,"M0WB5G@U&,H$NG?W#I<(2)?+73M
M>0Q&<Q%U42J,7>YWH"==04GT(IU@$G(=C],`#SR%+ZAOVEJ>U_P4S@W/]9=+
MK.TS\6V$(!A>S8696KXE*)*&%A9_BX'3'/,R]UB=9BA\9<A`'2P#=E(Y[9,'
MI)@+3;9$YQC:!45RC_.ALA.UE^E!KYA-T7O;6JN1_XK!`2-B+J+'\P>'=WH$
M;4:;S]$NOHL0'*278G2=8,:[NZ1`52F1,]XQAM:]V3J.,F6A31M5;?C]8O$#
(X@X'9$0(````
`
end

482
sys/dev/cxgb/t3fw-4.1.0.bin.gz.uu
View File

@ -1,482 +0,0 @@
/**************************************************************************
Copyright (c) 2007, Chelsio Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Neither the name of the Chelsio Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
$FreeBSD$
***************************************************************************/
begin 644 t3fw-4.1.0.bin.gz
M'XL("$@Q:T8``W0S9G<M-"XQ+C`N8FEN`.R\"UP3U]HO/)D$DDPFY$+`@!"2
M$&!RCUAOK;74NFM;[5ML:S>[=K=L$ZRV6FUKJU4KB$##/2!B`@206B]X`VJM
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MMOKCR59__'7>_U?Q/_+HB[HHYFL:3)4:^*(-XDO]]#Y;`?EU/6!S4($HYN!9
M-?;,94AO56,O[8*\W_AYJ>D:Q-']8-2M00R3,`RR40$0$B"D85A8%\-@7=L_
MN_HP/(]!C=)@%"&+#;U/QK!%+!W`G"S3_X+*J"!P,`&&_F-B"$I_'K8@"15'
M0.`EL(\8"8'+ML7#`ME>V;!N#%$A()G/&8;IAM##9U!MOV!\!H2`095!W_A<
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`
end

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/**************************************************************************
Copyright (c) 2007, Chelsio Inc.
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions and the following disclaimer.
2. Neither the name of the Chelsio Corporation nor the names of its
contributors may be used to endorse or promote products derived from
this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
$FreeBSD$
***************************************************************************/
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*%P!M0DW?O%L`````
`
end

24
sys/modules/cxgb/Makefile
View File

@ -15,12 +15,28 @@ CFLAGS+= -DCONFIG_CHELSIO_T3_CORE -g -DCONFIG_DEFINED -DDEFAULT_JUMBO -I${CXGB}
.if ${MACHINE_ARCH} != "ia64"
# ld is broken on ia64
t3fw-4.1.0.bin: ${CXGB}/t3fw-4.1.0.bin.gz.uu
uudecode -p < ${CXGB}/t3fw-4.1.0.bin.gz.uu \
t3fw-4.5.0.bin: ${CXGB}/t3fw-4.5.0.bin.gz.uu
uudecode -p < ${CXGB}/t3fw-4.5.0.bin.gz.uu \
| gzip -dc > ${.TARGET}
FIRMWS= t3fw-4.1.0.bin:t3fw410
CLEANFILES+= t3fw-4.1.0.bin
FIRMWS= t3fw-4.5.0.bin:t3fw450
CLEANFILES+= t3fw-4.5.0.bin
t3b_protocol_sram-1.1.0.bin: ${CXGB}/t3b_protocol_sram-1.1.0.bin.gz.uu
uudecode -p < ${CXGB}/t3b_protocol_sram-1.1.0.bin.gz.uu \
| gzip -dc > ${.TARGET}
FIRMWS+= t3b_protocol_sram-1.1.0.bin:t3bps110
CLEANFILES+= t3b_protocol_sram-1.1.0.bin
t3b_tp_eeprom-1.1.0.bin: ${CXGB}/t3b_tp_eeprom-1.1.0.bin.gz.uu
uudecode -p < ${CXGB}/t3b_tp_eeprom-1.1.0.bin.gz.uu \
| gzip -dc > ${.TARGET}
FIRMWS+= t3b_tp_eeprom-1.1.0.bin:t3btpe110
CLEANFILES+= t3b_tp_eeprom-1.1.0.bin
.endif