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MFC r271394, r271398:

Browse Source 
Add more register values to armreg.h and remove CPU_CONTROL_32BP_ENABLE
  from asm.h as they were already defined in armreg.h.

  Unify interrupts bit definition and usage. While here remove PSR_C_bit.
This commit is contained in:
Ian Lepore 2015-02-12 03:50:33 +00:00
parent ccf8029fb7
commit b89d606a31
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/stable/10/; revision=278613
28 changed files with 116 additions and 86 deletions
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19
sys/arm/arm/cpufunc_asm_sheeva.S
View File

@ -29,6 +29,7 @@
* SUCH DAMAGE.
*/
#include <machine/armreg.h>
#include <machine/asm.h>
__FBSDID("$FreeBSD$");
@ -42,7 +43,7 @@ __FBSDID("$FreeBSD$");
ENTRY(sheeva_setttb)
/* Disable irqs */
mrs r2, cpsr
orr r3, r2, #I32_bit | F32_bit
orr r3, r2, #PSR_I | PSR_F
msr cpsr_c, r3
mov r1, #0
@ -87,7 +88,7 @@ ENTRY(sheeva_dcache_wbinv_range)
add r3, r0, ip
sub r2, r3, #1
/* Disable irqs */
orr r3, lr, #I32_bit | F32_bit
orr r3, lr, #PSR_I | PSR_F
msr cpsr_c, r3
mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */
mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */
@ -130,7 +131,7 @@ ENTRY(sheeva_idcache_wbinv_range)
add r3, r0, ip
sub r2, r3, #1
/* Disable irqs */
orr r3, lr, #I32_bit | F32_bit
orr r3, lr, #PSR_I | PSR_F
msr cpsr_c, r3
mcr p15, 5, r0, c15, c15, 0 /* Clean and inv zone start address */
mcr p15, 5, r2, c15, c15, 1 /* Clean and inv zone end address */
@ -182,7 +183,7 @@ ENTRY(sheeva_dcache_inv_range)
add r3, r0, ip
sub r2, r3, #1
/* Disable irqs */
orr r3, lr, #I32_bit | F32_bit
orr r3, lr, #PSR_I | PSR_F
msr cpsr_c, r3
mcr p15, 5, r0, c15, c14, 0 /* Inv zone start address */
mcr p15, 5, r2, c15, c14, 1 /* Inv zone end address */
@ -225,7 +226,7 @@ ENTRY(sheeva_dcache_wb_range)
add r3, r0, ip
sub r2, r3, #1
/* Disable irqs */
orr r3, lr, #I32_bit | F32_bit
orr r3, lr, #PSR_I | PSR_F
msr cpsr_c, r3
mcr p15, 5, r0, c15, c13, 0 /* Clean zone start address */
mcr p15, 5, r2, c15, c13, 1 /* Clean zone end address */
@ -268,7 +269,7 @@ ENTRY(sheeva_l2cache_wbinv_range)
add r3, r0, ip
sub r2, r3, #1
/* Disable irqs */
orr r3, lr, #I32_bit | F32_bit
orr r3, lr, #PSR_I | PSR_F
msr cpsr_c, r3
mcr p15, 1, r0, c15, c9, 4 /* Clean L2 zone start address */
mcr p15, 1, r2, c15, c9, 5 /* Clean L2 zone end address */
@ -313,7 +314,7 @@ ENTRY(sheeva_l2cache_inv_range)
add r3, r0, ip
sub r2, r3, #1
/* Disable irqs */
orr r3, lr, #I32_bit | F32_bit
orr r3, lr, #PSR_I | PSR_F
msr cpsr_c, r3
mcr p15, 1, r0, c15, c11, 4 /* Inv L2 zone start address */
mcr p15, 1, r2, c15, c11, 5 /* Inv L2 zone end address */
@ -356,7 +357,7 @@ ENTRY(sheeva_l2cache_wb_range)
add r3, r0, ip
sub r2, r3, #1
/* Disable irqs */
orr r3, lr, #I32_bit | F32_bit
orr r3, lr, #PSR_I | PSR_F
msr cpsr_c, r3
mcr p15, 1, r0, c15, c9, 4 /* Clean L2 zone start address */
mcr p15, 1, r2, c15, c9, 5 /* Clean L2 zone end address */
@ -379,7 +380,7 @@ END(sheeva_l2cache_wb_range)
ENTRY(sheeva_l2cache_wbinv_all)
/* Disable irqs */
mrs r1, cpsr
orr r2, r1, #I32_bit | F32_bit
orr r2, r1, #PSR_I | PSR_F
msr cpsr_c, r2
mov r0, #0

6
sys/arm/arm/cpufunc_asm_xscale.S
View File

@ -71,7 +71,7 @@
*
* XScale assembly functions for CPU / MMU / TLB specific operations
*/
#include <machine/armreg.h>
#include <machine/asm.h>
__FBSDID("$FreeBSD$");
@ -135,7 +135,7 @@ END(xscale_control)
ENTRY(xscale_setttb)
#ifdef CACHE_CLEAN_BLOCK_INTR
mrs r3, cpsr
orr r1, r3, #(I32_bit | F32_bit)
orr r1, r3, #(PSR_I | PSR_F)
msr cpsr_fsxc, r1
#else
ldr r3, .Lblock_userspace_access
@ -267,7 +267,7 @@ _C_LABEL(xscale_minidata_clean_size):
#ifdef CACHE_CLEAN_BLOCK_INTR
#define XSCALE_CACHE_CLEAN_BLOCK \
mrs r3, cpsr ; \
orr r0, r3, #(I32_bit | F32_bit) ; \
orr r0, r3, #(PSR_I | PSR_F) ; \
msr cpsr_fsxc, r0
#define XSCALE_CACHE_CLEAN_UNBLOCK \

5
sys/arm/arm/cpufunc_asm_xscale_c3.S
View File

@ -73,6 +73,7 @@
* XScale core 3 assembly functions for CPU / MMU / TLB specific operations
*/
#include <machine/armreg.h>
#include <machine/asm.h>
__FBSDID("$FreeBSD$");
@ -122,7 +123,7 @@ __FBSDID("$FreeBSD$");
#define XSCALE_CACHE_CLEAN_BLOCK \
stmfd sp!, {r4} ; \
mrs r4, cpsr ; \
orr r0, r4, #(I32_bit | F32_bit) ; \
orr r0, r4, #(PSR_I | PSR_F) ; \
msr cpsr_fsxc, r0
#define XSCALE_CACHE_CLEAN_UNBLOCK \
@ -349,7 +350,7 @@ END(xscalec3_l2cache_flush_rng)
ENTRY(xscalec3_setttb)
#ifdef CACHE_CLEAN_BLOCK_INTR
mrs r3, cpsr
orr r1, r3, #(I32_bit | F32_bit)
orr r1, r3, #(PSR_I | PSR_F)
msr cpsr_fsxc, r1
#else
ldr r3, .Lblock_userspace_access

8
sys/arm/arm/exception.S
View File

@ -244,12 +244,12 @@ __FBSDID("$FreeBSD$");
#define DO_AST \
ldr r0, [sp] /* Get the SPSR from stack */ ;\
mrs r4, cpsr /* save CPSR */ ;\
orr r1, r4, #(I32_bit|F32_bit) ;\
orr r1, r4, #(PSR_I|PSR_F) ;\
msr cpsr_c, r1 /* Disable interrupts */ ;\
and r0, r0, #(PSR_MODE) /* Returning to USR mode? */ ;\
teq r0, #(PSR_USR32_MODE) ;\
bne 2f /* Nope, get out now */ ;\
bic r4, r4, #(I32_bit|F32_bit) ;\
bic r4, r4, #(PSR_I|PSR_F) ;\
1: GET_CURTHREAD_PTR(r5) ;\
ldr r1, [r5, #(TD_FLAGS)] ;\
and r1, r1, #(TDF_ASTPENDING|TDF_NEEDRESCHED) ;\
@ -258,7 +258,7 @@ __FBSDID("$FreeBSD$");
msr cpsr_c, r4 /* Restore interrupts */ ;\
mov r0, sp ;\
bl _C_LABEL(ast) /* ast(frame) */ ;\
orr r0, r4, #(I32_bit|F32_bit) ;\
orr r0, r4, #(PSR_I|PSR_F) ;\
msr cpsr_c, r0 ;\
b 1b ;\
2:
@ -382,7 +382,7 @@ END(irq_entry)
*/
ASENTRY_NP(fiq_entry)
mrs r8, cpsr /* FIQ handling isn't supported, */
bic r8, #(F32_bit) /* just disable FIQ and return. */
bic r8, #(PSR_F) /* just disable FIQ and return. */
msr cpsr_c, r8 /* The r8 we trash here is the */
subs pc, lr, #4 /* banked FIQ-mode r8. */
END(fiq_entry)

12
sys/arm/arm/fiq.c
View File

@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <machine/armreg.h>
#include <machine/cpufunc.h>
#include <machine/fiq.h>
#include <vm/vm.h>
@ -54,9 +55,6 @@ TAILQ_HEAD(, fiqhandler) fiqhandler_stack =
extern char *fiq_nullhandler_code;
extern uint32_t fiq_nullhandler_size;
#define IRQ_BIT I32_bit
#define FIQ_BIT F32_bit
/*
* fiq_installhandler:
*
@ -102,7 +100,7 @@ fiq_claim(struct fiqhandler *fh)
if (fh->fh_size > 0x100)
return (EFBIG);
oldirqstate = disable_interrupts(FIQ_BIT);
oldirqstate = disable_interrupts(PSR_F);
if ((ofh = TAILQ_FIRST(&fiqhandler_stack)) != NULL) {
if ((ofh->fh_flags & FH_CANPUSH) == 0) {
@ -125,7 +123,7 @@ fiq_claim(struct fiqhandler *fh)
fiq_installhandler(fh->fh_func, fh->fh_size);
/* Make sure FIQs are enabled when we return. */
oldirqstate &= ~FIQ_BIT;
oldirqstate &= ~PSR_F;
out:
restore_interrupts(oldirqstate);
@ -143,7 +141,7 @@ fiq_release(struct fiqhandler *fh)
u_int oldirqstate;
struct fiqhandler *ofh;
oldirqstate = disable_interrupts(FIQ_BIT);
oldirqstate = disable_interrupts(PSR_F);
/*
* If we are the currently active FIQ handler, then we
@ -167,7 +165,7 @@ fiq_release(struct fiqhandler *fh)
fiq_installhandler(fiq_nullhandler_code, fiq_nullhandler_size);
/* Make sure FIQs are disabled when we return. */
oldirqstate |= FIQ_BIT;
oldirqstate |= PSR_F;
}
restore_interrupts(oldirqstate);

6
sys/arm/arm/locore.S
View File

@ -106,7 +106,7 @@ ASENTRY_NP(_start)
/* Make sure interrupts are disabled. */
mrs r7, cpsr
orr r7, r7, #(I32_bit|F32_bit)
orr r7, r7, #(PSR_I | PSR_F)
msr cpsr_c, r7
#if defined (FLASHADDR) && defined(LOADERRAMADDR)
@ -369,7 +369,7 @@ ASENTRY_NP(mpentry)
/* Make sure interrupts are disabled. */
mrs r7, cpsr
orr r7, r7, #(I32_bit|F32_bit)
orr r7, r7, #(PSR_I | PSR_F)
msr cpsr_c, r7
/* Disable MMU. It should be disabled already, but make sure. */
@ -447,7 +447,7 @@ ENTRY_NP(cpu_halt)
mrs r2, cpsr
bic r2, r2, #(PSR_MODE)
orr r2, r2, #(PSR_SVC32_MODE)
orr r2, r2, #(I32_bit | F32_bit)
orr r2, r2, #(PSR_I | PSR_F)
msr cpsr_fsxc, r2
ldr r4, .Lcpu_reset_address

4
sys/arm/arm/machdep.c
View File

@ -619,7 +619,7 @@ spinlock_enter(void)
td = curthread;
if (td->td_md.md_spinlock_count == 0) {
cspr = disable_interrupts(I32_bit | F32_bit);
cspr = disable_interrupts(PSR_I | PSR_F);
td->td_md.md_spinlock_count = 1;
td->td_md.md_saved_cspr = cspr;
} else
@ -746,7 +746,7 @@ sys_sigreturn(td, uap)
*/
spsr = uc.uc_mcontext.__gregs[_REG_CPSR];
if ((spsr & PSR_MODE) != PSR_USR32_MODE ||
(spsr & (I32_bit | F32_bit)) != 0)
(spsr & (PSR_I | PSR_F)) != 0)
return (EINVAL);
/* Restore register context. */
set_mcontext(td, &uc.uc_mcontext);

3
sys/arm/arm/mp_machdep.c
View File

@ -43,6 +43,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_kern.h>
#include <vm/pmap.h>
#include <machine/armreg.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
#include <machine/smp.h>
@ -236,7 +237,7 @@ init_secondary(int cpu)
for (int i = start; i <= end; i++)
arm_unmask_irq(i);
enable_interrupts(I32_bit);
enable_interrupts(PSR_I);
loop_counter = 0;
while (smp_started == 0) {

26
sys/arm/arm/trap.c
View File

@ -241,10 +241,10 @@ data_abort_handler(struct trapframe *tf)
pcb = td->td_pcb;
/* Re-enable interrupts if they were enabled previously */
if (td->td_md.md_spinlock_count == 0) {
if (__predict_true(tf->tf_spsr & I32_bit) == 0)
enable_interrupts(I32_bit);
if (__predict_true(tf->tf_spsr & F32_bit) == 0)
enable_interrupts(F32_bit);
if (__predict_true(tf->tf_spsr & PSR_I) == 0)
enable_interrupts(PSR_I);
if (__predict_true(tf->tf_spsr & PSR_F) == 0)
enable_interrupts(PSR_F);
}
@ -446,7 +446,7 @@ dab_fatal(struct trapframe *tf, u_int fsr, u_int far, struct thread *td,
mode = TRAP_USERMODE(tf) ? "user" : "kernel";
disable_interrupts(I32_bit|F32_bit);
disable_interrupts(PSR_I|PSR_F);
if (td != NULL) {
printf("Fatal %s mode data abort: '%s'\n", mode,
data_aborts[fsr & FAULT_TYPE_MASK].desc);
@ -656,10 +656,10 @@ prefetch_abort_handler(struct trapframe *tf)
}
fault_pc = tf->tf_pc;
if (td->td_md.md_spinlock_count == 0) {
if (__predict_true(tf->tf_spsr & I32_bit) == 0)
enable_interrupts(I32_bit);
if (__predict_true(tf->tf_spsr & F32_bit) == 0)
enable_interrupts(F32_bit);
if (__predict_true(tf->tf_spsr & PSR_I) == 0)
enable_interrupts(PSR_I);
if (__predict_true(tf->tf_spsr & PSR_F) == 0)
enable_interrupts(PSR_F);
}
/* Prefetch aborts cannot happen in kernel mode */
@ -864,10 +864,10 @@ swi_handler(struct trapframe *frame)
* be safe to enable them, but check anyway.
*/
if (td->td_md.md_spinlock_count == 0) {
if (__predict_true(frame->tf_spsr & I32_bit) == 0)
enable_interrupts(I32_bit);
if (__predict_true(frame->tf_spsr & F32_bit) == 0)
enable_interrupts(F32_bit);
if (__predict_true(frame->tf_spsr & PSR_I) == 0)
enable_interrupts(PSR_I);
if (__predict_true(frame->tf_spsr & PSR_F) == 0)
enable_interrupts(PSR_F);
}
syscall(td, frame);

7
sys/arm/arm/undefined.c
View File

@ -69,6 +69,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/vm_extern.h>
#include <machine/armreg.h>
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/frame.h>
@ -180,8 +181,10 @@ undefinedinstruction(struct trapframe *frame)
ksiginfo_t ksi;
/* Enable interrupts if they were enabled before the exception. */
if (!(frame->tf_spsr & I32_bit))
enable_interrupts(I32_bit|F32_bit);
if (__predict_true(frame->tf_spsr & PSR_I) == 0)
enable_interrupts(PSR_I);
if (__predict_true(frame->tf_spsr & PSR_F) == 0)
enable_interrupts(PSR_F);
PCPU_INC(cnt.v_trap);

8
sys/arm/arm/vm_machdep.c
View File

@ -157,7 +157,7 @@ cpu_fork(register struct thread *td1, register struct proc *p2,
sf->sf_r4 = (u_int)fork_return;
sf->sf_r5 = (u_int)td2;
sf->sf_pc = (u_int)fork_trampoline;
tf->tf_spsr &= ~PSR_C_bit;
tf->tf_spsr &= ~PSR_C;
tf->tf_r0 = 0;
tf->tf_r1 = 0;
pcb2->un_32.pcb32_sp = (u_int)sf;
@ -327,7 +327,7 @@ cpu_set_syscall_retval(struct thread *td, int error)
frame->tf_r0 = td->td_retval[0];
frame->tf_r1 = td->td_retval[1];
}
frame->tf_spsr &= ~PSR_C_bit; /* carry bit */
frame->tf_spsr &= ~PSR_C; /* carry bit */
break;
case ERESTART:
/*
@ -340,7 +340,7 @@ cpu_set_syscall_retval(struct thread *td, int error)
break;
default:
frame->tf_r0 = error;
frame->tf_spsr |= PSR_C_bit; /* carry bit */
frame->tf_spsr |= PSR_C; /* carry bit */
break;
}
}
@ -365,7 +365,7 @@ cpu_set_upcall(struct thread *td, struct thread *td0)
sf->sf_r4 = (u_int)fork_return;
sf->sf_r5 = (u_int)td;
sf->sf_pc = (u_int)fork_trampoline;
tf->tf_spsr &= ~PSR_C_bit;
tf->tf_spsr &= ~PSR_C;
tf->tf_r0 = 0;
td->td_pcb->un_32.pcb32_sp = (u_int)sf;
KASSERT((td->td_pcb->un_32.pcb32_sp & 7) == 0,

3
sys/arm/at91/at91.c
View File

@ -42,6 +42,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_page.h>
#include <vm/vm_extern.h>
#include <machine/armreg.h>
#define _ARM32_BUS_DMA_PRIVATE
#include <machine/bus.h>
#include <machine/devmap.h>
@ -303,7 +304,7 @@ at91_attach(device_t dev)
bus_generic_probe(dev);
bus_generic_attach(dev);
enable_interrupts(I32_bit | F32_bit);
enable_interrupts(PSR_I | PSR_F);
return (0);
}

3
sys/arm/at91/at91_aic.c
View File

@ -36,6 +36,7 @@ __FBSDID("$FreeBSD$");
#include <sys/systm.h>
#include <sys/rman.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
@ -149,7 +150,7 @@ at91_aic_attach(device_t dev)
/* Disable and clear all interrupts. */
WR4(sc, IC_IDCR, 0xffffffff);
WR4(sc, IC_ICCR, 0xffffffff);
enable_interrupts(I32_bit | F32_bit);
enable_interrupts(PSR_I | PSR_F);
return (err);
}

3
sys/arm/cavium/cns11xx/econa.c
View File

@ -42,6 +42,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_extern.h>
#define _ARM32_BUS_DMA_PRIVATE
#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/intr.h>
#include <machine/resource.h>
@ -508,7 +509,7 @@ econa_attach(device_t dev)
bus_generic_probe(dev);
bus_generic_attach(dev);
enable_interrupts(I32_bit | F32_bit);
enable_interrupts(PSR_I | PSR_F);
return (0);
}

40
sys/arm/include/armreg.h
View File

@ -44,21 +44,29 @@
#define INSN_SIZE 4
#define INSN_COND_MASK 0xf0000000 /* Condition mask */
#define PSR_MODE 0x0000001f /* mode mask */
#define PSR_USR26_MODE 0x00000000
#define PSR_FIQ26_MODE 0x00000001
#define PSR_IRQ26_MODE 0x00000002
#define PSR_SVC26_MODE 0x00000003
#define PSR_USR32_MODE 0x00000010
#define PSR_FIQ32_MODE 0x00000011
#define PSR_IRQ32_MODE 0x00000012
#define PSR_SVC32_MODE 0x00000013
#define PSR_MON32_MODE 0x00000016
#define PSR_ABT32_MODE 0x00000017
#define PSR_HYP32_MODE 0x0000001a
#define PSR_UND32_MODE 0x0000001b
#define PSR_SYS32_MODE 0x0000001f
#define PSR_32_MODE 0x00000010
#define PSR_FLAGS 0xf0000000 /* flags */
#define PSR_C_bit (1 << 29) /* carry */
#define PSR_T 0x00000020 /* Instruction set bit */
#define PSR_F 0x00000040 /* FIQ disable bit */
#define PSR_I 0x00000080 /* IRQ disable bit */
#define PSR_A 0x00000100 /* Imprecise abort bit */
#define PSR_E 0x00000200 /* Data endianess bit */
#define PSR_GE 0x000f0000 /* Greater than or equal to bits */
#define PSR_J 0x01000000 /* Java bit */
#define PSR_Q 0x08000000 /* Sticky overflow bit */
#define PSR_V 0x10000000 /* Overflow bit */
#define PSR_C 0x20000000 /* Carry bit */
#define PSR_Z 0x40000000 /* Zero bit */
#define PSR_N 0x80000000 /* Negative bit */
#define PSR_FLAGS 0xf0000000 /* Flags mask. */
/* The high-order byte is always the implementor */
#define CPU_ID_IMPLEMENTOR_MASK 0xff000000
@ -235,16 +243,23 @@
#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */
#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */
#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */
#define CPU_CONTROL_SW_ENABLE 0x00000400 /* SW: SWP instruction enable */
#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */
#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */
#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */
#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */
#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */
#define CPU_CONTROL_HAF_ENABLE 0x00020000 /* HA: Hardware Access Flag Enable */
#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */
#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */
#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */
#define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */
#define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */
#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */
#define CPU_CONTROL_AF_ENABLE 0x20000000 /* Access Flag enable */
#define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */
#define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: TEX Remap*/
#define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access Flag enable */
#define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */
#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE
@ -361,6 +376,15 @@
#define FAULT_EXTERNAL 0x400 /* External abort (armv6+) */
#define FAULT_WNR 0x800 /* Write-not-Read access (armv6+) */
/* Fault status register definitions - v6+ */
#define FSR_STATUS_TO_IDX(fsr) (((fsr) & 0xF) | \
(((fsr) & (1 << 10)>> (10 - 4))))
#define FSR_LPAE (1 << 9) /* LPAE indicator */
#define FSR_WNR (1 << 11) /* Write-not-Read access */
#define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/
#define FSR_CM (1 << 13) /* Cache maintenance fault */
/*
* Address of the vector page, low and high versions.
*/

6
sys/arm/include/asm.h
View File

@ -43,12 +43,6 @@
#define _C_LABEL(x) x
#define _ASM_LABEL(x) x
#define I32_bit (1 << 7) /* IRQ disable */
#define F32_bit (1 << 6) /* FIQ disable */
#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */
#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */
#ifndef _ALIGN_TEXT
# define _ALIGN_TEXT .align 0
#endif

10
sys/arm/include/atomic.h
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@ -40,6 +40,7 @@
#define _MACHINE_ATOMIC_H_
#include <sys/types.h>
#include <machine/armreg.h>
#ifndef _KERNEL
#include <machine/sysarch.h>
@ -67,12 +68,7 @@
#define wmb() dmb()
#define rmb() dmb()
#ifndef I32_bit
#define I32_bit (1 << 7) /* IRQ disable */
#endif
#ifndef F32_bit
#define F32_bit (1 << 6) /* FIQ disable */
#endif
/*
* It would be nice to use _HAVE_ARMv6_INSTRUCTIONS from machine/asm.h
@ -702,7 +698,7 @@ atomic_store_rel_long(volatile u_long *p, u_long v)
"orr %1, %0, %2;" \
"msr cpsr_fsxc, %1;" \
: "=r" (cpsr_save), "=r" (tmp) \
: "I" (I32_bit | F32_bit) \
: "I" (PSR_I | PSR_F) \
: "cc" ); \
(expr); \
__asm __volatile( \

3
sys/arm/s3c2xx0/s3c24x0.c
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@ -43,6 +43,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm.h>
#include <vm/pmap.h>
#include <machine/armreg.h>
#include <machine/cpu.h>
#include <machine/bus.h>
@ -638,7 +639,7 @@ s3c24x0_clock_freq(struct s3c2xx0_softc *sc)
void
cpu_reset(void)
{
(void) disable_interrupts(I32_bit|F32_bit);
(void) disable_interrupts(PSR_I|PSR_F);
bus_space_write_4(&s3c2xx0_bs_tag, s3c2xx0_softc->sc_wdt_ioh, WDT_WTCON,
WTCON_ENABLE | WTCON_CLKSEL_16 | WTCON_ENRST);

2
sys/arm/xscale/i80321/i80321_intr.h
View File

@ -106,7 +106,7 @@ i80321_splx(int new)
hwpend = (i80321_ipending & ICU_INT_HWMASK) & ~new;
if (hwpend != 0) {
oldirqstate = disable_interrupts(I32_bit);
oldirqstate = disable_interrupts(PSR_I);
intr_enabled |= hwpend;
i80321_set_intrmask();
restore_interrupts(oldirqstate);

3
sys/arm/xscale/i80321/i80321_timer.c
View File

@ -52,6 +52,7 @@ __FBSDID("$FreeBSD$");
#include <sys/rman.h>
#include <sys/timetc.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
@ -381,7 +382,7 @@ cpu_initclocks(void)
/* Report the clock frequency. */
oldirqstate = disable_interrupts(I32_bit);
oldirqstate = disable_interrupts(PSR_I);
irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
#ifdef CPU_XSCALE_81342

3
sys/arm/xscale/i80321/iq80321.c
View File

@ -52,6 +52,7 @@ __FBSDID("$FreeBSD$");
#include <sys/module.h>
#include <sys/malloc.h>
#include <sys/rman.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/intr.h>
@ -325,7 +326,7 @@ arm_unmask_irq(uintptr_t nb)
void
cpu_reset()
{
(void) disable_interrupts(I32_bit|F32_bit);
(void) disable_interrupts(PSR_I|PSR_F);
*(__volatile uint32_t *)(IQ80321_80321_VBASE + VERDE_ATU_BASE +
ATU_PCSR) = PCSR_RIB | PCSR_RPB;
printf("Reset failed!\n");

3
sys/arm/xscale/i8134x/i81342.c
View File

@ -34,6 +34,7 @@ __FBSDID("$FreeBSD$");
#include <sys/module.h>
#define _ARM32_BUS_DMA_PRIVATE
#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/intr.h>
@ -248,7 +249,7 @@ void
cpu_reset(void)
{
disable_interrupts(I32_bit);
disable_interrupts(PSR_I);
/* XXX: Use the watchdog to reset for now */
__asm __volatile("mcr p6, 0, %0, c8, c9, 0\n"
"mcr p6, 0, %1, c7, c9, 0\n"

5
sys/arm/xscale/ixp425/ixp425.c
View File

@ -46,6 +46,7 @@ __FBSDID("$FreeBSD$");
#include <sys/module.h>
#include <sys/malloc.h>
#include <sys/rman.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/intr.h>
@ -202,7 +203,7 @@ arm_mask_irq(uintptr_t nb)
{
int i;
i = disable_interrupts(I32_bit);
i = disable_interrupts(PSR_I);
if (nb < 32) {
intr_enabled &= ~(1 << nb);
ixp425_set_intrmask();
@ -220,7 +221,7 @@ arm_unmask_irq(uintptr_t nb)
{
int i;
i = disable_interrupts(I32_bit);
i = disable_interrupts(PSR_I);
if (nb < 32) {
intr_enabled |= (1 << nb);
ixp425_set_intrmask();

3
sys/arm/xscale/ixp425/ixp425_pci.c
View File

@ -47,6 +47,7 @@ __FBSDID("$FreeBSD$");
#include <dev/pci/pcivar.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/pcb.h>
@ -70,7 +71,7 @@ extern struct ixp425_softc *ixp425_softc;
#define PCI_CSR_READ_4(sc, reg) \
bus_read_4(sc->sc_csr, reg)
#define PCI_CONF_LOCK(s) (s) = disable_interrupts(I32_bit)
#define PCI_CONF_LOCK(s) (s) = disable_interrupts(PSR_I)
#define PCI_CONF_UNLOCK(s) restore_interrupts((s))
static device_probe_t ixppcib_probe;

3
sys/arm/xscale/ixp425/ixp425_timer.c
View File

@ -46,6 +46,7 @@ __FBSDID("$FreeBSD$");
#include <sys/rman.h>
#include <sys/timetc.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
@ -175,7 +176,7 @@ cpu_initclocks(void)
/* Report the clock frequency. */
oldirqstate = disable_interrupts(I32_bit);
oldirqstate = disable_interrupts(PSR_I);
irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, IXP425_INT_TMR0,
IXP425_INT_TMR0, 1, RF_ACTIVE);

3
sys/arm/xscale/pxa/pxa_icu.c
View File

@ -33,6 +33,7 @@ __FBSDID("$FreeBSD$");
#include <sys/malloc.h>
#include <sys/rman.h>
#include <sys/timetc.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/intr.h>
@ -105,7 +106,7 @@ pxa_icu_attach(device_t dev)
pxa_icu_set_iclr(0);
/* XXX: This should move to configure_final or something. */
enable_interrupts(I32_bit|F32_bit);
enable_interrupts(PSR_I|PSR_F);
return (0);
}

3
sys/arm/xscale/pxa/pxa_timer.c
View File

@ -33,6 +33,7 @@ __FBSDID("$FreeBSD$");
#include <sys/malloc.h>
#include <sys/rman.h>
#include <sys/timetc.h>
#include <machine/armreg.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/frame.h>
@ -190,7 +191,7 @@ cpu_reset(void)
{
uint32_t val;
(void)disable_interrupts(I32_bit|F32_bit);
(void)disable_interrupts(PSR_I|PSR_F);
val = pxa_timer_get_oscr();
val += PXA_TIMER_FREQUENCY;

2
usr.bin/truss/arm-fbsd.c
View File

@ -316,7 +316,7 @@ arm_syscall_exit(struct trussinfo *trussinfo, int syscall_num __unused)
}
retval = regs.r[0];
errorp = !!(regs.r_cpsr & PSR_C_bit);
errorp = !!(regs.r_cpsr & PSR_C);
/*
* This code, while simpler than the initial versions I used, could