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riscv: T-HEAD PBMT support

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T-HEAD CPUs provide a spec-violating implementation of page-based memory
types, using PTE bits [63:59]. Add basic support for this "errata",
referred to in some places as an "extension".

Note that this change is not enough on its own, but a workaround is
needed for the bootstrap (locore) page tables as well.

Reviewed by:	jhb
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D45472
This commit is contained in:
Mitchell Horne 2024-11-21 14:12:12 -04:00
parent dfe57951f0
commit ccbe9a9f73
5 changed files with 37 additions and 0 deletions
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26
sys/riscv/include/pte.h
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@ -102,6 +102,32 @@ typedef uint64_t pn_t; /* page number */
#define PTE_MA_NC (1ul << PTE_MA_SHIFT)
#define PTE_MA_IO (2ul << PTE_MA_SHIFT)
/*
* T-HEAD Custom Memory Attribute (MA) bits [63:59].
*
* bit 59: Trustable (relating to TEE)
* bit 60: Shareable (among CPUs, not configurable)
* bit 61: Bufferable (writes to device memory)
* bit 62: Cacheable
* bit 63: Memory Ordering (1 = strongly ordered (device), 0 = default)
*
* +------+-------+------------------------------------------------------------+
* | Mode | Value | Requested Memory Attributes |
* +------+-------+------------------------------------------------------------+
* | NC | 00110 | Weakly-ordered, non-cacheable, bufferable, shareable, |
* | | | non-trustable |
* | PMA | 01110 | Weakly-ordered, cacheable, bufferable, shareable, |
* | | | non-trustable |
* | IO | 10010 | Strongly-ordered, non-cacheable, non-bufferable, |
* | | | shareable, non-trustable |
* +------+-------+------------------------------------------------------------+
*/
#define PTE_THEAD_MA_SHIFT 59
#define PTE_THEAD_MA_MASK (0x1ful << PTE_THEAD_MA_SHIFT)
#define PTE_THEAD_MA_NC (0x6ul << PTE_THEAD_MA_SHIFT)
#define PTE_THEAD_MA_NONE (0xeul << PTE_THEAD_MA_SHIFT)
#define PTE_THEAD_MA_IO (0x12ul << PTE_THEAD_MA_SHIFT)
/* Bits 63 - 54 are reserved for future use. */
#define PTE_HI_MASK 0xFFC0000000000000ULL

2
sys/riscv/include/thead.h
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@ -30,6 +30,8 @@
#ifndef _RISCV_THEAD_H_
#define _RISCV_THEAD_H_
extern bool has_errata_thead_pbmt;
void thead_setup_cache(void);
#endif /* _RISCV_THEAD_H_ */

1
sys/riscv/riscv/identcpu.c
View File

@ -470,6 +470,7 @@ handle_thead_quirks(u_int cpu, struct cpu_desc *desc)
if (cpu != 0)
return;
has_errata_thead_pbmt = true;
thead_setup_cache();
}

6
sys/riscv/riscv/pmap.c
View File

@ -156,6 +156,7 @@
#include <machine/md_var.h>
#include <machine/pcb.h>
#include <machine/sbi.h>
#include <machine/thead.h>
/*
* Boundary values for the page table page index space:
@ -867,6 +868,11 @@ pmap_bootstrap(vm_paddr_t kernstart, vm_size_t kernlen)
memattr_bits[VM_MEMATTR_UNCACHEABLE] = PTE_MA_NC;
memattr_bits[VM_MEMATTR_DEVICE] = PTE_MA_IO;
memattr_mask = PTE_MA_MASK;
} else if (has_errata_thead_pbmt) {
memattr_bits[VM_MEMATTR_PMA] = PTE_THEAD_MA_NONE;
memattr_bits[VM_MEMATTR_UNCACHEABLE] = PTE_THEAD_MA_NC;
memattr_bits[VM_MEMATTR_DEVICE] = PTE_THEAD_MA_IO;
memattr_mask = PTE_THEAD_MA_MASK;
}
/* Create a new set of pagetables to run the kernel in. */

2
sys/riscv/thead/thead.c
View File

@ -32,6 +32,8 @@
#include <machine/thead.h>
bool has_errata_thead_pbmt = false;
/* ----------------- dcache ops --------------------- */