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Begin adding support to explicitly set the current chainmask.

Browse Source 
Right now the only way to set the chainmask is to set the hardware
configured chainmask through capabilities.  This is fine for forcing
the chainmask to be something other than what the hardware is capable
of (eg to reduce TX/RX to one connected antenna) but it does change what
the HAL hardware chainmask configuration is.

For operational mode changes, it (may?) make sense to separately control
the TX/RX chainmask.

Right now it's done as part of ar5416_reset.c - ar5416UpdateChainMasks()
calculates which TX/RX chainmasks to enable based on the operating mode.
(1 for legacy and whatever is supported for 11n operation.)  But doing
this in the HAL is suboptimal - the driver needs to know the currently
configured chainmask in order to correctly enable things for each
TX descriptor.  This is currently done by overriding the chainmask
config in the ar5416 TX routines but this has to disappear - the AR9300
HAL support requires the driver to dynamically set the TX chainmask based
on the TX power and TX rate in order to meet mini-PCIe slot power
requirements.

So:

* Introduce a new HAL method to set the operational chainmask variables;
* Introduce null methods for the previous generation chipsets;
* Add new driver state to record the current chainmask separate from
  the hardware configured chainmask.

Part #2 of this will involve disabling ar5416UpdateChainMasks() and moving
it into the driver; as well as properly programming the TX chainmask
based on the currently configured HAL chainmask.

Tested:

* AR5416, STA mode - both legacy (11a/11bg) and 11n rates - verified
  that AR_SELFGEN_MASK (the chainmask used for self-generated frames like
  ACKs and RTSes) is correct, as well as the TX descriptor contents is
  correct.
This commit is contained in:
Adrian Chadd 2013-02-25 22:42:43 +00:00
parent 776a9ddc8c
commit d2a72d673f
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=247286
14 changed files with 49 additions and 2 deletions
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2
sys/dev/ath/ath_hal/ah.h
View File

@ -1437,6 +1437,8 @@ struct ath_hal {
HAL_STATUS __ahdecl(*ah_setQuiet)(struct ath_hal *ah, uint32_t period,
uint32_t duration, uint32_t nextStart,
HAL_QUIET_FLAG flag);
void __ahdecl(*ah_setChainMasks)(struct ath_hal *,
uint32_t, uint32_t);
/* DFS functions */
void __ahdecl(*ah_enableDfs)(struct ath_hal *ah,

1
sys/dev/ath/ath_hal/ar5210/ar5210.h
View File

@ -259,6 +259,7 @@ extern HAL_BOOL ar5210GetDiagState(struct ath_hal *ah, int request,
extern uint32_t ar5210Get11nExtBusy(struct ath_hal *);
extern HAL_BOOL ar5210GetMibCycleCounts(struct ath_hal *,
HAL_SURVEY_SAMPLE *);
extern void ar5210SetChainMasks(struct ath_hal *, uint32_t, uint32_t);
extern void ar5210EnableDfs(struct ath_hal *, HAL_PHYERR_PARAM *);
extern void ar5210GetDfsThresh(struct ath_hal *, HAL_PHYERR_PARAM *);
extern void ar5210UpdateDiagReg(struct ath_hal *ah, uint32_t val);

1
sys/dev/ath/ath_hal/ar5210/ar5210_attach.c
View File

@ -137,6 +137,7 @@ static const struct ath_hal_private ar5210hal = {{
.ah_setCoverageClass = ar5210SetCoverageClass,
.ah_get11nExtBusy = ar5210Get11nExtBusy,
.ah_getMibCycleCounts = ar5210GetMibCycleCounts,
.ah_setChainMasks = ar5210SetChainMasks,
.ah_enableDfs = ar5210EnableDfs,
.ah_getDfsThresh = ar5210GetDfsThresh,
/* XXX procRadarEvent */

6
sys/dev/ath/ath_hal/ar5210/ar5210_misc.c
View File

@ -670,6 +670,12 @@ ar5210GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)
return (AH_FALSE);
}
void
ar5210SetChainMasks(struct ath_hal *ah, uint32_t txchainmask,
uint32_t rxchainmask)
{
}
void
ar5210EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
{

2
sys/dev/ath/ath_hal/ar5211/ar5211.h
View File

@ -286,6 +286,8 @@ extern HAL_BOOL ar5211GetDiagState(struct ath_hal *ah, int request,
extern uint32_t ar5211Get11nExtBusy(struct ath_hal *);
extern HAL_BOOL ar5211GetMibCycleCounts(struct ath_hal *,
HAL_SURVEY_SAMPLE *);
extern void ar5211SetChainMasks(struct ath_hal *ah, uint32_t, uint32_t);
extern void ar5211EnableDfs(struct ath_hal *, HAL_PHYERR_PARAM *);
extern void ar5211GetDfsThresh(struct ath_hal *, HAL_PHYERR_PARAM *);

1
sys/dev/ath/ath_hal/ar5211/ar5211_attach.c
View File

@ -137,6 +137,7 @@ static const struct ath_hal_private ar5211hal = {{
.ah_setCoverageClass = ar5211SetCoverageClass,
.ah_get11nExtBusy = ar5211Get11nExtBusy,
.ah_getMibCycleCounts = ar5211GetMibCycleCounts,
.ah_setChainMasks = ar5211SetChainMasks,
.ah_enableDfs = ar5211EnableDfs,
.ah_getDfsThresh = ar5211GetDfsThresh,
/* XXX procRadarEvent */

6
sys/dev/ath/ath_hal/ar5211/ar5211_misc.c
View File

@ -710,6 +710,12 @@ ar5211GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)
return (AH_FALSE);
}
void
ar5211SetChainMasks(struct ath_hal *ah, uint32_t txchainmask,
uint32_t rxchainmask)
{
}
void
ar5211EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
{

1
sys/dev/ath/ath_hal/ar5212/ar5212.h
View File

@ -513,6 +513,7 @@ extern HAL_STATUS ar5212SetQuiet(struct ath_hal *ah, uint32_t period,
uint32_t duration, uint32_t nextStart, HAL_QUIET_FLAG flag);
extern HAL_BOOL ar5212GetMibCycleCounts(struct ath_hal *,
HAL_SURVEY_SAMPLE *);
extern void ar5212SetChainMasks(struct ath_hal *, uint32_t, uint32_t);
extern HAL_BOOL ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode,
int setChip);

1
sys/dev/ath/ath_hal/ar5212/ar5212_attach.c
View File

@ -134,6 +134,7 @@ static const struct ath_hal_private ar5212hal = {{
.ah_setCoverageClass = ar5212SetCoverageClass,
.ah_setQuiet = ar5212SetQuiet,
.ah_getMibCycleCounts = ar5212GetMibCycleCounts,
.ah_setChainMasks = ar5212SetChainMasks,
/* DFS Functions */
.ah_enableDfs = ar5212EnableDfs,

6
sys/dev/ath/ath_hal/ar5212/ar5212_misc.c
View File

@ -1413,3 +1413,9 @@ ar5212GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)
return (AH_FALSE);
}
void
ar5212SetChainMasks(struct ath_hal *ah, uint32_t tx_chainmask,
uint32_t rx_chainmask)
{
}

1
sys/dev/ath/ath_hal/ar5416/ar5416.h
View File

@ -239,6 +239,7 @@ extern HAL_BOOL ar5416SetDecompMask(struct ath_hal *, uint16_t, int);
extern void ar5416SetCoverageClass(struct ath_hal *, uint8_t, int);
extern HAL_BOOL ar5416GetMibCycleCounts(struct ath_hal *ah,
HAL_SURVEY_SAMPLE *hsample);
extern void ar5416SetChainMasks(struct ath_hal *ah, uint32_t, uint32_t);
extern uint32_t ar5416Get11nExtBusy(struct ath_hal *ah);
extern void ar5416Set11nMac2040(struct ath_hal *ah, HAL_HT_MACMODE mode);
extern HAL_HT_RXCLEAR ar5416Get11nRxClear(struct ath_hal *ah);

1
sys/dev/ath/ath_hal/ar5416/ar5416_attach.c
View File

@ -150,6 +150,7 @@ ar5416InitState(struct ath_hal_5416 *ahp5416, uint16_t devid, HAL_SOFTC sc,
ah->ah_setCoverageClass = ar5416SetCoverageClass;
ah->ah_setQuiet = ar5416SetQuiet;
ah->ah_getMibCycleCounts = ar5416GetMibCycleCounts;
ah->ah_setChainMasks = ar5416SetChainMasks;
ah->ah_resetKeyCacheEntry = ar5416ResetKeyCacheEntry;
ah->ah_setKeyCacheEntry = ar5416SetKeyCacheEntry;

14
sys/dev/ath/ath_hal/ar5416/ar5416_misc.c
View File

@ -255,6 +255,20 @@ ar5416GetMibCycleCounts(struct ath_hal *ah, HAL_SURVEY_SAMPLE *hsample)
return (good);
}
/*
* Setup the TX/RX chainmasks - this needs to be done before a call
* to the reset method as it doesn't update the hardware.
*/
void
ar5416SetChainMasks(struct ath_hal *ah, uint32_t tx_chainmask,
uint32_t rx_chainmask)
{
HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
AH5416(ah)->ah_tx_chainmask = tx_chainmask & pCap->halTxChainMask;
AH5416(ah)->ah_rx_chainmask = rx_chainmask & pCap->halRxChainMask;
}
/*
* Return approximation of extension channel busy over an time interval
* 0% (clear) -> 100% (busy)

8
sys/dev/ath/if_athvar.h
View File

@ -715,8 +715,10 @@ struct ath_softc {
u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */
u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */
uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */
int sc_txchainmask; /* currently configured TX chainmask */
int sc_rxchainmask; /* currently configured RX chainmask */
int sc_txchainmask; /* hardware TX chainmask */
int sc_rxchainmask; /* hardware RX chainmask */
int sc_cur_txchainmask; /* currently configured TX chainmask */
int sc_cur_rxchainmask; /* currently configured RX chainmask */
int sc_rts_aggr_limit; /* TX limit on RTS aggregates */
int sc_aggr_limit; /* TX limit on all aggregates */
int sc_delim_min_pad; /* Minimum delimiter count */
@ -1334,6 +1336,8 @@ void ath_intr(void *);
((*(_ah)->ah_getMibCycleCounts)((_ah), (_sample)))
#define ath_hal_get_chan_ext_busy(_ah) \
((*(_ah)->ah_get11nExtBusy)((_ah)))
#define ath_hal_setchainmasks(_ah, _txchainmask, _rxchainmask) \
((*(_ah)->ah_setChainMasks)((_ah), (_txchainmask), (_rxchainmask)))
#define ath_hal_spectral_supported(_ah) \
(ath_hal_getcapability(_ah, HAL_CAP_SPECTRAL_SCAN, 0, NULL) == HAL_OK)