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While AHCI specification tells that multi-vector MSI doesn't use global IS

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register, nVidia chipsets have different oppinion, requiring every interrupt
to be acknowledged there.

While there, add interrupt descriptions in multi-vector MSI mode.
This commit is contained in:
Alexander Motin 2010-01-10 16:05:05 +00:00
parent 5be4c0818e
commit f343c07f96
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=202011
1 changed files with 12 additions and 0 deletions
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12
sys/dev/ahci/ahci.c
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@ -570,6 +570,12 @@ ahci_setup_interrupt(device_t dev)
device_printf(dev, "unable to setup interrupt\n");
return ENXIO;
}
if (ctlr->numirqs > 1) {
bus_describe_intr(dev, ctlr->irqs[i].r_irq,
ctlr->irqs[i].handle,
ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE ?
"ch%d" : "%d", i);
}
}
return (0);
}
@ -622,8 +628,14 @@ ahci_intr_one(void *data)
int unit;
unit = irq->r_irq_rid - 1;
/* Some controllers have edge triggered IS. */
if (ctlr->quirks & AHCI_Q_EDGEIS)
ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
if ((arg = ctlr->interrupt[unit].argument))
ctlr->interrupt[unit].function(arg);
/* AHCI declares level triggered IS. */
if (!(ctlr->quirks & AHCI_Q_EDGEIS))
ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
}
static struct resource *