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This commit is contained in:
Randall Stewart 2009-10-29 21:14:10 +00:00
parent 1b4a3a93ea
commit f40c80b188
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/projects/mips/; revision=198625
35 changed files with 2290 additions and 2080 deletions
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125
sys/mips/rmi/board.c
View File

@ -41,68 +41,69 @@
#include <mips/rmi/shared_structs.h>
static int xlr_rxstn_to_txstn_map[128] = {
[0 ... 7] = TX_STN_CPU_0,
[8 ... 15] = TX_STN_CPU_1,
[16 ... 23] = TX_STN_CPU_2,
[24 ... 31] = TX_STN_CPU_3,
[32 ... 39] = TX_STN_CPU_4,
[40 ... 47] = TX_STN_CPU_5,
[48 ... 55] = TX_STN_CPU_6,
[56 ... 63] = TX_STN_CPU_7,
[64 ... 95] = TX_STN_INVALID,
[96 ... 103] = TX_STN_GMAC,
[104 ... 107] = TX_STN_DMA,
[108 ... 111] = TX_STN_INVALID,
[112 ... 113] = TX_STN_XGS_0,
[114 ... 115] = TX_STN_XGS_1,
[116 ... 119] = TX_STN_INVALID,
[120 ... 127] = TX_STN_SAE
[0...7] = TX_STN_CPU_0,
[8...15] = TX_STN_CPU_1,
[16...23] = TX_STN_CPU_2,
[24...31] = TX_STN_CPU_3,
[32...39] = TX_STN_CPU_4,
[40...47] = TX_STN_CPU_5,
[48...55] = TX_STN_CPU_6,
[56...63] = TX_STN_CPU_7,
[64...95] = TX_STN_INVALID,
[96...103] = TX_STN_GMAC,
[104...107] = TX_STN_DMA,
[108...111] = TX_STN_INVALID,
[112...113] = TX_STN_XGS_0,
[114...115] = TX_STN_XGS_1,
[116...119] = TX_STN_INVALID,
[120...127] = TX_STN_SAE
};
static int xls_rxstn_to_txstn_map[128] = {
[0 ... 7] = TX_STN_CPU_0,
[8 ... 15] = TX_STN_CPU_1,
[16 ... 23] = TX_STN_CPU_2,
[24 ... 31] = TX_STN_CPU_3,
[32 ... 63] = TX_STN_INVALID,
[64 ... 71] = TX_STN_PCIE,
[72 ... 79] = TX_STN_INVALID,
[80 ... 87] = TX_STN_GMAC1,
[88 ... 95] = TX_STN_INVALID,
[96 ... 103] = TX_STN_GMAC0,
[104 ... 107] = TX_STN_DMA,
[108 ... 111] = TX_STN_CDE,
[112 ... 119] = TX_STN_INVALID,
[120 ... 127] = TX_STN_SAE
[0...7] = TX_STN_CPU_0,
[8...15] = TX_STN_CPU_1,
[16...23] = TX_STN_CPU_2,
[24...31] = TX_STN_CPU_3,
[32...63] = TX_STN_INVALID,
[64...71] = TX_STN_PCIE,
[72...79] = TX_STN_INVALID,
[80...87] = TX_STN_GMAC1,
[88...95] = TX_STN_INVALID,
[96...103] = TX_STN_GMAC0,
[104...107] = TX_STN_DMA,
[108...111] = TX_STN_CDE,
[112...119] = TX_STN_INVALID,
[120...127] = TX_STN_SAE
};
struct stn_cc *xlr_core_cc_configs[] = {&cc_table_cpu_0, &cc_table_cpu_1,
&cc_table_cpu_2, &cc_table_cpu_3,
&cc_table_cpu_4, &cc_table_cpu_5,
&cc_table_cpu_6, &cc_table_cpu_7 };
&cc_table_cpu_2, &cc_table_cpu_3,
&cc_table_cpu_4, &cc_table_cpu_5,
&cc_table_cpu_6, &cc_table_cpu_7};
struct stn_cc *xls_core_cc_configs[] = {&xls_cc_table_cpu_0, &xls_cc_table_cpu_1,
&xls_cc_table_cpu_2, &xls_cc_table_cpu_3};
struct stn_cc *xls_core_cc_configs[] = {&xls_cc_table_cpu_0, &xls_cc_table_cpu_1,
&xls_cc_table_cpu_2, &xls_cc_table_cpu_3};
struct xlr_board_info xlr_board_info;
/*
* All our knowledge of chip and board that cannot be detected by probing
* All our knowledge of chip and board that cannot be detected by probing
* at run-time goes here
*/
int xlr_board_info_setup()
int
xlr_board_info_setup()
{
if (xlr_is_xls()) {
xlr_board_info.is_xls = 1;
xlr_board_info.nr_cpus = 8;
xlr_board_info.usb = 1;
xlr_board_info.cfi =
(xlr_boot1_info.board_major_version != RMI_XLR_BOARD_ARIZONA_VIII);
(xlr_boot1_info.board_major_version != RMI_XLR_BOARD_ARIZONA_VIII);
xlr_board_info.pci_irq = 0;
xlr_board_info.credit_configs = xls_core_cc_configs;
xlr_board_info.bucket_sizes = &xls_bucket_sizes;
xlr_board_info.msgmap = xls_rxstn_to_txstn_map;
xlr_board_info.gmacports = 8;
xlr_board_info.bucket_sizes = &xls_bucket_sizes;
xlr_board_info.msgmap = xls_rxstn_to_txstn_map;
xlr_board_info.gmacports = 8;
/* network block 0 */
xlr_board_info.gmac_block[0].type = XLR_GMAC;
@ -110,13 +111,13 @@ int xlr_board_info_setup()
xlr_board_info.gmac_block[0].credit_config = &xls_cc_table_gmac0;
xlr_board_info.gmac_block[0].station_txbase = MSGRNG_STNID_GMACTX0;
xlr_board_info.gmac_block[0].station_rfr = MSGRNG_STNID_GMACRFR_0;
if (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_VI)
if (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_VI)
xlr_board_info.gmac_block[0].mode = XLR_PORT0_RGMII;
else
xlr_board_info.gmac_block[0].mode = XLR_SGMII;
xlr_board_info.gmac_block[0].baseaddr = XLR_IO_GMAC_0_OFFSET;
xlr_board_info.gmac_block[0].baseirq = PIC_GMAC_0_IRQ;
xlr_board_info.gmac_block[0].baseinst = 0;
xlr_board_info.gmac_block[0].baseaddr = XLR_IO_GMAC_0_OFFSET;
xlr_board_info.gmac_block[0].baseirq = PIC_GMAC_0_IRQ;
xlr_board_info.gmac_block[0].baseinst = 0;
/* network block 1 */
xlr_board_info.gmac_block[1].type = XLR_GMAC;
@ -124,13 +125,13 @@ int xlr_board_info_setup()
xlr_board_info.gmac_block[1].credit_config = &xls_cc_table_gmac1;
xlr_board_info.gmac_block[1].station_txbase = MSGRNG_STNID_GMAC1_TX0;
xlr_board_info.gmac_block[1].station_rfr = MSGRNG_STNID_GMAC1_FR_0;
xlr_board_info.gmac_block[1].mode = XLR_SGMII;
xlr_board_info.gmac_block[1].baseaddr = XLR_IO_GMAC_4_OFFSET;
xlr_board_info.gmac_block[1].baseirq = PIC_XGS_0_IRQ;
xlr_board_info.gmac_block[1].baseinst = 4;
xlr_board_info.gmac_block[1].mode = XLR_SGMII;
xlr_board_info.gmac_block[1].baseaddr = XLR_IO_GMAC_4_OFFSET;
xlr_board_info.gmac_block[1].baseirq = PIC_XGS_0_IRQ;
xlr_board_info.gmac_block[1].baseinst = 4;
/* network block 2 */
xlr_board_info.gmac_block[2].enabled = 0; /* disabled on XLS */
xlr_board_info.gmac_block[2].enabled = 0; /* disabled on XLS */
} else {
xlr_board_info.is_xls = 0;
xlr_board_info.nr_cpus = 32;
@ -138,9 +139,9 @@ int xlr_board_info_setup()
xlr_board_info.cfi = 1;
xlr_board_info.pci_irq = 0;
xlr_board_info.credit_configs = xlr_core_cc_configs;
xlr_board_info.bucket_sizes = &bucket_sizes;
xlr_board_info.msgmap = xlr_rxstn_to_txstn_map;
xlr_board_info.gmacports = 4;
xlr_board_info.bucket_sizes = &bucket_sizes;
xlr_board_info.msgmap = xlr_rxstn_to_txstn_map;
xlr_board_info.gmacports = 4;
/* GMAC0 */
xlr_board_info.gmac_block[0].type = XLR_GMAC;
@ -149,9 +150,9 @@ int xlr_board_info_setup()
xlr_board_info.gmac_block[0].station_txbase = MSGRNG_STNID_GMACTX0;
xlr_board_info.gmac_block[0].station_rfr = MSGRNG_STNID_GMACRFR_0;
xlr_board_info.gmac_block[0].mode = XLR_RGMII;
xlr_board_info.gmac_block[0].baseaddr = XLR_IO_GMAC_0_OFFSET;
xlr_board_info.gmac_block[0].baseirq = PIC_GMAC_0_IRQ;
xlr_board_info.gmac_block[0].baseinst = 0;
xlr_board_info.gmac_block[0].baseaddr = XLR_IO_GMAC_0_OFFSET;
xlr_board_info.gmac_block[0].baseirq = PIC_GMAC_0_IRQ;
xlr_board_info.gmac_block[0].baseinst = 0;
/* XGMAC0 */
xlr_board_info.gmac_block[1].type = XLR_XGMAC;
@ -160,9 +161,9 @@ int xlr_board_info_setup()
xlr_board_info.gmac_block[1].station_txbase = MSGRNG_STNID_XGS0_TX;
xlr_board_info.gmac_block[1].station_rfr = MSGRNG_STNID_XGS0FR;
xlr_board_info.gmac_block[1].mode = -1;
xlr_board_info.gmac_block[1].baseaddr = XLR_IO_XGMAC_0_OFFSET;
xlr_board_info.gmac_block[1].baseirq = PIC_XGS_0_IRQ;
xlr_board_info.gmac_block[1].baseinst = 4;
xlr_board_info.gmac_block[1].baseaddr = XLR_IO_XGMAC_0_OFFSET;
xlr_board_info.gmac_block[1].baseirq = PIC_XGS_0_IRQ;
xlr_board_info.gmac_block[1].baseinst = 4;
/* XGMAC1 */
xlr_board_info.gmac_block[2].type = XLR_XGMAC;
@ -171,9 +172,9 @@ int xlr_board_info_setup()
xlr_board_info.gmac_block[2].station_txbase = MSGRNG_STNID_XGS1_TX;
xlr_board_info.gmac_block[2].station_rfr = MSGRNG_STNID_XGS1FR;
xlr_board_info.gmac_block[2].mode = -1;
xlr_board_info.gmac_block[2].baseaddr = XLR_IO_XGMAC_1_OFFSET;
xlr_board_info.gmac_block[2].baseirq = PIC_XGS_1_IRQ;
xlr_board_info.gmac_block[2].baseinst = 5;
xlr_board_info.gmac_block[2].baseaddr = XLR_IO_XGMAC_1_OFFSET;
xlr_board_info.gmac_block[2].baseirq = PIC_XGS_1_IRQ;
xlr_board_info.gmac_block[2].baseinst = 5;
}
return 0;
}

57
sys/mips/rmi/board.h
View File

@ -150,7 +150,7 @@ xlr_revision_b0(void)
static __inline__ int
xlr_revision_b1(void)
{
return xlr_revision() == 0x0c0003;
return xlr_revision() == 0x0c0003;
}
static __inline__ int
@ -182,7 +182,8 @@ static __inline__ int
xlr_board_atx_iv(void)
{
return (xlr_boot1_info.board_major_version == RMI_XLR_BOARD_ARIZONA_IV)
&& (xlr_boot1_info.board_minor_version == 0); }
&& (xlr_boot1_info.board_minor_version == 0);
}
static __inline__ int
xlr_board_atx_iv_b(void)
{
@ -225,48 +226,54 @@ static __inline__ int
xlr_board_pci(void)
{
return (xlr_board_atx_iii_256() || xlr_board_atx_iii_512()
|| xlr_board_atx_v_512());
|| xlr_board_atx_v_512());
}
static __inline__ int
xlr_is_xls2xx(void)
{
uint32_t chipid = mips_rd_prid() & 0xffffff00U;
uint32_t chipid = mips_rd_prid() & 0xffffff00U;
return chipid == 0x0c8e00 || chipid == 0x0c8f00;
return chipid == 0x0c8e00 || chipid == 0x0c8f00;
}
static __inline__ int
xlr_is_xls4xx(void)
{
uint32_t chipid = mips_rd_prid() & 0xffffff00U;
uint32_t chipid = mips_rd_prid() & 0xffffff00U;
return chipid == 0x0c8800 || chipid == 0x0c8c00;
return chipid == 0x0c8800 || chipid == 0x0c8c00;
}
/* all our knowledge of chip and board that cannot be detected run-time goes here */
enum gmac_block_types { XLR_GMAC, XLR_XGMAC, XLR_SPI4};
enum gmac_block_modes { XLR_RGMII, XLR_SGMII, XLR_PORT0_RGMII };
enum gmac_block_types {
XLR_GMAC, XLR_XGMAC, XLR_SPI4
};
enum gmac_block_modes {
XLR_RGMII, XLR_SGMII, XLR_PORT0_RGMII
};
struct xlr_board_info {
int is_xls;
int nr_cpus;
int usb; /* usb enabled ? */
int cfi; /* compact flash driver for NOR? */
int usb; /* usb enabled ? */
int cfi; /* compact flash driver for NOR? */
int pci_irq;
struct stn_cc **credit_configs; /* pointer to Core station credits */
struct bucket_size *bucket_sizes; /* pointer to Core station bucket */
int *msgmap; /* mapping of message station to devices */
int gmacports; /* number of gmac ports on the board */
struct stn_cc **credit_configs; /* pointer to Core station credits */
struct bucket_size *bucket_sizes; /* pointer to Core station
* bucket */
int *msgmap; /* mapping of message station to devices */
int gmacports; /* number of gmac ports on the board */
struct xlr_gmac_block_t {
int type; /* see enum gmac_block_types */
unsigned int enabled; /* mask of ports enabled */
struct stn_cc *credit_config; /* credit configuration */
int station_txbase; /* station id for tx */
int station_rfr; /* free desc bucket */
int mode; /* see gmac_block_modes */
uint32_t baseaddr; /* IO base */
int baseirq; /* first irq for this block, the rest are in sequence */
int baseinst; /* the first rge unit for this block */
} gmac_block [3];
int type; /* see enum gmac_block_types */
unsigned int enabled; /* mask of ports enabled */
struct stn_cc *credit_config; /* credit configuration */
int station_txbase; /* station id for tx */
int station_rfr;/* free desc bucket */
int mode; /* see gmac_block_modes */
uint32_t baseaddr; /* IO base */
int baseirq; /* first irq for this block, the rest are in
* sequence */
int baseinst; /* the first rge unit for this block */
} gmac_block[3];
};
extern struct xlr_board_info xlr_board_info;

171
sys/mips/rmi/clock.c
View File

@ -28,7 +28,7 @@
*
* RMI_BSD */
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
#include <sys/param.h>
#include <sys/kernel.h>
@ -77,12 +77,13 @@ u_int32_t counter_lower_last = 0;
static int scale_factor;
static int count_scale_factor[32];
uint64_t platform_get_frequency()
uint64_t
platform_get_frequency()
{
return XLR_PIC_HZ;
}
void
void
mips_timer_early_init(uint64_t clock_hz)
{
/* Initialize clock early so that we can use DELAY sooner */
@ -94,7 +95,7 @@ mips_timer_early_init(uint64_t clock_hz)
/*
* count_compare_clockhandler:
*
* Handle the clock interrupt when count becomes equal to
* Handle the clock interrupt when count becomes equal to
* compare.
*/
void
@ -107,23 +108,21 @@ count_compare_clockhandler(struct trapframe *tf)
if (cpu == 0) {
mips_wr_compare(0);
}
else {
} else {
count_scale_factor[cpu]++;
cycles = mips_rd_count();
cycles += XLR_CPU_HZ/hz;
cycles += XLR_CPU_HZ / hz;
mips_wr_compare(cycles);
hardclock_cpu(USERMODE(tf->sr));
if (count_scale_factor[cpu] == STAT_PROF_CLOCK_SCALE_FACTOR) {
statclock(USERMODE(tf->sr));
if(profprocs != 0) {
if (profprocs != 0) {
profclock(USERMODE(tf->sr), tf->pc);
}
count_scale_factor[cpu] = 0;
}
/* If needed , handle count compare tick skew here */
/* If needed , handle count compare tick skew here */
}
critical_exit();
@ -141,18 +140,17 @@ pic_hardclockhandler(struct trapframe *tf)
hardclock(USERMODE(tf->sr), tf->pc);
if (scale_factor == STAT_PROF_CLOCK_SCALE_FACTOR) {
statclock(USERMODE(tf->sr));
if(profprocs != 0) {
if (profprocs != 0) {
profclock(USERMODE(tf->sr), tf->pc);
}
scale_factor = 0;
}
#ifdef XLR_PERFMON
if (xlr_perfmon_started)
xlr_perfmon_clockhandler();
xlr_perfmon_clockhandler();
#endif
}
else {
} else {
/* If needed , handle count compare tick skew here */
}
critical_exit();
@ -161,75 +159,77 @@ pic_hardclockhandler(struct trapframe *tf)
int
pic_timecounthandler(struct trapframe *tf)
{
return (FILTER_HANDLED);
return (FILTER_HANDLED);
}
void
platform_initclocks(void)
{
int cpu = PCPU_GET(cpuid);
void *cookie;
int cpu = PCPU_GET(cpuid);
void *cookie;
/* Note: Passing #3 as NULL ensures that clockhandler
* gets called with trapframe
*/
/* profiling/process accounting timer interrupt for non-zero cpus */
cpu_establish_hardintr("compare",
NULL,
(driver_intr_t *)count_compare_clockhandler,
NULL,
IRQ_TIMER,
INTR_TYPE_CLK|INTR_FAST, &cookie);
/*
* Note: Passing #3 as NULL ensures that clockhandler gets called
* with trapframe
*/
/* profiling/process accounting timer interrupt for non-zero cpus */
cpu_establish_hardintr("compare",
NULL,
(driver_intr_t *) count_compare_clockhandler,
NULL,
IRQ_TIMER,
INTR_TYPE_CLK | INTR_FAST, &cookie);
/* timekeeping timer interrupt for cpu 0 */
cpu_establish_hardintr("hardclk",
NULL,
(driver_intr_t *)pic_hardclockhandler,
NULL,
PIC_TIMER_7_IRQ,
INTR_TYPE_CLK|INTR_FAST,
&cookie);
/* timekeeping timer interrupt for cpu 0 */
cpu_establish_hardintr("hardclk",
NULL,
(driver_intr_t *) pic_hardclockhandler,
NULL,
PIC_TIMER_7_IRQ,
INTR_TYPE_CLK | INTR_FAST,
&cookie);
/* this is used by timecounter */
cpu_establish_hardintr("timecount",
(driver_filter_t *)pic_timecounthandler, NULL,
NULL, PIC_TIMER_6_IRQ, INTR_TYPE_CLK|INTR_FAST,
&cookie);
if (cpu == 0) {
__uint64_t maxval = XLR_PIC_HZ/hz;
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
/* this is used by timecounter */
cpu_establish_hardintr("timecount",
(driver_filter_t *) pic_timecounthandler, NULL,
NULL, PIC_TIMER_6_IRQ, INTR_TYPE_CLK | INTR_FAST,
&cookie);
stathz = hz / STAT_PROF_CLOCK_SCALE_FACTOR;
profhz = stathz;
if (cpu == 0) {
__uint64_t maxval = XLR_PIC_HZ / hz;
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
/* Setup PIC Interrupt */
stathz = hz / STAT_PROF_CLOCK_SCALE_FACTOR;
profhz = stathz;
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_0, (maxval & 0xffffffff)); /* 0x100 + 7*/
xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_1, (maxval >> 32) & 0xffffffff);/* 0x110 + 7 */
/* 0x40 + 8 */
/* reg 40 is lower bits 31-0 and holds CPU mask */
xlr_write_reg(mmio, PIC_IRT_0_TIMER_7, (1 << cpu));
/* 0x80 + 8 */
/* Reg 80 is upper bits 63-32 and holds */
/* Valid Edge Local IRQ */
xlr_write_reg(mmio, PIC_IRT_1_TIMER_7, (1<<31)|(0<<30)|(1<<6)|(PIC_TIMER_7_IRQ));
pic_update_control(1<<(8+7));
/* Setup PIC Interrupt */
xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_0, (0xffffffff & 0xffffffff));
xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_1, (0xffffffff & 0xffffffff));
xlr_write_reg(mmio, PIC_IRT_0_TIMER_6, (1 << cpu));
xlr_write_reg(mmio, PIC_IRT_1_TIMER_6, (1<<31)|(0<<30)|(1<<6)|(PIC_TIMER_6_IRQ));
pic_update_control(1<<(8+6));
mtx_unlock_spin(&xlr_pic_lock);
} else {
/* Setup count-compare interrupt for vcpu[1-31] */
mips_wr_compare((xlr_boot1_info.cpu_frequency)/hz);
}
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_0, (maxval & 0xffffffff)); /* 0x100 + 7 */
xlr_write_reg(mmio, PIC_TIMER_7_MAXVAL_1, (maxval >> 32) & 0xffffffff); /* 0x110 + 7 */
/* 0x40 + 8 */
/* reg 40 is lower bits 31-0 and holds CPU mask */
xlr_write_reg(mmio, PIC_IRT_0_TIMER_7, (1 << cpu));
/* 0x80 + 8 */
/* Reg 80 is upper bits 63-32 and holds */
/* Valid Edge Local IRQ */
xlr_write_reg(mmio, PIC_IRT_1_TIMER_7, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_7_IRQ));
pic_update_control(1 << (8 + 7));
xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_0, (0xffffffff & 0xffffffff));
xlr_write_reg(mmio, PIC_TIMER_6_MAXVAL_1, (0xffffffff & 0xffffffff));
xlr_write_reg(mmio, PIC_IRT_0_TIMER_6, (1 << cpu));
xlr_write_reg(mmio, PIC_IRT_1_TIMER_6, (1 << 31) | (0 << 30) | (1 << 6) | (PIC_TIMER_6_IRQ));
pic_update_control(1 << (8 + 6));
mtx_unlock_spin(&xlr_pic_lock);
} else {
/* Setup count-compare interrupt for vcpu[1-31] */
mips_wr_compare((xlr_boot1_info.cpu_frequency) / hz);
}
}
unsigned __attribute__((no_instrument_function))
unsigned
__attribute__((no_instrument_function))
platform_get_timecount(struct timecounter *tc __unused)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
@ -268,18 +268,21 @@ DELAY(int n)
}
static
uint64_t read_pic_counter(void)
uint64_t
read_pic_counter(void)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
uint32_t lower, upper;
uint64_t tc;
/* Pull the value of the 64 bit counter which is stored in
* PIC register 120+N and 130+N
/*
* Pull the value of the 64 bit counter which is stored in PIC
* register 120+N and 130+N
*/
upper = 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_1);
upper = 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_1);
lower = 0xffffffffU - xlr_read_reg(mmio, PIC_TIMER_6_COUNTER_0);
tc = (((uint64_t)upper << 32) | (uint64_t)lower);
return(tc);
tc = (((uint64_t) upper << 32) | (uint64_t) lower);
return (tc);
}
extern struct timecounter counter_timecounter;
@ -303,16 +306,16 @@ mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
cycles_per_tick = counter_freq / 1000;
cycles_per_hz = counter_freq / hz;
cycles_per_usec = counter_freq / (1 * 1000 * 1000);
cycles_per_sec = counter_freq ;
cycles_per_sec = counter_freq;
counter_timecounter.tc_frequency = counter_freq;
printf("hz=%d cyl_per_hz:%jd cyl_per_usec:%jd freq:%jd cyl_per_hz:%jd cyl_per_sec:%jd\n",
hz,
cycles_per_tick,
cycles_per_usec,
counter_freq,
cycles_per_hz,
cycles_per_sec
);
hz,
cycles_per_tick,
cycles_per_usec,
counter_freq,
cycles_per_hz,
cycles_per_sec
);
set_cputicker(read_pic_counter, counter_freq, 1);
}

2
sys/mips/rmi/clock.h
View File

@ -37,4 +37,4 @@ void count_compare_clockhandler(struct trapframe *);
void pic_hardclockhandler(struct trapframe *);
int pic_timecounthandler(struct trapframe *);
#endif /* _RMI_CLOCK_H_ */
#endif /* _RMI_CLOCK_H_ */

92
sys/mips/rmi/debug.h
View File

@ -33,51 +33,51 @@
#include <machine/atomic.h>
enum {
//cacheline 0
MSGRNG_INT,
MSGRNG_PIC_INT,
MSGRNG_MSG,
MSGRNG_EXIT_STATUS,
MSGRNG_MSG_CYCLES,
//cacheline 1
NETIF_TX = 8,
NETIF_RX,
NETIF_TX_COMPLETE,
NETIF_TX_COMPLETE_TX,
NETIF_RX_CYCLES,
NETIF_TX_COMPLETE_CYCLES,
NETIF_TX_CYCLES,
NETIF_TIMER_START_Q,
//NETIF_REG_FRIN,
//NETIF_INT_REG,
//cacheline 2
REPLENISH_ENTER = 16,
REPLENISH_ENTER_COUNT,
REPLENISH_CPU,
REPLENISH_FRIN,
REPLENISH_CYCLES,
NETIF_STACK_TX,
NETIF_START_Q,
NETIF_STOP_Q,
//cacheline 3
USER_MAC_START = 24,
USER_MAC_INT = 24,
USER_MAC_TX_COMPLETE,
USER_MAC_RX,
USER_MAC_POLL,
USER_MAC_TX,
USER_MAC_TX_FAIL,
USER_MAC_TX_COUNT,
USER_MAC_FRIN,
//cacheline 4
USER_MAC_TX_FAIL_GMAC_CREDITS = 32,
USER_MAC_DO_PAGE_FAULT,
USER_MAC_UPDATE_TLB,
USER_MAC_UPDATE_BIGTLB,
USER_MAC_UPDATE_TLB_PFN0,
USER_MAC_UPDATE_TLB_PFN1,
XLR_MAX_COUNTERS = 40
//cacheline 0
MSGRNG_INT,
MSGRNG_PIC_INT,
MSGRNG_MSG,
MSGRNG_EXIT_STATUS,
MSGRNG_MSG_CYCLES,
//cacheline 1
NETIF_TX = 8,
NETIF_RX,
NETIF_TX_COMPLETE,
NETIF_TX_COMPLETE_TX,
NETIF_RX_CYCLES,
NETIF_TX_COMPLETE_CYCLES,
NETIF_TX_CYCLES,
NETIF_TIMER_START_Q,
//NETIF_REG_FRIN,
//NETIF_INT_REG,
//cacheline 2
REPLENISH_ENTER = 16,
REPLENISH_ENTER_COUNT,
REPLENISH_CPU,
REPLENISH_FRIN,
REPLENISH_CYCLES,
NETIF_STACK_TX,
NETIF_START_Q,
NETIF_STOP_Q,
//cacheline 3
USER_MAC_START = 24,
USER_MAC_INT = 24,
USER_MAC_TX_COMPLETE,
USER_MAC_RX,
USER_MAC_POLL,
USER_MAC_TX,
USER_MAC_TX_FAIL,
USER_MAC_TX_COUNT,
USER_MAC_FRIN,
//cacheline 4
USER_MAC_TX_FAIL_GMAC_CREDITS = 32,
USER_MAC_DO_PAGE_FAULT,
USER_MAC_UPDATE_TLB,
USER_MAC_UPDATE_BIGTLB,
USER_MAC_UPDATE_TLB_PFN0,
USER_MAC_UPDATE_TLB_PFN1,
XLR_MAX_COUNTERS = 40
};
extern int xlr_counters[MAXCPU][XLR_MAX_COUNTERS];
extern __uint32_t msgrng_msg_cycles;
@ -88,7 +88,7 @@ extern __uint32_t msgrng_msg_cycles;
#define xlr_set_counter(x, value) atomic_set_int(&xlr_counters[PCPU_GET(cpuid)][(x)], (value))
#define xlr_get_counter(x) (&xlr_counters[0][(x)])
#else /* default mode */
#else /* default mode */
#define xlr_inc_counter(x)
#define xlr_dec_counter(x)

192
sys/mips/rmi/ehcireg.h
View File

@ -60,7 +60,7 @@
#define PCI_USBREV_1_1 0x11
#define PCI_USBREV_2_0 0x20
#define PCI_EHCI_FLADJ 0x61 /*RW Frame len adj, SOF=59488+6*fladj */
#define PCI_EHCI_FLADJ 0x61 /* RW Frame len adj, SOF=59488+6*fladj */
#define PCI_EHCI_PORTWAKECAP 0x62 /* RW Port wake caps (opt) */
@ -77,30 +77,30 @@
/*** EHCI capability registers ***/
#define EHCI_CAPLENGTH 0x00 /*RO Capability register length field */
#define EHCI_CAPLENGTH 0x00 /* RO Capability register length field */
/* reserved 0x01 */
#define EHCI_HCIVERSION 0x02 /* RO Interface version number */
#define EHCI_HCSPARAMS 0x04 /* RO Structural parameters */
#define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf)
#define EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)
#define EHCI_HCS_N_CC(x) (((x) >> 12) & 0xf) /* # of companion ctlrs */
#define EHCI_HCS_N_PCC(x) (((x) >> 8) & 0xf) /* # of ports per comp. */
#define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */
#define EHCI_HCS_N_PORTS(x) ((x) & 0xf) /* # of ports */
#define EHCI_HCS_N_CC(x) (((x) >> 12) & 0xf) /* # of companion ctlrs */
#define EHCI_HCS_N_PCC(x) (((x) >> 8) & 0xf) /* # of ports per comp. */
#define EHCI_HCS_PPC(x) ((x) & 0x10) /* port power control */
#define EHCI_HCS_N_PORTS(x) ((x) & 0xf) /* # of ports */
#define EHCI_HCCPARAMS 0x08 /* RO Capability parameters */
#define EHCI_HCC_EECP(x) (((x) >> 8) & 0xff) /* extended ports caps */
#define EHCI_HCC_IST(x) (((x) >> 4) & 0xf) /* isoc sched threshold */
#define EHCI_HCC_ASPC(x) ((x) & 0x4) /* async sched park cap */
#define EHCI_HCC_PFLF(x) ((x) & 0x2) /* prog frame list flag */
#define EHCI_HCC_64BIT(x) ((x) & 0x1) /* 64 bit address cap */
#define EHCI_HCC_EECP(x) (((x) >> 8) & 0xff) /* extended ports caps */
#define EHCI_HCC_IST(x) (((x) >> 4) & 0xf) /* isoc sched threshold */
#define EHCI_HCC_ASPC(x) ((x) & 0x4) /* async sched park cap */
#define EHCI_HCC_PFLF(x) ((x) & 0x2) /* prog frame list flag */
#define EHCI_HCC_64BIT(x) ((x) & 0x1) /* 64 bit address cap */
#define EHCI_HCSP_PORTROUTE 0x0c /*RO Companion port route description */
#define EHCI_HCSP_PORTROUTE 0x0c /* RO Companion port route description */
/* EHCI operational registers. Offset given by EHCI_CAPLENGTH register */
#define EHCI_USBCMD 0x00 /* RO, RW, WO Command register */
#define EHCI_CMD_ITC_M 0x00ff0000 /* RW interrupt threshold ctrl */
#define EHCI_CMD_ITC_M 0x00ff0000 /* RW interrupt threshold ctrl */
#define EHCI_CMD_ITC_1 0x00010000
#define EHCI_CMD_ITC_2 0x00020000
#define EHCI_CMD_ITC_4 0x00040000
@ -108,39 +108,41 @@
#define EHCI_CMD_ITC_16 0x00100000
#define EHCI_CMD_ITC_32 0x00200000
#define EHCI_CMD_ITC_64 0x00400000
#define EHCI_CMD_ASPME 0x00000800 /* RW/RO async park enable */
#define EHCI_CMD_ASPMC 0x00000300 /* RW/RO async park count */
#define EHCI_CMD_LHCR 0x00000080 /* RW light host ctrl reset */
#define EHCI_CMD_IAAD 0x00000040 /* RW intr on async adv door bell */
#define EHCI_CMD_ASE 0x00000020 /* RW async sched enable */
#define EHCI_CMD_PSE 0x00000010 /* RW periodic sched enable */
#define EHCI_CMD_FLS_M 0x0000000c /* RW/RO frame list size */
#define EHCI_CMD_FLS(x) (((x) >> 2) & 3) /* RW/RO frame list size */
#define EHCI_CMD_HCRESET 0x00000002 /* RW reset */
#define EHCI_CMD_RS 0x00000001 /* RW run/stop */
#define EHCI_CMD_ASPME 0x00000800 /* RW/RO async park enable */
#define EHCI_CMD_ASPMC 0x00000300 /* RW/RO async park count */
#define EHCI_CMD_LHCR 0x00000080 /* RW light host ctrl reset */
#define EHCI_CMD_IAAD 0x00000040 /* RW intr on async adv door
* bell */
#define EHCI_CMD_ASE 0x00000020 /* RW async sched enable */
#define EHCI_CMD_PSE 0x00000010 /* RW periodic sched enable */
#define EHCI_CMD_FLS_M 0x0000000c /* RW/RO frame list size */
#define EHCI_CMD_FLS(x) (((x) >> 2) & 3) /* RW/RO frame list size */
#define EHCI_CMD_HCRESET 0x00000002 /* RW reset */
#define EHCI_CMD_RS 0x00000001 /* RW run/stop */
#define EHCI_USBSTS 0x04 /* RO, RW, RWC Status register */
#define EHCI_STS_ASS 0x00008000 /* RO async sched status */
#define EHCI_STS_PSS 0x00004000 /* RO periodic sched status */
#define EHCI_STS_REC 0x00002000 /* RO reclamation */
#define EHCI_STS_HCH 0x00001000 /* RO host controller halted */
#define EHCI_STS_IAA 0x00000020 /* RWC interrupt on async adv */
#define EHCI_STS_HSE 0x00000010 /* RWC host system error */
#define EHCI_STS_FLR 0x00000008 /* RWC frame list rollover */
#define EHCI_STS_PCD 0x00000004 /* RWC port change detect */
#define EHCI_STS_ERRINT 0x00000002 /* RWC error interrupt */
#define EHCI_STS_INT 0x00000001 /* RWC interrupt */
#define EHCI_STS_ASS 0x00008000 /* RO async sched status */
#define EHCI_STS_PSS 0x00004000 /* RO periodic sched status */
#define EHCI_STS_REC 0x00002000 /* RO reclamation */
#define EHCI_STS_HCH 0x00001000 /* RO host controller halted */
#define EHCI_STS_IAA 0x00000020 /* RWC interrupt on async adv */
#define EHCI_STS_HSE 0x00000010 /* RWC host system error */
#define EHCI_STS_FLR 0x00000008 /* RWC frame list rollover */
#define EHCI_STS_PCD 0x00000004 /* RWC port change detect */
#define EHCI_STS_ERRINT 0x00000002 /* RWC error interrupt */
#define EHCI_STS_INT 0x00000001 /* RWC interrupt */
#define EHCI_STS_INTRS(x) ((x) & 0x3f)
#define EHCI_NORMAL_INTRS (EHCI_STS_IAA | EHCI_STS_HSE | EHCI_STS_PCD | EHCI_STS_ERRINT | EHCI_STS_INT)
#define EHCI_USBINTR 0x08 /* RW Interrupt register */
#define EHCI_INTR_IAAE 0x00000020 /* interrupt on async advance ena */
#define EHCI_INTR_HSEE 0x00000010 /* host system error ena */
#define EHCI_INTR_FLRE 0x00000008 /* frame list rollover ena */
#define EHCI_INTR_PCIE 0x00000004 /* port change ena */
#define EHCI_INTR_UEIE 0x00000002 /* USB error intr ena */
#define EHCI_INTR_UIE 0x00000001 /* USB intr ena */
#define EHCI_INTR_IAAE 0x00000020 /* interrupt on async advance
* ena */
#define EHCI_INTR_HSEE 0x00000010 /* host system error ena */
#define EHCI_INTR_FLRE 0x00000008 /* frame list rollover ena */
#define EHCI_INTR_PCIE 0x00000004 /* port change ena */
#define EHCI_INTR_UEIE 0x00000002 /* USB error intr ena */
#define EHCI_INTR_UIE 0x00000001 /* USB intr ena */
#define EHCI_FRINDEX 0x0c /* RW Frame Index register */
@ -150,30 +152,30 @@
#define EHCI_ASYNCLISTADDR 0x18 /* RW Async List Base */
#define EHCI_CONFIGFLAG 0x40 /* RW Configure Flag register */
#define EHCI_CONF_CF 0x00000001 /* RW configure flag */
#define EHCI_CONF_CF 0x00000001 /* RW configure flag */
#define EHCI_PORTSC(n) (0x40+4*(n)) /* RO, RW, RWC Port Status reg */
#define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current ena */
#define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect ena */
#define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect ena */
#define EHCI_PS_PTC 0x000f0000 /* RW port test control */
#define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */
#define EHCI_PS_PO 0x00002000 /* RW port owner */
#define EHCI_PS_PP 0x00001000 /* RW,RO port power */
#define EHCI_PS_LS 0x00000c00 /* RO line status */
#define EHCI_PORTSC(n) (0x40+4*(n)) /* RO, RW, RWC Port Status reg */
#define EHCI_PS_WKOC_E 0x00400000 /* RW wake on over current ena */
#define EHCI_PS_WKDSCNNT_E 0x00200000 /* RW wake on disconnect ena */
#define EHCI_PS_WKCNNT_E 0x00100000 /* RW wake on connect ena */
#define EHCI_PS_PTC 0x000f0000 /* RW port test control */
#define EHCI_PS_PIC 0x0000c000 /* RW port indicator control */
#define EHCI_PS_PO 0x00002000 /* RW port owner */
#define EHCI_PS_PP 0x00001000 /* RW,RO port power */
#define EHCI_PS_LS 0x00000c00 /* RO line status */
#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == 0x00000400)
#define EHCI_PS_PR 0x00000100 /* RW port reset */
#define EHCI_PS_SUSP 0x00000080 /* RW suspend */
#define EHCI_PS_FPR 0x00000040 /* RW force port resume */
#define EHCI_PS_OCC 0x00000020 /* RWC over current change */
#define EHCI_PS_OCA 0x00000010 /* RO over current active */
#define EHCI_PS_PEC 0x00000008 /* RWC port enable change */
#define EHCI_PS_PE 0x00000004 /* RW port enable */
#define EHCI_PS_CSC 0x00000002 /* RWC connect status change */
#define EHCI_PS_CS 0x00000001 /* RO connect status */
#define EHCI_PS_PR 0x00000100 /* RW port reset */
#define EHCI_PS_SUSP 0x00000080 /* RW suspend */
#define EHCI_PS_FPR 0x00000040 /* RW force port resume */
#define EHCI_PS_OCC 0x00000020 /* RWC over current change */
#define EHCI_PS_OCA 0x00000010 /* RO over current active */
#define EHCI_PS_PEC 0x00000008 /* RWC port enable change */
#define EHCI_PS_PE 0x00000004 /* RW port enable */
#define EHCI_PS_CSC 0x00000002 /* RWC connect status change */
#define EHCI_PS_CS 0x00000001 /* RO connect status */
#define EHCI_PS_CLEAR (EHCI_PS_OCC|EHCI_PS_PEC|EHCI_PS_CSC)
#define EHCI_PORT_RESET_COMPLETE 2 /* ms */
#define EHCI_PORT_RESET_COMPLETE 2 /* ms */
#define EHCI_FLALIGN_ALIGN 0x1000
@ -186,6 +188,7 @@
#endif
typedef u_int32_t ehci_link_t;
#define EHCI_LINK_TERMINATE 0x00000001
#define EHCI_LINK_TYPE(x) ((x) & 0x00000006)
#define EHCI_LINK_ITD 0x0
@ -198,24 +201,26 @@ typedef u_int32_t ehci_physaddr_t;
/* Isochronous Transfer Descriptor */
typedef struct {
ehci_link_t itd_next;
ehci_link_t itd_next;
/* XXX many more */
} ehci_itd_t;
} ehci_itd_t;
#define EHCI_ITD_ALIGN 32
/* Split Transaction Isochronous Transfer Descriptor */
typedef struct {
ehci_link_t sitd_next;
ehci_link_t sitd_next;
/* XXX many more */
} ehci_sitd_t;
} ehci_sitd_t;
#define EHCI_SITD_ALIGN 32
/* Queue Element Transfer Descriptor */
#define EHCI_QTD_NBUFFERS 5
typedef struct {
ehci_link_t qtd_next;
ehci_link_t qtd_altnext;
u_int32_t qtd_status;
ehci_link_t qtd_next;
ehci_link_t qtd_altnext;
u_int32_t qtd_status;
#define EHCI_QTD_GET_STATUS(x) (((x) >> 0) & 0xff)
#define EHCI_QTD_SET_STATUS(x) ((x) << 0)
#define EHCI_QTD_ACTIVE 0x80
@ -243,59 +248,62 @@ typedef struct {
#define EHCI_QTD_GET_TOGGLE(x) (((x) >> 31) & 0x1)
#define EHCI_QTD_SET_TOGGLE(x) ((x) << 31)
#define EHCI_QTD_TOGGLE_MASK 0x80000000
ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS];
ehci_physaddr_t qtd_buffer[EHCI_QTD_NBUFFERS];
ehci_physaddr_t qtd_buffer_hi[EHCI_QTD_NBUFFERS];
} ehci_qtd_t;
} ehci_qtd_t;
#define EHCI_QTD_ALIGN 32
/* Queue Head */
typedef struct {
ehci_link_t qh_link;
u_int32_t qh_endp;
#define EHCI_QH_GET_ADDR(x) (((x) >> 0) & 0x7f) /* endpoint addr */
ehci_link_t qh_link;
u_int32_t qh_endp;
#define EHCI_QH_GET_ADDR(x) (((x) >> 0) & 0x7f) /* endpoint addr */
#define EHCI_QH_SET_ADDR(x) (x)
#define EHCI_QH_ADDRMASK 0x0000007f
#define EHCI_QH_GET_INACT(x) (((x) >> 7) & 0x01) /* inactivate on next */
#define EHCI_QH_GET_INACT(x) (((x) >> 7) & 0x01) /* inactivate on next */
#define EHCI_QH_INACT 0x00000080
#define EHCI_QH_GET_ENDPT(x) (((x) >> 8) & 0x0f) /* endpoint no */
#define EHCI_QH_GET_ENDPT(x) (((x) >> 8) & 0x0f) /* endpoint no */
#define EHCI_QH_SET_ENDPT(x) ((x) << 8)
#define EHCI_QH_GET_EPS(x) (((x) >> 12) & 0x03) /* endpoint speed */
#define EHCI_QH_GET_EPS(x) (((x) >> 12) & 0x03) /* endpoint speed */
#define EHCI_QH_SET_EPS(x) ((x) << 12)
#define EHCI_QH_SPEED_FULL 0x0
#define EHCI_QH_SPEED_LOW 0x1
#define EHCI_QH_SPEED_HIGH 0x2
#define EHCI_QH_GET_DTC(x) (((x) >> 14) & 0x01) /* data toggle control */
#define EHCI_QH_GET_DTC(x) (((x) >> 14) & 0x01) /* data toggle control */
#define EHCI_QH_DTC 0x00004000
#define EHCI_QH_GET_HRECL(x) (((x) >> 15) & 0x01) /* head of reclamation */
#define EHCI_QH_GET_HRECL(x) (((x) >> 15) & 0x01) /* head of reclamation */
#define EHCI_QH_HRECL 0x00008000
#define EHCI_QH_GET_MPL(x) (((x) >> 16) & 0x7ff) /* max packet len */
#define EHCI_QH_GET_MPL(x) (((x) >> 16) & 0x7ff) /* max packet len */
#define EHCI_QH_SET_MPL(x) ((x) << 16)
#define EHCI_QH_MPLMASK 0x07ff0000
#define EHCI_QH_GET_CTL(x) (((x) >> 27) & 0x01) /* control endpoint */
#define EHCI_QH_GET_CTL(x) (((x) >> 27) & 0x01) /* control endpoint */
#define EHCI_QH_CTL 0x08000000
#define EHCI_QH_GET_NRL(x) (((x) >> 28) & 0x0f) /* NAK reload */
#define EHCI_QH_GET_NRL(x) (((x) >> 28) & 0x0f) /* NAK reload */
#define EHCI_QH_SET_NRL(x) ((x) << 28)
u_int32_t qh_endphub;
#define EHCI_QH_GET_SMASK(x) (((x) >> 0) & 0xff) /* intr sched mask */
u_int32_t qh_endphub;
#define EHCI_QH_GET_SMASK(x) (((x) >> 0) & 0xff) /* intr sched mask */
#define EHCI_QH_SET_SMASK(x) ((x) << 0)
#define EHCI_QH_GET_CMASK(x) (((x) >> 8) & 0xff) /* split completion mask */
#define EHCI_QH_GET_CMASK(x) (((x) >> 8) & 0xff) /* split completion mask */
#define EHCI_QH_SET_CMASK(x) ((x) << 8)
#define EHCI_QH_GET_HUBA(x) (((x) >> 16) & 0x7f) /* hub address */
#define EHCI_QH_GET_HUBA(x) (((x) >> 16) & 0x7f) /* hub address */
#define EHCI_QH_SET_HUBA(x) ((x) << 16)
#define EHCI_QH_GET_PORT(x) (((x) >> 23) & 0x7f) /* hub port */
#define EHCI_QH_GET_PORT(x) (((x) >> 23) & 0x7f) /* hub port */
#define EHCI_QH_SET_PORT(x) ((x) << 23)
#define EHCI_QH_GET_MULT(x) (((x) >> 30) & 0x03) /* pipe multiplier */
#define EHCI_QH_GET_MULT(x) (((x) >> 30) & 0x03) /* pipe multiplier */
#define EHCI_QH_SET_MULT(x) ((x) << 30)
ehci_link_t qh_curqtd;
ehci_qtd_t qh_qtd;
} ehci_qh_t;
ehci_link_t qh_curqtd;
ehci_qtd_t qh_qtd;
} ehci_qh_t;
#define EHCI_QH_ALIGN 32
/* Periodic Frame Span Traversal Node */
typedef struct {
ehci_link_t fstn_link;
ehci_link_t fstn_back;
} ehci_fstn_t;
ehci_link_t fstn_link;
ehci_link_t fstn_back;
} ehci_fstn_t;
#define EHCI_FSTN_ALIGN 32
#endif /* _DEV_PCI_EHCIREG_H_ */
#endif /* _DEV_PCI_EHCIREG_H_ */

62
sys/mips/rmi/ehcivar.h
View File

@ -39,12 +39,13 @@
typedef struct ehci_soft_qtd {
ehci_qtd_t qtd;
struct ehci_soft_qtd *nextqtd; /* mirrors nextqtd in TD */
struct ehci_soft_qtd *nextqtd; /* mirrors nextqtd in TD */
ehci_physaddr_t physaddr;
usbd_xfer_handle xfer;
LIST_ENTRY(ehci_soft_qtd) hnext;
LIST_ENTRY(ehci_soft_qtd) hnext;
u_int16_t len;
} ehci_soft_qtd_t;
} ehci_soft_qtd_t;
#define EHCI_SQTD_SIZE ((sizeof (struct ehci_soft_qtd) + EHCI_QTD_ALIGN - 1) / EHCI_QTD_ALIGN * EHCI_QTD_ALIGN)
#define EHCI_SQTD_CHUNK (EHCI_PAGE_SIZE / EHCI_SQTD_SIZE)
@ -55,14 +56,15 @@ typedef struct ehci_soft_qh {
struct ehci_soft_qtd *sqtd;
ehci_physaddr_t physaddr;
int islot; /* Interrupt list slot. */
} ehci_soft_qh_t;
} ehci_soft_qh_t;
#define EHCI_SQH_SIZE ((sizeof (struct ehci_soft_qh) + EHCI_QH_ALIGN - 1) / EHCI_QH_ALIGN * EHCI_QH_ALIGN)
#define EHCI_SQH_CHUNK (EHCI_PAGE_SIZE / EHCI_SQH_SIZE)
struct ehci_xfer {
struct usbd_xfer xfer;
struct usb_task abort_task;
LIST_ENTRY(ehci_xfer) inext; /* list of active xfers */
struct usb_task abort_task;
LIST_ENTRY(ehci_xfer) inext; /* list of active xfers */
ehci_soft_qtd_t *sqtdstart;
ehci_soft_qtd_t *sqtdend;
u_int32_t ehci_xfer_flags;
@ -70,6 +72,7 @@ struct ehci_xfer {
int isdone;
#endif
};
#define EHCI_XFER_ABORTING 0x0001 /* xfer is aborting. */
#define EHCI_XFER_ABORTWAIT 0x0002 /* abort completion is being awaited. */
@ -79,7 +82,7 @@ struct ehci_xfer {
* Information about an entry in the interrupt list.
*/
struct ehci_soft_islot {
ehci_soft_qh_t *sqh; /* Queue Head. */
ehci_soft_qh_t *sqh; /* Queue Head. */
};
#define EHCI_FRAMELIST_MAXCOUNT 1024
@ -97,7 +100,7 @@ struct ehci_soft_islot {
#define EHCI_SCFLG_LOSTINTRBUG 0x0002 /* workaround for VIA / ATI chipsets */
typedef struct ehci_softc {
struct usbd_bus sc_bus; /* base device */
struct usbd_bus sc_bus; /* base device */
int sc_flags;
bus_space_tag_t iot;
bus_space_handle_t ioh;
@ -108,15 +111,15 @@ typedef struct ehci_softc {
struct resource *io_res;
struct resource *irq_res;
#endif
u_int sc_offs; /* offset to operational regs */
u_int sc_offs; /* offset to operational regs */
char sc_vendor[32]; /* vendor string for root hub */
int sc_id_vendor; /* vendor ID for root hub */
char sc_vendor[32]; /* vendor string for root hub */
int sc_id_vendor; /* vendor ID for root hub */
u_int32_t sc_cmd; /* shadow of cmd reg during suspend */
u_int32_t sc_cmd; /* shadow of cmd reg during suspend */
#if defined(__NetBSD__) || defined(__OpenBSD__)
void *sc_powerhook; /* cookie from power hook */
void *sc_shutdownhook; /* cookie from shutdown hook */
void *sc_powerhook; /* cookie from power hook */
void *sc_shutdownhook; /* cookie from shutdown hook */
#endif
u_int sc_ncomp;
@ -127,29 +130,29 @@ typedef struct ehci_softc {
ehci_link_t *sc_flist;
u_int sc_flsize;
#ifndef __FreeBSD__
u_int sc_rand; /* XXX need proper intr scheduling */
u_int sc_rand; /* XXX need proper intr scheduling */
#endif
struct ehci_soft_islot sc_islots[EHCI_INTRQHS];
LIST_HEAD(, ehci_xfer) sc_intrhead;
LIST_HEAD(, ehci_xfer) sc_intrhead;
ehci_soft_qh_t *sc_freeqhs;
ehci_soft_qtd_t *sc_freeqtds;
int sc_noport;
u_int8_t sc_addr; /* device address */
u_int8_t sc_conf; /* device configuration */
u_int8_t sc_addr; /* device address */
u_int8_t sc_conf; /* device configuration */
usbd_xfer_handle sc_intrxfer;
char sc_isreset;
#ifdef USB_USE_SOFTINTR
char sc_softwake;
#endif /* USB_USE_SOFTINTR */
#endif /* USB_USE_SOFTINTR */
u_int32_t sc_eintrs;
ehci_soft_qh_t *sc_async_head;
SIMPLEQ_HEAD(, usbd_xfer) sc_free_xfers; /* free xfers */
SIMPLEQ_HEAD(, usbd_xfer) sc_free_xfers; /* free xfers */
struct lock sc_doorbell_lock;
@ -157,13 +160,13 @@ typedef struct ehci_softc {
usb_callout_t sc_tmo_intrlist;
#if defined(__NetBSD__) || defined(__OpenBSD__)
device_ptr_t sc_child; /* /dev/usb# device */
device_ptr_t sc_child; /* /dev/usb# device */
#endif
char sc_dying;
#if defined(__NetBSD__)
struct usb_dma_reserve sc_dma_reserve;
#endif
} ehci_softc_t;
} ehci_softc_t;
#define EREAD1(sc, a) bus_space_read_1((sc)->iot, (sc)->ioh, (a))
#define EREAD2(sc, a) bus_space_read_2((sc)->iot, (sc)->ioh, (a))
@ -178,14 +181,15 @@ typedef struct ehci_softc {
#define EOWRITE2(sc, a, x) bus_space_write_2((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a), (x))
#define EOWRITE4(sc, a, x) bus_space_write_4((sc)->iot, (sc)->ioh, (sc)->sc_offs+(a), (x))
usbd_status ehci_init(ehci_softc_t *);
int ehci_intr(void *);
int ehci_detach(ehci_softc_t *, int);
usbd_status ehci_init(ehci_softc_t *);
int ehci_intr(void *);
int ehci_detach(ehci_softc_t *, int);
#if defined(__NetBSD__) || defined(__OpenBSD__)
int ehci_activate(device_ptr_t, enum devact);
int ehci_activate(device_ptr_t, enum devact);
#endif
void ehci_power(int state, void *priv);
void ehci_shutdown(void *v);
void ehci_power(int state, void *priv);
void ehci_shutdown(void *v);
#define MS_TO_TICKS(ms) ((ms) * hz / 1000)

3
sys/mips/rmi/interrupt.h
View File

@ -39,5 +39,4 @@
#define IRQ_MSGRING 6
#define IRQ_TIMER 7
#endif /* _RMI_INTERRUPT_H_ */
#endif /* _RMI_INTERRUPT_H_ */

63
sys/mips/rmi/intr_machdep.c
View File

@ -55,40 +55,42 @@ struct mips_intrhand mips_intr_handlers[XLR_MAX_INTR];
static void
mips_mask_hard_irq(void *source)
{
uintptr_t irq = (uintptr_t)source;
uintptr_t irq = (uintptr_t) source;
write_c0_eimr64(read_c0_eimr64() & ~(1ULL<<irq));
write_c0_eimr64(read_c0_eimr64() & ~(1ULL << irq));
}
static void
mips_unmask_hard_irq(void *source)
{
uintptr_t irq = (uintptr_t)source;
uintptr_t irq = (uintptr_t) source;
write_c0_eimr64(read_c0_eimr64() | (1ULL<<irq));
write_c0_eimr64(read_c0_eimr64() | (1ULL << irq));
}
void
cpu_establish_hardintr(const char *name, driver_filter_t *filt,
void (*handler)(void*), void *arg, int irq, int flags, void **cookiep)
cpu_establish_hardintr(const char *name, driver_filter_t * filt,
void (*handler) (void *), void *arg, int irq, int flags, void **cookiep)
{
struct mips_intrhand *mih; /* descriptor for the IRQ */
struct intr_event *ie; /* descriptor for the IRQ */
struct mips_intrhand *mih; /* descriptor for the IRQ */
struct intr_event *ie; /* descriptor for the IRQ */
int errcode;
if (irq < 0 || irq > XLR_MAX_INTR)
panic("%s called for unknown hard intr %d", __func__, irq);
/* FIXME locking - not needed now, because we do this only on startup from
CPU0 */
/*
* FIXME locking - not needed now, because we do this only on
* startup from CPU0
*/
mih = &mips_intr_handlers[irq];
/*mih->cntp = &intrcnt[irq]; */
/* mih->cntp = &intrcnt[irq]; */
ie = mih->mih_event;
if (ie == NULL) {
errcode = intr_event_create(&ie, (void *)(uintptr_t)irq, 0,
errcode = intr_event_create(&ie, (void *)(uintptr_t) irq, 0,
irq, mips_mask_hard_irq, mips_unmask_hard_irq,
NULL, NULL, "hard intr%d:", irq);
if (errcode) {
printf("Could not create event for intr %d\n", irq);
return;
@ -97,17 +99,17 @@ cpu_establish_hardintr(const char *name, driver_filter_t *filt,
intr_event_add_handler(ie, name, filt, handler, arg,
intr_priority(flags), flags, cookiep);
mih->mih_event = ie;
mips_unmask_hard_irq((void*)(uintptr_t)irq);
mips_unmask_hard_irq((void *)(uintptr_t) irq);
}
void
cpu_establish_softintr(const char *name, driver_filter_t *filt,
void (*handler)(void*), void *arg, int irq, int flags,
cpu_establish_softintr(const char *name, driver_filter_t * filt,
void (*handler) (void *), void *arg, int irq, int flags,
void **cookiep)
{
/* we don't separate them into soft/hard like other mips */
cpu_establish_hardintr(name, filt, handler, arg, irq, flags, cookiep);
/* we don't separate them into soft/hard like other mips */
cpu_establish_hardintr(name, filt, handler, arg, irq, flags, cookiep);
}
@ -126,24 +128,23 @@ cpu_intr(struct trapframe *tf)
critical_exit();
return;
}
/* No need to clear the EIRR here. the handler is gonna
* write to compare which clears eirr also
/*
* No need to clear the EIRR here. the handler is gonna write to
* compare which clears eirr also
*/
if (eirr & (1 << IRQ_TIMER)) {
count_compare_clockhandler(tf);
critical_exit();
return;
}
/* FIXME sched pin >? LOCK>? */
for(i = sizeof(eirr)*8 - 1; i>=0; i--) {
if ((eirr & 1ULL<<i) == 0)
for (i = sizeof(eirr) * 8 - 1; i >= 0; i--) {
if ((eirr & 1ULL << i) == 0)
continue;
#ifdef SMP
/* These are reserved interrupts */
if((i == IPI_AST) || (i == IPI_RENDEZVOUS) || (i == IPI_STOP)
|| (i == IPI_SMP_CALL_FUNCTION)) {
if ((i == IPI_AST) || (i == IPI_RENDEZVOUS) || (i == IPI_STOP)
|| (i == IPI_SMP_CALL_FUNCTION)) {
write_c0_eirr64(1ULL << i);
pic_ack(i);
smp_handle_ipi(tf, i);
@ -161,19 +162,17 @@ cpu_intr(struct trapframe *tf)
#endif
#endif
mih = &mips_intr_handlers[i];
/*atomic_add_long(mih->cntp, 1);*/
ie = mih->mih_event;
/* atomic_add_long(mih->cntp, 1); */
ie = mih->mih_event;
write_c0_eirr64(1ULL << i);
if (!ie || TAILQ_EMPTY(&ie->ie_handlers)) {
printf("stray interrupt %d\n", i);
continue;
}
if (intr_event_handle(ie, tf) != 0) {
printf("stray interrupt %d\n",i);
printf("stray interrupt %d\n", i);
}
}
critical_exit();
}

153
sys/mips/rmi/iodi.c
View File

@ -74,15 +74,18 @@ extern void iodi_activateirqs(void);
extern bus_space_tag_t uart_bus_space_mem;
static struct resource *iodi_alloc_resource(device_t, device_t, int, int *,
u_long, u_long, u_long, u_int);
static struct resource *
iodi_alloc_resource(device_t, device_t, int, int *,
u_long, u_long, u_long, u_int);
static int iodi_activate_resource(device_t, device_t, int, int,
struct resource *);
static int iodi_setup_intr(device_t, device_t, struct resource *, int,
driver_filter_t *, driver_intr_t *, void *, void **);
static int
iodi_activate_resource(device_t, device_t, int, int,
struct resource *);
static int
iodi_setup_intr(device_t, device_t, struct resource *, int,
driver_filter_t *, driver_intr_t *, void *, void **);
struct iodi_softc *iodi_softc; /* There can be only one. */
struct iodi_softc *iodi_softc; /* There can be only one. */
/*
static void pic_usb_ack(void *arg)
@ -98,56 +101,56 @@ static void pic_usb_ack(void *arg)
static int
iodi_setup_intr(device_t dev, device_t child,
struct resource *ires, int flags, driver_filter_t *filt, driver_intr_t *intr, void *arg,
void **cookiep)
struct resource *ires, int flags, driver_filter_t * filt, driver_intr_t * intr, void *arg,
void **cookiep)
{
int level;
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
xlr_reg_t reg;
int level;
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
xlr_reg_t reg;
/* FIXME is this the right place to fiddle with PIC? */
if (strcmp(device_get_name(child),"uart") == 0) {
/* FIXME uart 1? */
mtx_lock_spin(&xlr_pic_lock);
level = PIC_IRQ_IS_EDGE_TRIGGERED(PIC_IRT_UART_0_INDEX);
xlr_write_reg(mmio, PIC_IRT_0_UART_0, 0x01);
xlr_write_reg(mmio, PIC_IRT_1_UART_0, ((1 << 31) | (level<<30)|(1<<6)|(PIC_UART_0_IRQ)));
mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr("uart", NULL,
(driver_intr_t *)intr, (void *)arg, PIC_UART_0_IRQ, flags, cookiep);
/* FIXME is this the right place to fiddle with PIC? */
if (strcmp(device_get_name(child), "uart") == 0) {
/* FIXME uart 1? */
mtx_lock_spin(&xlr_pic_lock);
level = PIC_IRQ_IS_EDGE_TRIGGERED(PIC_IRT_UART_0_INDEX);
xlr_write_reg(mmio, PIC_IRT_0_UART_0, 0x01);
xlr_write_reg(mmio, PIC_IRT_1_UART_0, ((1 << 31) | (level << 30) | (1 << 6) | (PIC_UART_0_IRQ)));
mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr("uart", NULL,
(driver_intr_t *) intr, (void *)arg, PIC_UART_0_IRQ, flags, cookiep);
} else if (strcmp(device_get_name(child),"rge") == 0) {
int irq;
irq = rman_get_rid(ires);
mtx_lock_spin(&xlr_pic_lock);
reg = xlr_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
xlr_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, reg | (1<<6)|(1<<30)| (1<<31));
mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr("rge", NULL, (driver_intr_t *)intr, (void *)arg, irq, flags, cookiep);
} else if (strcmp(device_get_name(child), "rge") == 0) {
int irq;
} else if (strcmp(device_get_name(child),"ehci") == 0) {
mtx_lock_spin(&xlr_pic_lock);
reg = xlr_read_reg(mmio, PIC_IRT_1_BASE + PIC_USB_IRQ - PIC_IRQ_BASE);
xlr_write_reg(mmio, PIC_IRT_1_BASE + PIC_USB_IRQ - PIC_IRQ_BASE, reg | (1<<6)|(1<<30)| (1<<31));
mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr("ehci", NULL, (driver_intr_t *)intr, (void *)arg, PIC_USB_IRQ, flags, cookiep);
}
irq = rman_get_rid(ires);
mtx_lock_spin(&xlr_pic_lock);
reg = xlr_read_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE);
xlr_write_reg(mmio, PIC_IRT_1_BASE + irq - PIC_IRQ_BASE, reg | (1 << 6) | (1 << 30) | (1 << 31));
mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr("rge", NULL, (driver_intr_t *) intr, (void *)arg, irq, flags, cookiep);
BUS_SETUP_INTR(device_get_parent(dev),
child, ires, flags, filt, intr, arg, cookiep);
} else if (strcmp(device_get_name(child), "ehci") == 0) {
mtx_lock_spin(&xlr_pic_lock);
reg = xlr_read_reg(mmio, PIC_IRT_1_BASE + PIC_USB_IRQ - PIC_IRQ_BASE);
xlr_write_reg(mmio, PIC_IRT_1_BASE + PIC_USB_IRQ - PIC_IRQ_BASE, reg | (1 << 6) | (1 << 30) | (1 << 31));
mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr("ehci", NULL, (driver_intr_t *) intr, (void *)arg, PIC_USB_IRQ, flags, cookiep);
}
BUS_SETUP_INTR(device_get_parent(dev),
child, ires, flags, filt, intr, arg, cookiep);
return (0);
return (0);
}
/* Strange hook found in mips/include/bus.h */
#ifndef MIPS_BUS_SPACE_PCI
#define MIPS_BUS_SPACE_PCI 10
#define MIPS_BUS_SPACE_PCI 10
#endif
static struct resource *
iodi_alloc_resource(device_t bus, device_t child, int type, int *rid,
u_long start, u_long end, u_long count, u_int flags)
u_long start, u_long end, u_long count, u_int flags)
{
struct resource *res = malloc(sizeof(*res), M_DEVBUF, M_WAITOK);
int unit;
@ -156,53 +159,52 @@ iodi_alloc_resource(device_t bus, device_t child, int type, int *rid,
switch (type) {
case SYS_RES_IRQ:
device_printf(bus, "IRQ resource - for %s %lx-%lx\n",
device_get_nameunit(child), start, end);
break;
device_get_nameunit(child), start, end);
break;
case SYS_RES_IOPORT:
case SYS_RES_IOPORT:
device_printf(bus, "IOPORT resource - for %s %lx-%lx\n",
device_get_nameunit(child), start, end);
break;
device_get_nameunit(child), start, end);
break;
case SYS_RES_MEMORY:
case SYS_RES_MEMORY:
device_printf(bus, "MEMORY resource - for %s %lx-%lx\n",
device_get_nameunit(child), start, end);
break;
}
device_get_nameunit(child), start, end);
break;
}
#endif
if (strcmp(device_get_name(child),"uart") == 0) {
if ((unit=device_get_unit(child)) == 0) { /* uart 0 */
if (strcmp(device_get_name(child), "uart") == 0) {
if ((unit = device_get_unit(child)) == 0) { /* uart 0 */
res->r_bushandle = (xlr_io_base + XLR_IO_UART_0_OFFSET);
}
else if ( unit == 1) {
} else if (unit == 1) {
res->r_bushandle = (xlr_io_base + XLR_IO_UART_1_OFFSET);
}
else
} else
printf("%s: Unknown uart unit\n", __FUNCTION__);
res->r_bustag = uart_bus_space_mem;
} else if (strcmp(device_get_name(child),"ehci") == 0) {
} else if (strcmp(device_get_name(child), "ehci") == 0) {
res->r_bushandle = 0xbef24000;
res->r_bustag = (bus_space_tag_t)MIPS_BUS_SPACE_PCI;
} else if (strcmp(device_get_name(child),"cfi") == 0) {
res->r_bustag = (bus_space_tag_t) MIPS_BUS_SPACE_PCI;
} else if (strcmp(device_get_name(child), "cfi") == 0) {
res->r_bushandle = 0xbc000000;
res->r_bustag = 0;
}
/*res->r_start = *rid;*/
/* res->r_start = *rid; */
return (res);
}
static int
iodi_activate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
struct resource *r)
{
return (0);
}
/* prototypes */
static int iodi_probe(device_t);
static int iodi_attach(device_t);
static void iodi_identify(driver_t *, device_t);
static int iodi_probe(device_t);
static int iodi_attach(device_t);
static void iodi_identify(driver_t *, device_t);
int
iodi_probe(device_t dev)
@ -211,9 +213,9 @@ iodi_probe(device_t dev)
}
void
iodi_identify(driver_t *driver, device_t parent)
iodi_identify(driver_t * driver, device_t parent)
{
BUS_ADD_CHILD(parent, 0, "iodi", 0);
}
@ -221,15 +223,16 @@ int
iodi_attach(device_t dev)
{
device_t tmpd;
/*
* Attach each devices
* Attach each devices
*/
device_add_child(dev, "uart", 0);
device_add_child(dev, "xlr_i2c", 0);
if (xlr_board_info.usb)
device_add_child(dev, "ehci", 0);
if (xlr_board_info.cfi)
device_add_child(dev, "cfi", 0);
@ -246,7 +249,6 @@ iodi_attach(device_t dev)
tmpd = device_add_child(dev, "rge", 3);
device_set_ivars(tmpd, &xlr_board_info.gmac_block[0]);
}
if (xlr_board_info.gmac_block[1].enabled) {
if (xlr_board_info.gmac_block[1].type == XLR_GMAC) {
tmpd = device_add_child(dev, "rge", 4);
@ -261,17 +263,16 @@ iodi_attach(device_t dev)
tmpd = device_add_child(dev, "rge", 7);
device_set_ivars(tmpd, &xlr_board_info.gmac_block[1]);
} else if (xlr_board_info.gmac_block[1].type == XLR_XGMAC) {
#if 0 /* XGMAC not yet */
#if 0 /* XGMAC not yet */
tmpd = device_add_child(dev, "rge", 4);
device_set_ivars(tmpd, &xlr_board_info.gmac_block[1]);
tmpd = device_add_child(dev, "rge", 5);
device_set_ivars(tmpd, &xlr_board_info.gmac_block[1]);
#endif
} else
device_printf(dev, "Unknown type of gmac 1\n");
} else
device_printf(dev, "Unknown type of gmac 1\n");
}
bus_generic_probe(dev);
bus_generic_attach(dev);
return 0;
@ -290,7 +291,7 @@ static device_method_t iodi_methods[] = {
static driver_t iodi_driver = {
"iodi",
iodi_methods,
1 /* no softc */
1 /* no softc */
};
static devclass_t iodi_devclass;

4
sys/mips/rmi/iomap.h
View File

@ -92,7 +92,7 @@
* For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28)
* Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes
* ie 1<<24 = 16M
*/
*/
#define DEFAULT_PCI_CONFIG_BASE 0x18000000
#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000
#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000
@ -107,4 +107,4 @@ extern unsigned long xlr_io_base;
extern void on_chip_init(void);
#endif /* _RMI_IOMAP_H_ */
#endif /* _RMI_IOMAP_H_ */

503
sys/mips/rmi/msgring.c
View File

@ -30,289 +30,288 @@
/**********************************************************
* -----------------DO NOT EDIT THIS FILE------------------
* This file has been autogenerated by the build process
* from "msgring.cfg"
* from "msgring.cfg"
**********************************************************/
#include <mips/rmi/msgring.h>
#include <mips/rmi/msgring.h>
struct bucket_size bucket_sizes = {
{
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 0,
32, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 0,
0, 32, 32, 32, 32, 32, 0, 32,
0, 0, 0, 0, 0, 0, 0, 0,
0, 32, 0, 32, 0, 0, 0, 0,
128, 0, 0, 0, 128, 0, 0, 0,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 0,
32, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 0,
0, 32, 32, 32, 32, 32, 0, 32,
0, 0, 0, 0, 0, 0, 0, 0,
0, 32, 0, 32, 0, 0, 0, 0,
128, 0, 0, 0, 128, 0, 0, 0,
}
};
struct stn_cc cc_table_cpu_0 = {{
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 4 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{0, 2 , 4 , 4 , 4 , 4 , 0 , 2 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 2 , 0 , 2 , 0 , 0 , 0 , 0 },
{16, 0 , 0 , 0 , 16 , 0 , 0 , 0 },
}};
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 4, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 2, 4, 4, 4, 4, 0, 2},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 2, 0, 2, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_cpu_1 = {{
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{0, 2 , 4 , 4 , 4 , 4 , 0 , 2 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 2 , 0 , 2 , 0 , 0 , 0 , 0 },
{16, 0 , 0 , 0 , 16 , 0 , 0 , 0 },
}};
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 2, 4, 4, 4, 4, 0, 2},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 2, 0, 2, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_cpu_2 = {{
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{0, 4 , 4 , 4 , 4 , 4 , 0 , 4 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 0 , 4 , 0 , 0 , 0 , 0 },
{16, 0 , 0 , 0 , 16 , 0 , 0 , 0 },
}};
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 4, 4, 4, 4, 4, 0, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 4, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_cpu_3 = {{
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{0, 4 , 4 , 4 , 4 , 4 , 0 , 4 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 0 , 4 , 0 , 0 , 0 , 0 },
{16, 0 , 0 , 0 , 16 , 0 , 0 , 0 },
}};
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 4, 4, 4, 4, 4, 0, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 4, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_cpu_4 = {{
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{0, 4 , 4 , 4 , 4 , 4 , 0 , 4 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 0 , 4 , 0 , 0 , 0 , 0 },
{16, 0 , 0 , 0 , 16 , 0 , 0 , 0 },
}};
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 4, 4, 4, 4, 4, 0, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 4, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_cpu_5 = {{
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{0, 4 , 4 , 4 , 4 , 4 , 0 , 4 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 0 , 4 , 0 , 0 , 0 , 0 },
{16, 0 , 0 , 0 , 16 , 0 , 0 , 0 },
}};
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 4, 4, 4, 4, 4, 0, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 4, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_cpu_6 = {{
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{0, 4 , 4 , 4 , 4 , 4 , 0 , 4 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 0 , 4 , 0 , 0 , 0 , 0 },
{16, 0 , 0 , 0 , 16 , 0 , 0 , 0 },
}};
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 4, 4, 4, 4, 4, 0, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 4, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_cpu_7 = {{
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{4, 2 , 2 , 2 , 2 , 2 , 2 , 2 },
{2, 2 , 2 , 2 , 2 , 2 , 2 , 0 },
{0, 4 , 4 , 4 , 4 , 4 , 0 , 4 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 0 , 4 , 0 , 0 , 0 , 0 },
{16, 0 , 0 , 0 , 16 , 0 , 0 , 0 },
}};
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 4, 4, 4, 4, 4, 0, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 4, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_xgs_0 = {{
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
}};
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc cc_table_xgs_1 = {{
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 4 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
}};
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 4, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc cc_table_gmac = {{
{8, 8 , 8 , 8 , 16 , 16 , 16 , 16 },
{8, 8 , 8 , 8 , 16 , 16 , 16 , 16 },
{8, 8 , 8 , 8 , 16 , 16 , 16 , 16 },
{8, 8 , 8 , 8 , 16 , 16 , 16 , 16 },
{8, 8 , 8 , 8 , 16 , 16 , 16 , 16 },
{8, 8 , 8 , 8 , 16 , 16 , 16 , 16 },
{8, 8 , 8 , 8 , 16 , 16 , 16 , 16 },
{8, 8 , 8 , 8 , 16 , 16 , 16 , 16 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 0 , 0 , 0 , 0 , 0 , 4 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
}};
{8, 8, 8, 8, 16, 16, 16, 16},
{8, 8, 8, 8, 16, 16, 16, 16},
{8, 8, 8, 8, 16, 16, 16, 16},
{8, 8, 8, 8, 16, 16, 16, 16},
{8, 8, 8, 8, 16, 16, 16, 16},
{8, 8, 8, 8, 16, 16, 16, 16},
{8, 8, 8, 8, 16, 16, 16, 16},
{8, 8, 8, 8, 16, 16, 16, 16},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 0, 0, 0, 0, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc cc_table_dma = {{
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
}};
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc cc_table_sec = {{
{8, 8 , 8 , 8 , 0 , 0 , 0 , 0 },
{8, 8 , 8 , 4 , 0 , 0 , 0 , 0 },
{8, 8 , 8 , 8 , 0 , 0 , 0 , 0 },
{8, 8 , 8 , 8 , 0 , 0 , 0 , 0 },
{8, 8 , 8 , 8 , 0 , 0 , 0 , 0 },
{8, 8 , 8 , 8 , 0 , 0 , 0 , 0 },
{8, 8 , 8 , 8 , 0 , 0 , 0 , 0 },
{8, 8 , 8 , 8 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
}};
{8, 8, 8, 8, 0, 0, 0, 0},
{8, 8, 8, 4, 0, 0, 0, 0},
{8, 8, 8, 8, 0, 0, 0, 0},
{8, 8, 8, 8, 0, 0, 0, 0},
{8, 8, 8, 8, 0, 0, 0, 0},
{8, 8, 8, 8, 0, 0, 0, 0},
{8, 8, 8, 8, 0, 0, 0, 0},
{8, 8, 8, 8, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};

281
sys/mips/rmi/msgring.h
View File

@ -187,83 +187,94 @@
#define MSGRNG_CODE_BOOT_WAKEUP 200
#define MSGRNG_CODE_SPI4 3
static inline int msgrng_xgmac_stid_rfr(int id)
static inline int
msgrng_xgmac_stid_rfr(int id)
{
return !id ? MSGRNG_STNID_XMAC0RFR : MSGRNG_STNID_XMAC1RFR;
return !id ? MSGRNG_STNID_XMAC0RFR : MSGRNG_STNID_XMAC1RFR;
}
static inline int msgrng_xgmac_stid_jfr(int id)
static inline int
msgrng_xgmac_stid_jfr(int id)
{
return !id ? MSGRNG_STNID_XMAC0JFR : MSGRNG_STNID_XMAC1JFR;
return !id ? MSGRNG_STNID_XMAC0JFR : MSGRNG_STNID_XMAC1JFR;
}
static inline int msgrng_xgmac_stid_tx(int id)
static inline int
msgrng_xgmac_stid_tx(int id)
{
return !id ? MSGRNG_STNID_XMAC0_00_TX : MSGRNG_STNID_XMAC1_00_TX;
return !id ? MSGRNG_STNID_XMAC0_00_TX : MSGRNG_STNID_XMAC1_00_TX;
}
static inline int msgrng_gmac_stid_rfr(int id)
static inline int
msgrng_gmac_stid_rfr(int id)
{
return (MSGRNG_STNID_GMACRFR_0);
return (MSGRNG_STNID_GMACRFR_0);
}
static inline int msgrng_gmac_stid_rfr_split_mode(int id)
static inline int
msgrng_gmac_stid_rfr_split_mode(int id)
{
return ((id>>1)?MSGRNG_STNID_GMACRFR_1:MSGRNG_STNID_GMACRFR_0);
return ((id >> 1) ? MSGRNG_STNID_GMACRFR_1 : MSGRNG_STNID_GMACRFR_0);
}
static inline int msgrng_gmac_stid_jfr(int id)
static inline int
msgrng_gmac_stid_jfr(int id)
{
return MSGRNG_STNID_GMACJFR_0;
return MSGRNG_STNID_GMACJFR_0;
}
static inline int msgrng_gmac_stid_jfr_split_mode(int id)
static inline int
msgrng_gmac_stid_jfr_split_mode(int id)
{
return ((id>>1)?MSGRNG_STNID_GMACJFR_1:MSGRNG_STNID_GMACJFR_0);
return ((id >> 1) ? MSGRNG_STNID_GMACJFR_1 : MSGRNG_STNID_GMACJFR_0);
}
static inline int msgrng_gmac_stid_tx(int id)
static inline int
msgrng_gmac_stid_tx(int id)
{
return (MSGRNG_STNID_GMACTX0 + id);
return (MSGRNG_STNID_GMACTX0 + id);
}
static inline void msgrng_send(unsigned int stid)
static inline void
msgrng_send(unsigned int stid)
{
__asm__ volatile (
".set push\n"
".set noreorder\n"
"sync\n"
// "msgsnd %0\n"
"move $8, %0\n"
"c2 0x80001\n"
".set pop\n"
: : "r" (stid) : "$8"
);
__asm__ volatile (
".set push\n"
".set noreorder\n"
"sync\n"
// "msgsnd %0\n"
"move $8, %0\n"
"c2 0x80001\n"
".set pop\n"
:: "r" (stid):"$8"
);
}
static inline void msgrng_receive(unsigned int pri)
static inline void
msgrng_receive(unsigned int pri)
{
__asm__ volatile (
".set push\n"
".set noreorder\n"
// "msgld %0\n"
"move $8, %0\n"
"c2 0x80002\n"
".set pop\n"
: : "r" (pri) : "$8"
);
__asm__ volatile (
".set push\n"
".set noreorder\n"
// "msgld %0\n"
"move $8, %0\n"
"c2 0x80002\n"
".set pop\n"
:: "r" (pri):"$8"
);
}
static inline void msgrng_wait(unsigned int mask)
static inline void
msgrng_wait(unsigned int mask)
{
__asm__ volatile (
".set push\n"
".set noreorder\n"
// "msgwait %0\n"
"move $8, %0\n"
"c2 0x80003\n"
".set pop\n"
: :"r" (mask) : "$8"
);
__asm__ volatile (
".set push\n"
".set noreorder\n"
// "msgwait %0\n"
"move $8, %0\n"
"c2 0x80003\n"
".set pop\n"
:: "r" (mask):"$8"
);
}
#define msgrng_enable(flags) \
@ -292,34 +303,35 @@ do { \
#define msgrng_flags_restore(flags) msgrng_disable(flags)
struct msgrng_msg {
__uint64_t msg0;
__uint64_t msg1;
__uint64_t msg2;
__uint64_t msg3;
__uint64_t msg0;
__uint64_t msg1;
__uint64_t msg2;
__uint64_t msg3;
};
static inline void message_send_block_fast(int size, unsigned int code, unsigned int stid,
unsigned long long msg0, unsigned long long msg1,
unsigned long long msg2, unsigned long long msg3)
static inline void
message_send_block_fast(int size, unsigned int code, unsigned int stid,
unsigned long long msg0, unsigned long long msg1,
unsigned long long msg2, unsigned long long msg3)
{
__asm__ __volatile__ (".set push\n"
".set noreorder\n"
".set mips64\n"
"dmtc2 %1, $0, 0\n"
"dmtc2 %2, $0, 1\n"
"dmtc2 %3, $0, 2\n"
"dmtc2 %4, $0, 3\n"
"move $8, %0\n"
"1: c2 0x80001\n"
"mfc2 $8, $2\n"
"andi $8, $8, 0x6\n"
"bnez $8, 1b\n"
"move $8, %0\n"
".set pop\n"
:
: "r"(((size-1)<<16)|(code<<8)|stid), "r" (msg0), "r" (msg1), "r"(msg2), "r"(msg3)
: "$8"
);
__asm__ __volatile__(".set push\n"
".set noreorder\n"
".set mips64\n"
"dmtc2 %1, $0, 0\n"
"dmtc2 %2, $0, 1\n"
"dmtc2 %3, $0, 2\n"
"dmtc2 %4, $0, 3\n"
"move $8, %0\n"
"1: c2 0x80001\n"
"mfc2 $8, $2\n"
"andi $8, $8, 0x6\n"
"bnez $8, 1b\n"
"move $8, %0\n"
".set pop\n"
:
: "r"(((size - 1) << 16) | (code << 8) | stid), "r"(msg0), "r"(msg1), "r"(msg2), "r"(msg3)
: "$8"
);
}
#define message_receive_fast(bucket, size, code, stid, msg0, msg1, msg2, msg3) \
@ -338,86 +350,94 @@ static inline void message_send_block_fast(int size, unsigned int code, unsigned
_tmp=0; \
} \
_tmp; \
} )
} )
static __inline__ int message_send(unsigned int size, unsigned int code,
unsigned int stid, struct msgrng_msg *msg)
static __inline__ int
message_send(unsigned int size, unsigned int code,
unsigned int stid, struct msgrng_msg *msg)
{
unsigned int dest = 0;
unsigned long long status=0;
int i=0;
unsigned int dest = 0;
unsigned long long status = 0;
int i = 0;
msgrng_load_tx_msg0(msg->msg0);
msgrng_load_tx_msg1(msg->msg1);
msgrng_load_tx_msg2(msg->msg2);
msgrng_load_tx_msg3(msg->msg3);
msgrng_load_tx_msg0(msg->msg0);
msgrng_load_tx_msg1(msg->msg1);
msgrng_load_tx_msg2(msg->msg2);
msgrng_load_tx_msg3(msg->msg3);
dest = ((size-1)<<16)|(code<<8)|(stid);
dest = ((size - 1) << 16) | (code << 8) | (stid);
//dbg_msg("Sending msg<%Lx,%Lx,%Lx,%Lx> to dest = %x\n",
//msg->msg0, msg->msg1, msg->msg2, msg->msg3, dest);
//dbg_msg("Sending msg<%Lx,%Lx,%Lx,%Lx> to dest = %x\n",
//msg->msg0, msg->msg1, msg->msg2, msg->msg3, dest);
msgrng_send(dest);
msgrng_send(dest);
for(i=0;i<16;i++) {
status = msgrng_read_status();
// dbg_msg("status = %Lx\n", status);
for (i = 0; i < 16; i++) {
status = msgrng_read_status();
//dbg_msg("status = %Lx\n", status);
if (status & 0x6) {
continue;
if (status & 0x6) {
continue;
} else
break;
}
else break;
if (i == 16) {
if (dest == 0x61)
//dbg_msg("Processor %x: Unable to send msg to %llx\n", processor_id(), dest);
return status & 0x6;
}
if (i==16) {
if (dest == 0x61)
//dbg_msg("Processor %x: Unable to send msg to %llx\n", processor_id(), dest);
return status & 0x6;
}
return msgrng_read_status() & 0x06;
return msgrng_read_status() & 0x06;
}
static __inline__ int message_send_retry(unsigned int size, unsigned int code,
unsigned int stid, struct msgrng_msg *msg)
static __inline__ int
message_send_retry(unsigned int size, unsigned int code,
unsigned int stid, struct msgrng_msg *msg)
{
int res = 0;
int retry = 0;
int res = 0;
int retry = 0;
for(;;) {
res = message_send(size, code, stid, msg);
/* retry a pending fail */
if (res & 0x02) continue;
/* credit fail */
if (res & 0x04) retry++;
else break;
if (retry == 4) return res & 0x06;
}
for (;;) {
res = message_send(size, code, stid, msg);
/* retry a pending fail */
if (res & 0x02)
continue;
/* credit fail */
if (res & 0x04)
retry++;
else
break;
if (retry == 4)
return res & 0x06;
}
return 0;
return 0;
}
static __inline__ int message_receive(int pri, int *size, int *code, int *src_id,
struct msgrng_msg *msg)
static __inline__ int
message_receive(int pri, int *size, int *code, int *src_id,
struct msgrng_msg *msg)
{
int res = message_receive_fast(pri, *size, *code, *src_id, msg->msg0, msg->msg1, msg->msg2, msg->msg3);
int res = message_receive_fast(pri, *size, *code, *src_id, msg->msg0, msg->msg1, msg->msg2, msg->msg3);
#ifdef MSGRING_DUMP_MESSAGES
if (!res) {
dbg_msg("Received msg <%llx, %llx, %llx, %llx> <%d,%d,%d>\n",
msg->msg0, msg->msg1, msg->msg2, msg->msg3,
*size, *code, *src_id);
}
if (!res) {
dbg_msg("Received msg <%llx, %llx, %llx, %llx> <%d,%d,%d>\n",
msg->msg0, msg->msg1, msg->msg2, msg->msg3,
*size, *code, *src_id);
}
#endif
return res;
return res;
}
#define MSGRNG_STN_RX_QSIZE 256
struct stn_cc {
unsigned short counters[16][8];
unsigned short counters[16][8];
};
struct bucket_size {
unsigned short bucket[128];
unsigned short bucket[128];
};
extern struct bucket_size bucket_sizes;
@ -495,12 +515,13 @@ enum {
MAX_TX_STNS
};
extern int register_msgring_handler(int major,
void (*action)(int, int,int,int,struct msgrng_msg *, void *),
void *dev_id);
extern void xlr_msgring_cpu_init(void);
extern int
register_msgring_handler(int major,
void (*action) (int, int, int, int, struct msgrng_msg *, void *),
void *dev_id);
extern void xlr_msgring_cpu_init(void);
extern void xlr_msgring_config(void);
extern void xlr_msgring_config(void);
#define cpu_to_msgring_bucket(cpu) ((((cpu) >> 2)<<3)|((cpu) & 0x03))

373
sys/mips/rmi/msgring_xls.c
View File

@ -7,212 +7,211 @@
#include <mips/rmi/msgring.h>
struct bucket_size xls_bucket_sizes = {
{ 32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 32, 32, 32, 32, 32, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 32, 32, 32, 32, 32, 0, 0,
64, 64, 64, 64, 32, 32, 32, 32,
0, 0, 0, 0, 0, 0, 0, 0,
128, 128, 0, 0, 0, 0, 0, 0,
{32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 32, 32, 32, 32, 32, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 32, 32, 32, 32, 32, 0, 0,
64, 64, 64, 64, 32, 32, 32, 32,
0, 0, 0, 0, 0, 0, 0, 0,
128, 128, 0, 0, 0, 0, 0, 0,
}
};
struct stn_cc xls_cc_table_cpu_0 = {{
{1, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 8 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 8 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 8 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 8 , 8 , 8 , 8 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 8 , 8 , 8 , 8 , 0 , 0 },
{16, 16 , 16 , 16 , 16 , 16 , 16 , 16 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{32, 32 , 0 , 0 , 0 , 0 , 0 , 0 },
}};
{1, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 8, 0, 0, 0, 0},
{0, 0, 0, 8, 0, 0, 0, 0},
{0, 0, 0, 8, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{16, 16, 16, 16, 16, 16, 16, 16},
{0, 0, 0, 0, 0, 0, 0, 0},
{32, 32, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_cpu_1 = {{
{1, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 8 , 8 , 8 , 8 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 8 , 8 , 8 , 8 , 0 , 0 },
{16, 16 , 16 , 16 , 16 , 16 , 16 , 16 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{32, 32 , 0 , 0 , 0 , 0 , 0 , 0 },
}};
{1, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{16, 16, 16, 16, 16, 16, 16, 16},
{0, 0, 0, 0, 0, 0, 0, 0},
{32, 32, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_cpu_2 = {{
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 8 , 8 , 8 , 8 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 8 , 8 , 8 , 8 , 0 , 0 },
{16, 16 , 16 , 16 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{32, 32 , 0 , 0 , 0 , 0 , 0 , 0 },
}};
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{16, 16, 16, 16, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{32, 32, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_cpu_3 = {{
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 8 , 8 , 8 , 8 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 4 , 8 , 8 , 8 , 8 , 0 , 0 },
{16, 16 , 16 , 16 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{32, 32 , 0 , 0 , 0 , 0 , 0 , 0 },
}};
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{16, 16, 16, 16, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{32, 32, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_gmac0 = {{
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 8 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 8 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
}};
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 8, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 8, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_gmac1 = {{
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{8, 8 , 8 , 8 , 8 , 8 , 8 , 8 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 8 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 8 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
}};
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 8, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 8, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_dma = {{
{4, 4 , 4 , 4 , 4 , 4 , 4 , 4 },
{4, 4 , 4 , 2 , 4 , 4 , 4 , 4 },
{4, 4 , 4 , 2 , 4 , 4 , 4 , 4 },
{4, 4 , 4 , 2 , 4 , 4 , 4 , 4 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
}};
{4, 4, 4, 4, 4, 4, 4, 4},
{4, 4, 4, 2, 4, 4, 4, 4},
{4, 4, 4, 2, 4, 4, 4, 4},
{4, 4, 4, 2, 4, 4, 4, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_cmp = {{
{4, 4 , 4 , 4 , 4 , 4 , 4 , 4 },
{4, 4 , 4 , 2 , 4 , 4 , 4 , 4 },
{4, 4 , 4 , 2 , 4 , 4 , 4 , 4 },
{4, 4 , 4 , 2 , 4 , 4 , 4 , 4 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
}};
{4, 4, 4, 4, 4, 4, 4, 4},
{4, 4, 4, 2, 4, 4, 4, 4},
{4, 4, 4, 2, 4, 4, 4, 4},
{4, 4, 4, 2, 4, 4, 4, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_pcie = {{
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
}};
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_sec = {{
{6, 8 , 8 , 8 , 0 , 0 , 0 , 0 },
{8, 8 , 8 , 4 , 0 , 0 , 0 , 0 },
{8, 8 , 8 , 4 , 0 , 0 , 0 , 0 },
{8, 8 , 8 , 4 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
{0, 0 , 0 , 0 , 0 , 0 , 0 , 0 },
}};
{6, 8, 8, 8, 0, 0, 0, 0},
{8, 8, 8, 4, 0, 0, 0, 0},
{8, 8, 8, 4, 0, 0, 0, 0},
{8, 8, 8, 4, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};

160
sys/mips/rmi/on_chip.c
View File

@ -49,11 +49,14 @@
#include <mips/rmi/pic.h>
#include <mips/rmi/board.h>
void disable_msgring_int(void *arg) ;
void enable_msgring_int(void *arg) ;
void
disable_msgring_int(void *arg);
void
enable_msgring_int(void *arg);
/* definitions */
struct tx_stn_handler {
void (*action)(int, int, int, int, struct msgrng_msg *, void *);
void (*action) (int, int, int, int, struct msgrng_msg *, void *);
void *dev_id;
};
@ -78,11 +81,11 @@ static struct mtx msgrng_lock;
static int msgring_int_enabled;
struct mtx xlr_pic_lock;
static int msgring_pop_num_buckets;
static uint32_t msgring_pop_bucket_mask;
static int msgring_int_type;
static int msgring_watermark_count;
static uint32_t msgring_thread_mask;
static int msgring_pop_num_buckets;
static uint32_t msgring_pop_bucket_mask;
static int msgring_int_type;
static int msgring_watermark_count;
static uint32_t msgring_thread_mask;
uint32_t msgrng_msg_cycles = 0;
@ -90,7 +93,8 @@ int xlr_counters[MAXCPU][XLR_MAX_COUNTERS] __aligned(XLR_CACHELINE_SIZE);
void xlr_msgring_handler(struct trapframe *);
void xlr_msgring_cpu_init(void)
void
xlr_msgring_cpu_init(void)
{
struct stn_cc *cc_config;
struct bucket_size *bucket_sizes;
@ -106,19 +110,20 @@ void xlr_msgring_cpu_init(void)
cc_config = xlr_board_info.credit_configs[id];
msgrng_flags_save(flags);
/* Message Stations are shared among all threads in a cpu core
* Assume, thread 0 on all cores are always active when more than
* 1 thread is active in a core
/*
* Message Stations are shared among all threads in a cpu core
* Assume, thread 0 on all cores are always active when more than 1
* thread is active in a core
*/
msgrng_write_bucksize(0, bucket_sizes->bucket[id*8 + 0]);
msgrng_write_bucksize(1, bucket_sizes->bucket[id*8 + 1]);
msgrng_write_bucksize(2, bucket_sizes->bucket[id*8 + 2]);
msgrng_write_bucksize(3, bucket_sizes->bucket[id*8 + 3]);
msgrng_write_bucksize(4, bucket_sizes->bucket[id*8 + 4]);
msgrng_write_bucksize(5, bucket_sizes->bucket[id*8 + 5]);
msgrng_write_bucksize(6, bucket_sizes->bucket[id*8 + 6]);
msgrng_write_bucksize(7, bucket_sizes->bucket[id*8 + 7]);
msgrng_write_bucksize(0, bucket_sizes->bucket[id * 8 + 0]);
msgrng_write_bucksize(1, bucket_sizes->bucket[id * 8 + 1]);
msgrng_write_bucksize(2, bucket_sizes->bucket[id * 8 + 2]);
msgrng_write_bucksize(3, bucket_sizes->bucket[id * 8 + 3]);
msgrng_write_bucksize(4, bucket_sizes->bucket[id * 8 + 4]);
msgrng_write_bucksize(5, bucket_sizes->bucket[id * 8 + 5]);
msgrng_write_bucksize(6, bucket_sizes->bucket[id * 8 + 6]);
msgrng_write_bucksize(7, bucket_sizes->bucket[id * 8 + 7]);
MSGRNG_CC_INIT_CPU_DEST(0, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(1, cc_config->counters);
@ -140,7 +145,8 @@ void xlr_msgring_cpu_init(void)
msgrng_flags_restore(flags);
}
void xlr_msgring_config(void)
void
xlr_msgring_config(void)
{
msgring_int_type = 0x02;
msgring_pop_num_buckets = 8;
@ -154,34 +160,38 @@ void xlr_msgring_config(void)
/* msgring_watermark_count, msgring_thread_mask); */
}
void xlr_msgring_handler(struct trapframe *tf)
void
xlr_msgring_handler(struct trapframe *tf)
{
unsigned long mflags;
int bucket=0;
int size=0, code=0, rx_stid=0, tx_stid=0;
int bucket = 0;
int size = 0, code = 0, rx_stid = 0, tx_stid = 0;
struct msgrng_msg msg;
unsigned int bucket_empty_bm = 0;
unsigned int status=0;
unsigned int status = 0;
xlr_inc_counter(MSGRNG_INT);
/* TODO: not necessary to disable preemption */
msgrng_flags_save(mflags);
/* First Drain all the high priority messages */
for(;;) {
for (;;) {
bucket_empty_bm = (msgrng_read_status() >> 24) & msgring_pop_bucket_mask;
/* all buckets empty, break*/
if ( bucket_empty_bm == msgring_pop_bucket_mask) break;
/* all buckets empty, break */
if (bucket_empty_bm == msgring_pop_bucket_mask)
break;
for(bucket=0; bucket < msgring_pop_num_buckets; bucket++) {
for (bucket = 0; bucket < msgring_pop_num_buckets; bucket++) {
uint32_t cycles = 0;
if ((bucket_empty_bm & (1 << bucket))/*empty*/) continue;
if ((bucket_empty_bm & (1 << bucket)) /* empty */ )
continue;
status = message_receive(bucket, &size, &code, &rx_stid, &msg);
if (status) continue;
if (status)
continue;
xlr_inc_counter(MSGRNG_MSG);
msgrng_msg_cycles = mips_rd_count();
cycles = msgrng_msg_cycles;
@ -190,20 +200,19 @@ void xlr_msgring_handler(struct trapframe *tf)
if (!tx_stn_handlers[tx_stid].action) {
printf("[%s]: No Handler for message from stn_id=%d, bucket=%d, "
"size=%d, msg0=%llx, dropping message\n",
__FUNCTION__, tx_stid, bucket, size, msg.msg0);
}
else {
"size=%d, msg0=%llx, dropping message\n",
__FUNCTION__, tx_stid, bucket, size, msg.msg0);
} else {
//printf("[%s]: rx_stid = %d\n", __FUNCTION__, rx_stid);
msgrng_flags_restore(mflags);
(*tx_stn_handlers[tx_stid].action)(bucket, size, code, rx_stid,
&msg, tx_stn_handlers[tx_stid].dev_id);
(*tx_stn_handlers[tx_stid].action) (bucket, size, code, rx_stid,
&msg, tx_stn_handlers[tx_stid].dev_id);
msgrng_flags_save(mflags);
}
xlr_set_counter(MSGRNG_MSG_CYCLES, (read_c0_count()-cycles));
}
xlr_set_counter(MSGRNG_MSG_CYCLES, (read_c0_count() - cycles));
}
}
xlr_set_counter(MSGRNG_EXIT_STATUS, msgrng_read_status());
msgrng_flags_restore(mflags);
@ -213,39 +222,42 @@ void xlr_msgring_handler(struct trapframe *tf)
/* Call the msg callback */
}
void enable_msgring_int(void *arg)
void
enable_msgring_int(void *arg)
{
unsigned long mflags=0;
unsigned long mflags = 0;
msgrng_access_save(&msgrng_lock, mflags);
/* enable the message ring interrupts */
msgrng_write_config((msgring_watermark_count<<24)|(IRQ_MSGRING<<16)
|(msgring_thread_mask<<8)|msgring_int_type);
msgrng_access_restore(&msgrng_lock, mflags);
msgrng_write_config((msgring_watermark_count << 24) | (IRQ_MSGRING << 16)
| (msgring_thread_mask << 8) | msgring_int_type);
msgrng_access_restore(&msgrng_lock, mflags);
}
void disable_msgring_int(void *arg)
void
disable_msgring_int(void *arg)
{
unsigned long mflags=0;
unsigned long mflags = 0;
uint32_t config;
msgrng_access_save(&msgrng_lock, mflags);
config = msgrng_read_config();
config &= ~0x3;
msgrng_write_config(config);
msgrng_access_restore(&msgrng_lock, mflags);
msgrng_access_restore(&msgrng_lock, mflags);
}
extern void platform_prep_smp_launch(void);
extern void msgring_process_fast_intr(void *arg);
int register_msgring_handler(int major,
void (*action)(int, int,int,int,struct msgrng_msg *, void *),
void *dev_id)
int
register_msgring_handler(int major,
void (*action) (int, int, int, int, struct msgrng_msg *, void *),
void *dev_id)
{
void *cookie; /* FIXME - use? */
void *cookie; /* FIXME - use? */
if (major >= MAX_TX_STNS)
if (major >= MAX_TX_STNS)
return 1;
//dbg_msg("major=%d, action=%p, dev_id=%p\n", major, action, dev_id);
@ -254,47 +266,49 @@ int register_msgring_handler(int major,
tx_stn_handlers[major].action = action;
tx_stn_handlers[major].dev_id = dev_id;
mtx_unlock_spin(&msgrng_lock);
if (xlr_test_and_set(&msgring_int_enabled)) {
platform_prep_smp_launch();
cpu_establish_hardintr("msgring", (driver_filter_t *)NULL,
(driver_intr_t *)msgring_process_fast_intr,
NULL, IRQ_MSGRING, INTR_TYPE_NET|INTR_FAST, &cookie);
cpu_establish_hardintr("msgring", (driver_filter_t *) NULL,
(driver_intr_t *) msgring_process_fast_intr,
NULL, IRQ_MSGRING, INTR_TYPE_NET | INTR_FAST, &cookie);
/* configure the msgring interrupt on cpu 0 */
enable_msgring_int(NULL);
}
return 0;
}
static void pic_init(void)
static void
pic_init(void)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
int i=0;
int i = 0;
int level;
dbg_msg("Initializing PIC...\n");
for(i=0; i<PIC_NUM_IRTS; i++) {
for (i = 0; i < PIC_NUM_IRTS; i++) {
level = PIC_IRQ_IS_EDGE_TRIGGERED(i);
/* Bind all PIC irqs to cpu 0 */
xlr_write_reg(mmio, PIC_IRT_0_BASE + i, 0x01);
/* Use local scheduling and high polarity for all IRTs
/*
* Use local scheduling and high polarity for all IRTs
* Invalidate all IRTs, by default
*/
xlr_write_reg(mmio, PIC_IRT_1_BASE + i, (level<<30)|(1<<6)|(PIC_IRQ_BASE + i));
}
xlr_write_reg(mmio, PIC_IRT_1_BASE + i, (level << 30) | (1 << 6) | (PIC_IRQ_BASE + i));
}
}
void on_chip_init(void)
void
on_chip_init(void)
{
int i=0, j=0;
int i = 0, j = 0;
/* Set xlr_io_base to the run time value */
/* Set xlr_io_base to the run time value */
mtx_init(&msgrng_lock, "msgring", NULL, MTX_SPIN | MTX_RECURSE);
mtx_init(&xlr_pic_lock, "pic", NULL, MTX_SPIN);
@ -303,11 +317,11 @@ void on_chip_init(void)
msgring_int_enabled = 0;
xlr_msgring_config();
pic_init();
pic_init();
xlr_msgring_cpu_init();
for(i=0;i<MAXCPU;i++)
for(j=0;j<XLR_MAX_COUNTERS;j++)
for (i = 0; i < MAXCPU; i++)
for (j = 0; j < XLR_MAX_COUNTERS; j++)
atomic_set_int(&xlr_counters[i][j], 0);
}

122
sys/mips/rmi/pcibus.c
View File

@ -66,7 +66,7 @@ static void pic_pcie_ack(void *);
*/
extern vm_map_t kernel_map;
vm_offset_t kmem_alloc_nofault( vm_map_t map, vm_size_t size);
vm_offset_t kmem_alloc_nofault(vm_map_t map, vm_size_t size);
int
@ -76,22 +76,26 @@ mips_pci_route_interrupt(device_t bus, device_t dev, int pin)
* Validate requested pin number.
*/
if ((pin < 1) || (pin > 4))
return(255);
return (255);
if (xlr_board_info.is_xls) {
switch (pin) {
case 1: return PIC_PCIE_LINK0_IRQ;
case 2: return PIC_PCIE_LINK1_IRQ;
case 3: return PIC_PCIE_LINK2_IRQ;
case 4: return PIC_PCIE_LINK3_IRQ;
case 1:
return PIC_PCIE_LINK0_IRQ;
case 2:
return PIC_PCIE_LINK1_IRQ;
case 3:
return PIC_PCIE_LINK2_IRQ;
case 4:
return PIC_PCIE_LINK3_IRQ;
}
} else {
} else {
if (pin == 1) {
return (16);
}
}
return(255);
return (255);
}
static struct rman irq_rman, port_rman, mem_rman;
@ -101,7 +105,7 @@ static void bridge_pcix_ack(void *arg)
{
xlr_read_reg(xlr_io_mmio(XLR_IO_PCIX_OFFSET), 0x140 >> 2);
}
*/
*/
/*
static void bridge_pcie_ack(void *arg)
{
@ -147,10 +151,10 @@ static void pic_pcie_ack(void *arg)
int
mips_platform_pci_setup_intr(device_t dev, device_t child,
struct resource *irq, int flags,
driver_filter_t *filt,
driver_intr_t *intr, void *arg,
void **cookiep)
struct resource *irq, int flags,
driver_filter_t * filt,
driver_intr_t * intr, void *arg,
void **cookiep)
{
int level;
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
@ -162,59 +166,58 @@ mips_platform_pci_setup_intr(device_t dev, device_t child,
return error;
if (rman_get_start(irq) != rman_get_end(irq)) {
device_printf(dev, "Interrupt allocation %lu != %lu\n",
rman_get_start(irq), rman_get_end(irq));
rman_get_start(irq), rman_get_end(irq));
return EINVAL;
}
xlrirq = rman_get_start(irq);
if (strcmp(device_get_name(dev),"pcib") != 0)
if (strcmp(device_get_name(dev), "pcib") != 0)
return 0;
if (xlr_board_info.is_xls == 0) {
mtx_lock_spin(&xlr_pic_lock);
level = PIC_IRQ_IS_EDGE_TRIGGERED(PIC_IRT_PCIX_INDEX);
xlr_write_reg(mmio, PIC_IRT_0_PCIX, 0x01);
xlr_write_reg(mmio, PIC_IRT_1_PCIX, ((1 << 31) | (level<<30)|
(1<<6)|(PIC_PCIX_IRQ)));
xlr_write_reg(mmio, PIC_IRT_1_PCIX, ((1 << 31) | (level << 30) |
(1 << 6) | (PIC_PCIX_IRQ)));
mtx_unlock_spin(&xlr_pic_lock);
cpu_establish_hardintr(device_get_name(child), filt,
(driver_intr_t *)intr, (void *)arg, PIC_PCIX_IRQ, flags, cookiep);
(driver_intr_t *) intr, (void *)arg, PIC_PCIX_IRQ, flags, cookiep);
} else {
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_IRT_0_BASE + xlrirq - PIC_IRQ_BASE, 0x01);
xlr_write_reg(mmio, PIC_IRT_1_BASE + xlrirq - PIC_IRQ_BASE,
((1 << 31) | (1<<30) | (1<<6) | xlrirq));
((1 << 31) | (1 << 30) | (1 << 6) | xlrirq));
mtx_unlock_spin(&xlr_pic_lock);
if (flags & INTR_FAST)
cpu_establish_hardintr(device_get_name(child), filt,
(driver_intr_t *)intr, (void *)arg, xlrirq, flags, cookiep);
if (flags & INTR_FAST)
cpu_establish_hardintr(device_get_name(child), filt,
(driver_intr_t *) intr, (void *)arg, xlrirq, flags, cookiep);
else
cpu_establish_hardintr(device_get_name(child), filt,
(driver_intr_t *)intr, (void *)arg, xlrirq, flags, cookiep);
cpu_establish_hardintr(device_get_name(child), filt,
(driver_intr_t *) intr, (void *)arg, xlrirq, flags, cookiep);
}
return bus_generic_setup_intr(dev, child, irq, flags, filt, intr,
arg, cookiep);
arg, cookiep);
}
int
mips_platform_pci_teardown_intr(device_t dev, device_t child,
struct resource *irq, void *cookie);
struct resource *irq, void *cookie);
int
mips_platform_pci_teardown_intr(device_t dev, device_t child,
struct resource *irq, void *cookie)
struct resource *irq, void *cookie)
{
if (strcmp(device_get_name(child),"pci") == 0) {
if (strcmp(device_get_name(child), "pci") == 0) {
/* if needed reprogram the pic to clear pcix related entry */
}
return bus_generic_teardown_intr(dev, child, irq, cookie);
}
void
void
pci_init_resources(void)
{
irq_rman.rm_start = 0;
@ -249,29 +252,29 @@ pci_init_resources(void)
struct resource *
xlr_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
u_long start, u_long end, u_long count, u_int flags)
u_long start, u_long end, u_long count, u_int flags)
{
struct rman *rm;
struct resource *rv;
struct rman *rm;
struct resource *rv;
vm_offset_t va;
int needactivate = flags & RF_ACTIVE;
int needactivate = flags & RF_ACTIVE;
#if 0
device_printf(bus, "xlr_pci_alloc_resource : child %s, type %d, start %lx end %lx, count %lx, flags %x\n",
device_get_nameunit(child), type, start, end, count, flags);
device_get_nameunit(child), type, start, end, count, flags);
#endif
switch (type) {
case SYS_RES_IRQ:
rm = &irq_rman;
rm = &irq_rman;
break;
case SYS_RES_IOPORT:
rm = &port_rman;
rm = &port_rman;
break;
case SYS_RES_MEMORY:
rm = &mem_rman;
rm = &mem_rman;
break;
default:
@ -282,43 +285,44 @@ xlr_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
if (rv == 0)
return 0;
rman_set_bustag(rv, (bus_space_tag_t)MIPS_BUS_SPACE_PCI);
rman_set_bustag(rv, (bus_space_tag_t) MIPS_BUS_SPACE_PCI);
rman_set_rid(rv, *rid);
if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
/* if ((start + count) > (2 << 28)) {
va_start = kmem_alloc_nofault(kernel_map, count);
}*/
/* This called for pmap_map_uncached, but the pmap_map
* calls pmap_kenter which does a is_cacheable_mem() check and
/*
* if ((start + count) > (2 << 28)) { va_start =
* kmem_alloc_nofault(kernel_map, count); }
*/
/*
* This called for pmap_map_uncached, but the pmap_map calls
* pmap_kenter which does a is_cacheable_mem() check and
* thus sets the PTE_UNCACHED bit. Hopefully this will work
* for this guy... RRS
*/
/* va = pmap_map(&va_start, start, start + count, 0);*/
va = (vm_offset_t)pmap_mapdev(start, start + count);
/* va = pmap_map(&va_start, start, start + count, 0); */
va = (vm_offset_t)pmap_mapdev(start, start + count);
rman_set_bushandle(rv, va);
/* bushandle is same as virtual addr */
rman_set_virtual(rv, (void *)va);
rman_set_bustag(rv, (bus_space_tag_t)MIPS_BUS_SPACE_PCI);
rman_set_bustag(rv, (bus_space_tag_t) MIPS_BUS_SPACE_PCI);
}
if (needactivate) {
if (bus_activate_resource(child, type, *rid, rv)) {
rman_release_resource(rv);
return (NULL);
}
}
if (needactivate) {
if (bus_activate_resource(child, type, *rid, rv)) {
rman_release_resource(rv);
return (NULL);
}
}
return rv;
}
int
pci_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
struct resource *r)
{
return (rman_deactivate_resource(r));
}
/* now in pci.c
int
pci_activate_resource(device_t bus, device_t child, int type, int rid,
@ -339,7 +343,7 @@ struct rman *
pci_get_rman(device_t dev, int type)
{
switch (type) {
case SYS_RES_IOPORT:
case SYS_RES_IOPORT:
return &port_rman;
case SYS_RES_MEMORY:

34
sys/mips/rmi/pcibus.h
View File

@ -36,23 +36,27 @@
#define PCIE_LINK3_MSI_STATUS 0x194
void pci_init_resources(void);
struct resource *xlr_pci_alloc_resource(device_t bus, device_t child,
int type, int *rid,
u_long start, u_long end, u_long count,
u_int flags);
int pci_activate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r);
int pci_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r);
int pci_release_resource(device_t bus, device_t child, int type, int rid,
struct resource *r);
struct resource *
xlr_pci_alloc_resource(device_t bus, device_t child,
int type, int *rid,
u_long start, u_long end, u_long count,
u_int flags);
int
pci_activate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r);
int
pci_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r);
int
pci_release_resource(device_t bus, device_t child, int type, int rid,
struct resource *r);
struct rman *pci_get_rman(device_t dev, int type);
int
mips_platform_pci_setup_intr(device_t dev, device_t child,
struct resource *irq, int flags,
driver_filter_t *filt,
driver_intr_t *intr, void *arg,
void **cookiep);
struct resource *irq, int flags,
driver_filter_t * filt,
driver_intr_t * intr, void *arg,
void **cookiep);
int
mips_pci_route_interrupt(device_t bus, device_t dev, int pin);
mips_pci_route_interrupt(device_t bus, device_t dev, int pin);

77
sys/mips/rmi/perfmon.h
View File

@ -33,18 +33,21 @@
#include <mips/rmi/perfmon_xlrconfig.h>
/*
/*
* category events reported by the perfmon library
*/
enum event_category_t { PERF_CP0_COUNTER=1, PERF_CP2_CREDITS, PERF_L2_COUNTER,
PERF_SBC_COUNTER, PERF_SBC_CREDITS, PERF_GMAC0_COUNTER, PERF_GMAC1_COUNTER,
PERF_GMAC2_COUNTER, PERF_GMAC_STAT_COM, PERF_GMAC_STAT_TX,
PERF_GMAC_STAT_RX, PERF_DRAM_COUNTER, PERF_PARAMETER_CONF=127};
enum event_category_t {
PERF_CP0_COUNTER = 1, PERF_CP2_CREDITS, PERF_L2_COUNTER,
PERF_SBC_COUNTER, PERF_SBC_CREDITS, PERF_GMAC0_COUNTER, PERF_GMAC1_COUNTER,
PERF_GMAC2_COUNTER, PERF_GMAC_STAT_COM, PERF_GMAC_STAT_TX,
PERF_GMAC_STAT_RX, PERF_DRAM_COUNTER, PERF_PARAMETER_CONF = 127};
enum perf_param_t { PERF_CPU_SAMPLING_INTERVAL, PERF_SYS_SAMPLING_INTERVAL, PERF_CC_SAMPLE_RATE, PERF_CP0_FLAGS};
enum perf_param_t {
PERF_CPU_SAMPLING_INTERVAL, PERF_SYS_SAMPLING_INTERVAL, PERF_CC_SAMPLE_RATE, PERF_CP0_FLAGS
};
#define CPO_EVENTS_TEMPLATE 0x06 /* enable kernel and user events */
#define CPO_EVENTS_TEMPLATE 0x06 /* enable kernel and user events */
#define PERFMON_ACTIVE_MAGIC 0xc001
#define PERFMON_ENABLED_MAGIC 0xb007
@ -52,17 +55,20 @@ enum perf_param_t { PERF_CPU_SAMPLING_INTERVAL, PERF_SYS_SAMPLING_INTERVAL, PERF
#define PERFMON_SERVER_PORT 7007
enum system_bridge_credits_t {PCIX_CREDITS, HT_CREDITS, GIO_CREDITS, OTHER_CREDITS};
enum system_bridge_credits_t {
PCIX_CREDITS, HT_CREDITS, GIO_CREDITS, OTHER_CREDITS
};
struct perf_config_data {
uint16_t magic; /* monitor start when this is initialized */
uint16_t generation; /* incremented when the config changes */
uint16_t magic; /* monitor start when this is initialized */
uint16_t generation; /* incremented when the config changes */
uint16_t flags;
uint16_t cc_sample_rate; /* rate at which credit counters are sampled
relative to sampling_rate */
uint32_t sampling_rate; /* rate at which events are sampled */
uint32_t cc_register_mask; /* credit counters registers to be sampled */
uint64_t events[NTHREADS]; /* events bitmap for each thread */
uint16_t cc_sample_rate;/* rate at which credit counters are sampled
* relative to sampling_rate */
uint32_t sampling_rate; /* rate at which events are sampled */
uint32_t cc_register_mask; /* credit counters registers to be
* sampled */
uint64_t events[NTHREADS]; /* events bitmap for each thread */
};
struct perf_sample {
@ -78,34 +84,39 @@ struct sample_q {
uint32_t overflows;
};
struct perf_area {
struct perf_area {
struct perf_config_data perf_config;
struct sample_q sample_fifo;
};
/*
* We have a shared location to keep a global tick counter for all the
* We have a shared location to keep a global tick counter for all the
* CPUS - TODO is this optimal? effect on cache?
*/
extern uint32_t *xlr_perfmon_timer_loc;
#define PERFMON_TIMESTAMP_LOC (xlr_perfmon_timer_loc)
static __inline__ uint32_t perfmon_timestamp_get(void)
static __inline__ uint32_t
perfmon_timestamp_get(void)
{
return *PERFMON_TIMESTAMP_LOC;
}
static __inline__ void perfmon_timestamp_set(uint32_t val)
static __inline__ void
perfmon_timestamp_set(uint32_t val)
{
*PERFMON_TIMESTAMP_LOC = val;
}
static __inline__ void perfmon_timestamp_incr(int val)
static __inline__ void
perfmon_timestamp_incr(int val)
{
(*PERFMON_TIMESTAMP_LOC) += val;
}
static __inline__ void send_sample_gts(uint32_t tag, uint32_t value, uint32_t td)
static __inline__ void
send_sample_gts(uint32_t tag, uint32_t value, uint32_t td)
{
xlr_send_sample(tag, value, perfmon_timestamp_get(), td);
}
@ -114,21 +125,23 @@ static __inline__ void send_sample_gts(uint32_t tag, uint32_t value, uint32_t td
* Simple FIFO, one producer - one consumer - circlar queue - no locking
*/
static __inline__ void init_fifo(struct sample_q *q)
static __inline__ void
init_fifo(struct sample_q *q)
{
q->head = q->tail = 0;
}
static __inline__ void put_sample(struct sample_q *q, uint32_t sample_tag, uint32_t counter,
uint32_t duration)
static __inline__ void
put_sample(struct sample_q *q, uint32_t sample_tag, uint32_t counter,
uint32_t duration)
{
uint32_t timestamp = perfmon_timestamp_get();
int new_tail = (q->tail + 1) % PERF_SAMPLE_BUFSZ;
if (q->head == new_tail) {
q->overflows++;
return;
}
q->samples[new_tail].sample_tag = sample_tag;
q->samples[new_tail].counter = counter;
q->samples[new_tail].timestamp = timestamp;
@ -137,8 +150,9 @@ static __inline__ void put_sample(struct sample_q *q, uint32_t sample_tag, uint3
q->tail = new_tail;
}
static __inline__ int get_sample(struct sample_q *q, uint32_t *sample_tag, uint32_t *counter,
uint32_t *timestamp, uint32_t *duration)
static __inline__ int
get_sample(struct sample_q *q, uint32_t * sample_tag, uint32_t * counter,
uint32_t * timestamp, uint32_t * duration)
{
int head = q->head;
@ -149,11 +163,12 @@ static __inline__ int get_sample(struct sample_q *q, uint32_t *sample_tag, uint3
*timestamp = q->samples[head].timestamp;
*duration = q->samples[head].duration;
q->head = (head+1) % PERF_SAMPLE_BUFSZ;
q->head = (head + 1) % PERF_SAMPLE_BUFSZ;
return 1;
}
static __inline__ void clear_queue(struct sample_q *q)
static __inline__ void
clear_queue(struct sample_q *q)
{
q->head = q->tail;
}
@ -162,7 +177,7 @@ void xlr_perfmon_sampler(void *);
void log_active_core(int core);
int get_start_generation(void);
void xlr_perfmon_clockhandler (void);
void xlr_perfmon_clockhandler(void);
extern int xlr_perfmon_started;
#endif /* PERFMON_H */
#endif /* PERFMON_H */

63
sys/mips/rmi/perfmon_kern.c
View File

@ -46,53 +46,56 @@
int xlr_perfmon_started = 0;
struct perf_area *xlr_shared_config_area = NULL;
uint32_t *xlr_perfmon_timer_loc;
uint32_t *xlr_cpu_sampling_interval;
uint32_t xlr_perfmon_kernel_version = 1; /* Future use */
uint32_t *xlr_cpu_sampling_interval;
uint32_t xlr_perfmon_kernel_version = 1; /* Future use */
uint32_t xlr_perfmon_ticks;
extern int mips_cpu_online_mask;
extern uint32_t cpu_ltop_map[MAXCPU];
#ifdef SMP
static __inline__ void pic_send_perfmon_ipi(int cpu)
static __inline__ void
pic_send_perfmon_ipi(int cpu)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
int tid, pid;
uint32_t ipi;
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
int tid, pid;
uint32_t ipi;
tid = cpu & 0x3;
pid = (cpu >> 2) & 0x7;
ipi = (pid << 20) | (tid << 16) | IPI_PERFMON;
tid = cpu & 0x3;
pid = (cpu >> 2) & 0x7;
ipi = (pid << 20) | (tid << 16) | IPI_PERFMON;
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_IPI, ipi);
mtx_unlock_spin(&xlr_pic_lock);
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_IPI, ipi);
mtx_unlock_spin(&xlr_pic_lock);
}
#endif
#endif
void
void
xlr_perfmon_clockhandler(void)
{
#ifdef SMP
int cpu;
int i;
#endif
if (xlr_perfmon_ticks++ >= (*xlr_cpu_sampling_interval)/(XLR_PIC_HZ/(hz * 1024))) {
if (xlr_perfmon_ticks++ >= (*xlr_cpu_sampling_interval) / (XLR_PIC_HZ / (hz * 1024))) {
/* update timer */
*xlr_perfmon_timer_loc += *xlr_cpu_sampling_interval;
xlr_perfmon_ticks = 0;
xlr_perfmon_sampler(NULL);
#ifdef SMP
for (i=0; i<NCPUS; i = i+NTHREADS) { /* oly thread 0 */
for (i = 0; i < NCPUS; i = i + NTHREADS) { /* oly thread 0 */
cpu = cpu_ltop_map[i];
if ((mips_cpu_online_mask & (1 << i)) &&
xlr_shared_config_area[cpu/NTHREADS].perf_config.magic ==
xlr_shared_config_area[cpu / NTHREADS].perf_config.magic ==
PERFMON_ACTIVE_MAGIC)
pic_send_perfmon_ipi(cpu);
}
#endif
}
@ -103,27 +106,26 @@ xlr_perfmon_start(void)
{
size_t size;
size = (NCORES * sizeof(*xlr_shared_config_area)) +
sizeof(*xlr_perfmon_timer_loc) +
sizeof(*xlr_cpu_sampling_interval);
size = (NCORES * sizeof(*xlr_shared_config_area)) +
sizeof(*xlr_perfmon_timer_loc) +
sizeof(*xlr_cpu_sampling_interval);
xlr_shared_config_area = malloc(size, M_TEMP, M_WAITOK);
if (!xlr_shared_config_area) {
/* ERROR */
return;
}
xlr_perfmon_timer_loc = (uint32_t *)(xlr_shared_config_area + NCORES);
xlr_cpu_sampling_interval = (uint32_t *)(xlr_perfmon_timer_loc +1);
xlr_perfmon_timer_loc = (uint32_t *) (xlr_shared_config_area + NCORES);
xlr_cpu_sampling_interval = (uint32_t *) (xlr_perfmon_timer_loc + 1);
*xlr_cpu_sampling_interval = DEFAULT_CPU_SAMPLING_INTERVAL;
*xlr_perfmon_timer_loc = 0;
xlr_perfmon_ticks = 0;
xlr_perfmon_init_cpu(NULL);
xlr_perfmon_init_cpu(NULL);
#ifdef SMP
smp_call_function(xlr_perfmon_init_cpu, NULL,
PCPU_GET(other_cpus) & 0x11111111);
smp_call_function(xlr_perfmon_init_cpu, NULL,
PCPU_GET(other_cpus) & 0x11111111);
#endif
xlr_perfmon_started = 1;
@ -143,7 +145,7 @@ sysctl_xlr_perfmon_start_stop(SYSCTL_HANDLER_ARGS)
int error, val = xlr_perfmon_started;
error = sysctl_handle_int(oidp, &val, 0, req);
if (error != 0 || req->newptr == NULL)
if (error != 0 || req->newptr == NULL)
return (error);
if (!xlr_perfmon_started && val != 0)
@ -157,6 +159,5 @@ sysctl_xlr_perfmon_start_stop(SYSCTL_HANDLER_ARGS)
SYSCTL_NODE(_debug, OID_AUTO, xlrperf, CTLFLAG_RW, NULL, "XLR PERF Nodes");
SYSCTL_PROC(_debug_xlrperf, OID_AUTO, start, CTLTYPE_INT | CTLFLAG_RW,
&xlr_perfmon_started, 0, sysctl_xlr_perfmon_start_stop, "I", "set/unset to start/stop "
"performance monitoring");
&xlr_perfmon_started, 0, sysctl_xlr_perfmon_start_stop, "I", "set/unset to start/stop "
"performance monitoring");

199
sys/mips/rmi/perfmon_percpu.c
View File

@ -62,27 +62,32 @@
extern uint32_t cpu_ltop_map[MAXCPU];
extern struct perf_area *xlr_shared_config_area;
static __inline__ uint32_t make_cpu_tag(uint32_t val)
static __inline__ uint32_t
make_cpu_tag(uint32_t val)
{
return PERF_CP0_COUNTER<<24 | (val & 0xffff);
return PERF_CP0_COUNTER << 24 | (val & 0xffff);
}
static __inline__ uint32_t make_cp0_perf_control(uint32_t flags, uint32_t thread, uint32_t event)
static __inline__ uint32_t
make_cp0_perf_control(uint32_t flags, uint32_t thread, uint32_t event)
{
return (flags & 0x1f) | (thread & 0x03)<<11 | (event & 0x3f)<<5 | 0x01;
return (flags & 0x1f) | (thread & 0x03) << 11 | (event & 0x3f) << 5 | 0x01;
}
static __inline__ uint32_t cp0_perf_control_get_thread(uint32_t control_word)
static __inline__ uint32_t
cp0_perf_control_get_thread(uint32_t control_word)
{
return (control_word & 0x1800)>>11;
return (control_word & 0x1800) >> 11;
}
static __inline__ uint32_t cp0_perf_control_get_event(uint32_t control_word)
static __inline__ uint32_t
cp0_perf_control_get_event(uint32_t control_word)
{
return (control_word & 0x7e0)>>5;
return (control_word & 0x7e0) >> 5;
}
static __inline__ uint32_t read_pic_6_timer_count(void)
static __inline__ uint32_t
read_pic_6_timer_count(void)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
@ -91,12 +96,13 @@ static __inline__ uint32_t read_pic_6_timer_count(void)
}
static uint32_t get_num_events(const uint64_t *events)
static uint32_t
get_num_events(const uint64_t * events)
{
int total = 0;
int thread;
for(thread = 0; thread<NTHREADS; thread++) {
for (thread = 0; thread < NTHREADS; thread++) {
if (events[thread] == 0)
continue;
total += get_set_bit_count64(events[thread]);
@ -104,28 +110,31 @@ static uint32_t get_num_events(const uint64_t *events)
return total;
}
static uint32_t get_first_control_word(uint32_t flags, const uint64_t *events)
static uint32_t
get_first_control_word(uint32_t flags, const uint64_t * events)
{
int thread, event;
for(thread = 0; thread<NTHREADS; thread++) {
if (events[thread] != 0) break;
for (thread = 0; thread < NTHREADS; thread++) {
if (events[thread] != 0)
break;
}
if(thread == NTHREADS)
if (thread == NTHREADS)
return -1;
event = find_first_set_bit64(events[thread]);
return make_cp0_perf_control(flags, thread, event);
}
static uint32_t get_next_control_word(uint32_t current_control_word, const uint64_t *events)
static uint32_t
get_next_control_word(uint32_t current_control_word, const uint64_t * events)
{
int thread = cp0_perf_control_get_thread(current_control_word);
int event = cp0_perf_control_get_event(current_control_word);
int i;
event = find_next_set_bit64(events[thread], event);
for(i = 0; event == -1 && i<NTHREADS; i++) {
for (i = 0; event == -1 && i < NTHREADS; i++) {
thread = (thread + 1) % NTHREADS;
if (events[thread] == 0)
continue;
@ -140,58 +149,92 @@ static uint32_t get_next_control_word(uint32_t current_control_word, const uint6
#define MY_CORE_NUM (cpu_ltop_map[PCPU_GET(cpuid)]/NTHREADS)
#define my_perf_area (&(xlr_shared_config_area[MY_CORE_NUM]))
static int num_events_array[NCORES];
static uint32_t saved_timestamp_array[NCORES];
static struct perf_config_data saved_config_array[NCORES];
static int cc_sample_array[NCORES];
static int num_events_array[NCORES];
static uint32_t saved_timestamp_array[NCORES];
static struct perf_config_data saved_config_array[NCORES];
static int cc_sample_array[NCORES];
#define num_events (num_events_array[MY_CORE_NUM])
#define saved_timestamp (saved_timestamp_array[MY_CORE_NUM])
#define saved_config (saved_config_array[MY_CORE_NUM])
#define cc_sample (cc_sample_array[MY_CORE_NUM])
static void do_sample_cc_registers(struct sample_q *q, uint32_t mask)
static void
do_sample_cc_registers(struct sample_q *q, uint32_t mask)
{
unsigned long flags;
DPRINT("Sample CC registers %x", mask);
msgrng_flags_save(flags);
if (mask & 0x00000001) put_sample(q, CC_SAMPLE + 0, read_cc_registers_0123(CC_REG0), 0);
if (mask & 0x00000002) put_sample(q, CC_SAMPLE + 1, read_cc_registers_4567(CC_REG0), 0);
if (mask & 0x00000004) put_sample(q, CC_SAMPLE + 2, read_cc_registers_0123(CC_REG1), 0);
if (mask & 0x00000008) put_sample(q, CC_SAMPLE + 3, read_cc_registers_4567(CC_REG1), 0);
if (mask & 0x00000010) put_sample(q, CC_SAMPLE + 4, read_cc_registers_0123(CC_REG2), 0);
if (mask & 0x00000020) put_sample(q, CC_SAMPLE + 5, read_cc_registers_4567(CC_REG2), 0);
if (mask & 0x00000040) put_sample(q, CC_SAMPLE + 6, read_cc_registers_0123(CC_REG3), 0);
if (mask & 0x00000080) put_sample(q, CC_SAMPLE + 7, read_cc_registers_4567(CC_REG3), 0);
if (mask & 0x00000100) put_sample(q, CC_SAMPLE + 8, read_cc_registers_0123(CC_REG4), 0);
if (mask & 0x00000200) put_sample(q, CC_SAMPLE + 9, read_cc_registers_4567(CC_REG4), 0);
if (mask & 0x00000400) put_sample(q, CC_SAMPLE + 10, read_cc_registers_0123(CC_REG5), 0);
if (mask & 0x00000800) put_sample(q, CC_SAMPLE + 11, read_cc_registers_4567(CC_REG5), 0);
if (mask & 0x00001000) put_sample(q, CC_SAMPLE + 12, read_cc_registers_0123(CC_REG6), 0);
if (mask & 0x00002000) put_sample(q, CC_SAMPLE + 13, read_cc_registers_4567(CC_REG6), 0);
if (mask & 0x00004000) put_sample(q, CC_SAMPLE + 14, read_cc_registers_0123(CC_REG7), 0);
if (mask & 0x00008000) put_sample(q, CC_SAMPLE + 15, read_cc_registers_4567(CC_REG7), 0);
if (mask & 0x00010000) put_sample(q, CC_SAMPLE + 16, read_cc_registers_0123(CC_REG8), 0);
if (mask & 0x00020000) put_sample(q, CC_SAMPLE + 17, read_cc_registers_4567(CC_REG8), 0);
if (mask & 0x00040000) put_sample(q, CC_SAMPLE + 18, read_cc_registers_0123(CC_REG9), 0);
if (mask & 0x00080000) put_sample(q, CC_SAMPLE + 19, read_cc_registers_4567(CC_REG9), 0);
if (mask & 0x00100000) put_sample(q, CC_SAMPLE + 20, read_cc_registers_0123(CC_REG10), 0);
if (mask & 0x00200000) put_sample(q, CC_SAMPLE + 21, read_cc_registers_4567(CC_REG10), 0);
if (mask & 0x00400000) put_sample(q, CC_SAMPLE + 22, read_cc_registers_0123(CC_REG11), 0);
if (mask & 0x00800000) put_sample(q, CC_SAMPLE + 23, read_cc_registers_4567(CC_REG11), 0);
if (mask & 0x01000000) put_sample(q, CC_SAMPLE + 24, read_cc_registers_0123(CC_REG12), 0);
if (mask & 0x02000000) put_sample(q, CC_SAMPLE + 24, read_cc_registers_4567(CC_REG12), 0);
if (mask & 0x04000000) put_sample(q, CC_SAMPLE + 26, read_cc_registers_0123(CC_REG13), 0);
if (mask & 0x08000000) put_sample(q, CC_SAMPLE + 27, read_cc_registers_4567(CC_REG13), 0);
if (mask & 0x10000000) put_sample(q, CC_SAMPLE + 28, read_cc_registers_0123(CC_REG14), 0);
if (mask & 0x20000000) put_sample(q, CC_SAMPLE + 29, read_cc_registers_4567(CC_REG14), 0);
if (mask & 0x40000000) put_sample(q, CC_SAMPLE + 30, read_cc_registers_0123(CC_REG15), 0);
if (mask & 0x80000000) put_sample(q, CC_SAMPLE + 31, read_cc_registers_4567(CC_REG15), 0);
if (mask & 0x00000001)
put_sample(q, CC_SAMPLE + 0, read_cc_registers_0123(CC_REG0), 0);
if (mask & 0x00000002)
put_sample(q, CC_SAMPLE + 1, read_cc_registers_4567(CC_REG0), 0);
if (mask & 0x00000004)
put_sample(q, CC_SAMPLE + 2, read_cc_registers_0123(CC_REG1), 0);
if (mask & 0x00000008)
put_sample(q, CC_SAMPLE + 3, read_cc_registers_4567(CC_REG1), 0);
if (mask & 0x00000010)
put_sample(q, CC_SAMPLE + 4, read_cc_registers_0123(CC_REG2), 0);
if (mask & 0x00000020)
put_sample(q, CC_SAMPLE + 5, read_cc_registers_4567(CC_REG2), 0);
if (mask & 0x00000040)
put_sample(q, CC_SAMPLE + 6, read_cc_registers_0123(CC_REG3), 0);
if (mask & 0x00000080)
put_sample(q, CC_SAMPLE + 7, read_cc_registers_4567(CC_REG3), 0);
if (mask & 0x00000100)
put_sample(q, CC_SAMPLE + 8, read_cc_registers_0123(CC_REG4), 0);
if (mask & 0x00000200)
put_sample(q, CC_SAMPLE + 9, read_cc_registers_4567(CC_REG4), 0);
if (mask & 0x00000400)
put_sample(q, CC_SAMPLE + 10, read_cc_registers_0123(CC_REG5), 0);
if (mask & 0x00000800)
put_sample(q, CC_SAMPLE + 11, read_cc_registers_4567(CC_REG5), 0);
if (mask & 0x00001000)
put_sample(q, CC_SAMPLE + 12, read_cc_registers_0123(CC_REG6), 0);
if (mask & 0x00002000)
put_sample(q, CC_SAMPLE + 13, read_cc_registers_4567(CC_REG6), 0);
if (mask & 0x00004000)
put_sample(q, CC_SAMPLE + 14, read_cc_registers_0123(CC_REG7), 0);
if (mask & 0x00008000)
put_sample(q, CC_SAMPLE + 15, read_cc_registers_4567(CC_REG7), 0);
if (mask & 0x00010000)
put_sample(q, CC_SAMPLE + 16, read_cc_registers_0123(CC_REG8), 0);
if (mask & 0x00020000)
put_sample(q, CC_SAMPLE + 17, read_cc_registers_4567(CC_REG8), 0);
if (mask & 0x00040000)
put_sample(q, CC_SAMPLE + 18, read_cc_registers_0123(CC_REG9), 0);
if (mask & 0x00080000)
put_sample(q, CC_SAMPLE + 19, read_cc_registers_4567(CC_REG9), 0);
if (mask & 0x00100000)
put_sample(q, CC_SAMPLE + 20, read_cc_registers_0123(CC_REG10), 0);
if (mask & 0x00200000)
put_sample(q, CC_SAMPLE + 21, read_cc_registers_4567(CC_REG10), 0);
if (mask & 0x00400000)
put_sample(q, CC_SAMPLE + 22, read_cc_registers_0123(CC_REG11), 0);
if (mask & 0x00800000)
put_sample(q, CC_SAMPLE + 23, read_cc_registers_4567(CC_REG11), 0);
if (mask & 0x01000000)
put_sample(q, CC_SAMPLE + 24, read_cc_registers_0123(CC_REG12), 0);
if (mask & 0x02000000)
put_sample(q, CC_SAMPLE + 24, read_cc_registers_4567(CC_REG12), 0);
if (mask & 0x04000000)
put_sample(q, CC_SAMPLE + 26, read_cc_registers_0123(CC_REG13), 0);
if (mask & 0x08000000)
put_sample(q, CC_SAMPLE + 27, read_cc_registers_4567(CC_REG13), 0);
if (mask & 0x10000000)
put_sample(q, CC_SAMPLE + 28, read_cc_registers_0123(CC_REG14), 0);
if (mask & 0x20000000)
put_sample(q, CC_SAMPLE + 29, read_cc_registers_4567(CC_REG14), 0);
if (mask & 0x40000000)
put_sample(q, CC_SAMPLE + 30, read_cc_registers_0123(CC_REG15), 0);
if (mask & 0x80000000)
put_sample(q, CC_SAMPLE + 31, read_cc_registers_4567(CC_REG15), 0);
msgrng_flags_restore(flags);
}
static void reconfigure(void)
static void
reconfigure(void)
{
uint32_t cntr_cntrl;
@ -200,19 +243,19 @@ static void reconfigure(void)
cc_sample = saved_config.cc_sample_rate;
DPRINT("%d - reconfigure num_events = %d, events = %llx,%llx,%llx,%llx\n",
processor_id(), num_events, saved_config.events[0],
saved_config.events[1],saved_config.events[2],saved_config.events[3] );
processor_id(), num_events, saved_config.events[0],
saved_config.events[1], saved_config.events[2], saved_config.events[3]);
if (num_events == 0)
return;
cntr_cntrl = get_first_control_word(saved_config.flags, saved_config.events);
write_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL0, cntr_cntrl);
write_c0_register(CP0_PERF_COUNTER, PERFCNTR0, 0); /* reset count */
write_c0_register(CP0_PERF_COUNTER, PERFCNTR0, 0); /* reset count */
if (num_events > 1) {
cntr_cntrl = get_next_control_word(cntr_cntrl, saved_config.events);
write_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL1, cntr_cntrl);
write_c0_register(CP0_PERF_COUNTER, PERFCNTR1, 0); /* reset count */
write_c0_register(CP0_PERF_COUNTER, PERFCNTR1, 0); /* reset count */
}
saved_timestamp = read_pic_6_timer_count();
}
@ -221,51 +264,50 @@ int xlr_perfmon_no_event_count = 0;
int xlr_perfmon_sample_count;
/* timer callback routine */
void xlr_perfmon_sampler(void *dummy)
void
xlr_perfmon_sampler(void *dummy)
{
uint32_t current_ts;
uint32_t cntr_cntrl=0;
uint32_t cntr_cntrl = 0;
/* xlr_ack_interrupt(XLR_PERFMON_IPI_VECTOR); */
if (my_perf_area->perf_config.magic != PERFMON_ACTIVE_MAGIC)
return;
/*
* If there has been a change in configuation, update the configuration
*/
* If there has been a change in configuation, update the
* configuration
*/
if (saved_config.generation != my_perf_area->perf_config.generation) {
reconfigure();
return;
}
/* credit counter samples if reqd */
if(saved_config.cc_register_mask && --cc_sample == 0) {
if (saved_config.cc_register_mask && --cc_sample == 0) {
cc_sample = saved_config.cc_sample_rate;
do_sample_cc_registers(&my_perf_area->sample_fifo,
my_perf_area->perf_config.cc_register_mask);
do_sample_cc_registers(&my_perf_area->sample_fifo,
my_perf_area->perf_config.cc_register_mask);
}
if (num_events == 0) {
xlr_perfmon_no_event_count++;
return;
}
/* put samples in the queue */
current_ts = read_pic_6_timer_count();
cntr_cntrl = read_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL0);
put_sample(&my_perf_area->sample_fifo, make_cpu_tag(cntr_cntrl),
read_c0_register(CP0_PERF_COUNTER, PERFCNTR0), current_ts - saved_timestamp);
read_c0_register(CP0_PERF_COUNTER, PERFCNTR0), current_ts - saved_timestamp);
xlr_perfmon_sample_count++;
write_c0_register(CP0_PERF_COUNTER, PERFCNTR0, 0); /* reset count */
write_c0_register(CP0_PERF_COUNTER, PERFCNTR0, 0); /* reset count */
if(num_events > 1) {
if (num_events > 1) {
cntr_cntrl = read_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL1);
put_sample(&my_perf_area->sample_fifo, make_cpu_tag(cntr_cntrl),
read_c0_register(CP0_PERF_COUNTER, PERFCNTR1), current_ts - saved_timestamp);
read_c0_register(CP0_PERF_COUNTER, PERFCNTR1), current_ts - saved_timestamp);
xlr_perfmon_sample_count++;
write_c0_register(CP0_PERF_COUNTER, PERFCNTR1, 0); /* reset count */
write_c0_register(CP0_PERF_COUNTER, PERFCNTR1, 0); /* reset count */
if(num_events > 2) {
if (num_events > 2) {
/* multiplex events */
cntr_cntrl = get_next_control_word(cntr_cntrl, saved_config.events);
write_c0_register(CP0_PERF_COUNTER, PERFCNTRCTL0, cntr_cntrl);
@ -280,12 +322,13 @@ void xlr_perfmon_sampler(void *dummy)
/*
* Initializes time to gather CPU performance counters and credit counters
*/
void xlr_perfmon_init_cpu(void *dummy)
void
xlr_perfmon_init_cpu(void *dummy)
{
int processor = cpu_ltop_map[PCPU_GET(cpuid)];
/* run on just one thread per core */
if(processor % 4)
if (processor % 4)
return;
DPRINT("%d : configure with %p", processor, my_perf_area);
@ -295,5 +338,5 @@ void xlr_perfmon_init_cpu(void *dummy)
my_perf_area->perf_config.generation = PERFMON_INITIAL_GENERATION;
DPRINT("%d : Initialize", processor);
return ;
return;
}

57
sys/mips/rmi/perfmon_utils.h
View File

@ -31,74 +31,87 @@
#ifndef UTILS_H
#define UTILS_H
#include <machine/stdarg.h> /* variable args */
#include <machine/stdarg.h> /* variable args */
/* TODO optimize of mips, even i & (i-1) is better */
static int __inline__ get_set_bit_count64(uint64_t value)
static int __inline__
get_set_bit_count64(uint64_t value)
{
int i, result=0;
int i, result = 0;
for(i=0; i<sizeof(value) *8; i++)
if(value & (1ULL<<i)) result++;
for (i = 0; i < sizeof(value) * 8; i++)
if (value & (1ULL << i))
result++;
return result;
}
static int __inline__ find_first_set_bit64(uint64_t value)
static int __inline__
find_first_set_bit64(uint64_t value)
{
int i;
for(i=0; i<sizeof(value) *8; i++)
if(value & (1ULL<<i)) return i;
for (i = 0; i < sizeof(value) * 8; i++)
if (value & (1ULL << i))
return i;
return -1;
}
static int __inline__ find_next_set_bit64(uint64_t value, int pos)
static int __inline__
find_next_set_bit64(uint64_t value, int pos)
{
int i;
for(i=pos+1; i<sizeof(value) *8; i++)
if(value & (1ULL<<i)) return i;
for (i = pos + 1; i < sizeof(value) * 8; i++)
if (value & (1ULL << i))
return i;
return -1;
}
/** --- **/
static int __inline__ get_set_bit_count(uint32_t value)
static int __inline__
get_set_bit_count(uint32_t value)
{
int i, result=0;
int i, result = 0;
for(i=0; i<sizeof(value) *8; i++)
if(value & (1U<<i)) result++;
for (i = 0; i < sizeof(value) * 8; i++)
if (value & (1U << i))
result++;
return result;
}
static int __inline__ find_first_set_bit(uint32_t value)
static int __inline__
find_first_set_bit(uint32_t value)
{
int i;
for(i=0; i<sizeof(value) *8; i++)
if(value & (1U<<i)) return i;
for (i = 0; i < sizeof(value) * 8; i++)
if (value & (1U << i))
return i;
return -1;
}
static int __inline__ find_next_set_bit(uint32_t value, int pos)
static int __inline__
find_next_set_bit(uint32_t value, int pos)
{
int i;
for(i=pos+1; i<sizeof(value) *8; i++)
if(value & (1U<<i)) return i;
for (i = pos + 1; i < sizeof(value) * 8; i++)
if (value & (1U << i))
return i;
return -1;
}
#ifdef DEBUG
void abort();
#define DPUTC(c) (putchar(c) && fflush(stdout))
#define DPRINT(fmt, ...) printf(fmt "\n", __VA_ARGS__)
#define ASSERT(x) ((x) || ({ printf("%s failed at (%s:%d)", #x, __FILE__, __LINE__) ; abort(); 0; }) )

2
sys/mips/rmi/perfmon_xlrconfig.h
View File

@ -33,7 +33,7 @@
#ifndef XLRCONFIG_PERFMON_H
#define XLRCONFIG_PERFMON_H
#include <mips/rmi/perfmon_utils.h> /* for DPRINT */
#include <mips/rmi/perfmon_utils.h> /* for DPRINT */
#define NCPUS 32
#define NCORES 8

87
sys/mips/rmi/pic.h
View File

@ -200,58 +200,69 @@
extern struct mtx xlr_pic_lock;
static __inline__ __uint32_t pic_read_control(void)
static __inline__ __uint32_t
pic_read_control(void)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
__uint32_t reg;
mtx_lock_spin(&xlr_pic_lock);
xlr_read_reg(mmio, PIC_CTRL);
mtx_unlock_spin(&xlr_pic_lock);
return reg;
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
__uint32_t reg;
mtx_lock_spin(&xlr_pic_lock);
xlr_read_reg(mmio, PIC_CTRL);
mtx_unlock_spin(&xlr_pic_lock);
return reg;
}
static __inline__ void pic_write_control(__uint32_t control)
static __inline__ void
pic_write_control(__uint32_t control)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_CTRL, control);
mtx_unlock_spin(&xlr_pic_lock);
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_CTRL, control);
mtx_unlock_spin(&xlr_pic_lock);
}
static __inline__ void pic_update_control(__uint32_t control)
static __inline__ void
pic_update_control(__uint32_t control)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_CTRL, (control | xlr_read_reg(mmio, PIC_CTRL)));
mtx_unlock_spin(&xlr_pic_lock);
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_CTRL, (control | xlr_read_reg(mmio, PIC_CTRL)));
mtx_unlock_spin(&xlr_pic_lock);
}
static __inline__ void pic_ack(int irq)
static __inline__ void
pic_ack(int irq)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
/* ack the pic, if needed */
if (!PIC_IRQ_IS_IRT(irq)) return;
/* ack the pic, if needed */
if (!PIC_IRQ_IS_IRT(irq))
return;
if(PIC_IRQ_IS_EDGE_TRIGGERED(irq)) {
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE) ));
mtx_unlock_spin(&xlr_pic_lock);
return;
}
return;
if (PIC_IRQ_IS_EDGE_TRIGGERED(irq)) {
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
mtx_unlock_spin(&xlr_pic_lock);
return;
}
return;
}
static inline void pic_delayed_ack(int irq)
static inline void
pic_delayed_ack(int irq)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
if (!PIC_IRQ_IS_IRT(irq)) return;
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
if(!PIC_IRQ_IS_EDGE_TRIGGERED(irq)) {
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE) ));
mtx_unlock_spin(&xlr_pic_lock);
return;
}
if (!PIC_IRQ_IS_IRT(irq))
return;
if (!PIC_IRQ_IS_EDGE_TRIGGERED(irq)) {
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_INT_ACK, (1 << (irq - PIC_IRQ_BASE)));
mtx_unlock_spin(&xlr_pic_lock);
return;
}
}
#endif /* _RMI_PIC_H_ */
#endif /* _RMI_PIC_H_ */

90
sys/mips/rmi/shared_structs.h
View File

@ -36,42 +36,42 @@
#define BOOT1_INFO_VERSION 0x0001
struct boot1_info {
uint64_t boot_level;
uint64_t io_base;
uint64_t output_device;
uint64_t uart_print;
uint64_t led_output;
uint64_t init;
uint64_t exit;
uint64_t warm_reset;
uint64_t wakeup;
uint64_t cpu_online_map;
uint64_t master_reentry_sp;
uint64_t master_reentry_gp;
uint64_t master_reentry_fn;
uint64_t slave_reentry_fn;
uint64_t magic_dword;
uint64_t uart_putchar;
uint64_t size;
uint64_t uart_getchar;
uint64_t nmi_handler;
uint64_t psb_version;
uint64_t mac_addr;
uint64_t cpu_frequency;
uint64_t board_version;
uint64_t malloc;
uint64_t free;
uint64_t alloc_pbuf;
uint64_t free_pbuf;
uint64_t psb_os_cpu_map;
uint64_t userapp_cpu_map;
uint64_t wakeup_os;
uint64_t psb_mem_map;
uint64_t board_major_version;
uint64_t board_minor_version;
uint64_t board_manf_revision;
uint64_t board_serial_number;
uint64_t psb_physaddr_map;
uint64_t boot_level;
uint64_t io_base;
uint64_t output_device;
uint64_t uart_print;
uint64_t led_output;
uint64_t init;
uint64_t exit;
uint64_t warm_reset;
uint64_t wakeup;
uint64_t cpu_online_map;
uint64_t master_reentry_sp;
uint64_t master_reentry_gp;
uint64_t master_reentry_fn;
uint64_t slave_reentry_fn;
uint64_t magic_dword;
uint64_t uart_putchar;
uint64_t size;
uint64_t uart_getchar;
uint64_t nmi_handler;
uint64_t psb_version;
uint64_t mac_addr;
uint64_t cpu_frequency;
uint64_t board_version;
uint64_t malloc;
uint64_t free;
uint64_t alloc_pbuf;
uint64_t free_pbuf;
uint64_t psb_os_cpu_map;
uint64_t userapp_cpu_map;
uint64_t wakeup_os;
uint64_t psb_mem_map;
uint64_t board_major_version;
uint64_t board_minor_version;
uint64_t board_manf_revision;
uint64_t board_serial_number;
uint64_t psb_physaddr_map;
};
extern struct boot1_info xlr_boot1_info;
@ -92,16 +92,18 @@ struct xlr_loader_info {
/* Boot loader uses the linux mips convention */
#define BOOT1_MEMMAP_MAX 32
enum xlr_phys_memmap_t { BOOT1_MEM_RAM=1, BOOT1_MEM_ROM_DATA, BOOT1_MEM_RESERVED};
enum xlr_phys_memmap_t {
BOOT1_MEM_RAM = 1, BOOT1_MEM_ROM_DATA, BOOT1_MEM_RESERVED
};
struct xlr_boot1_mem_map {
uint32_t num_entries;
struct {
uint64_t addr;
uint64_t size;
uint32_t type;
uint32_t pad;
} physmem_map[BOOT1_MEMMAP_MAX];
uint32_t num_entries;
struct {
uint64_t addr;
uint64_t size;
uint32_t type;
uint32_t pad;
} physmem_map[BOOT1_MEMMAP_MAX];
};

4
sys/mips/rmi/shared_structs_func.h
View File

@ -27,8 +27,8 @@
* SUCH DAMAGE.
*
* RMI_BSD */
/* DO NOT EDIT THIS FILE
* This file has been autogenerated by ./gen_struct_offsets
/* DO NOT EDIT THIS FILE
* This file has been autogenerated by ./gen_struct_offsets
*/
#ifndef _SHARED_STRUCTS_FUNC_H
#define _SHARED_STRUCTS_FUNC_H

4
sys/mips/rmi/shared_structs_offsets.h
View File

@ -27,8 +27,8 @@
* SUCH DAMAGE.
*
* RMI_BSD */
/* DO NOT EDIT THIS FILE
* This file has been autogenerated by ./gen_struct_offsets
/* DO NOT EDIT THIS FILE
* This file has been autogenerated by ./gen_struct_offsets
*/
#ifndef _SHARED_STRUCTS_OFFSETS_H
#define _SHARED_STRUCTS_OFFSETS_H

10
sys/mips/rmi/tick.c
View File

@ -91,13 +91,13 @@ sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)
{
int error;
uint64_t freq;
/*
* RRS wonders if this will really work. You don't
* change the req of the system here, it would require
* changes to the RMI PIC in order to get the TC to
* run at a differrent frequency.
* RRS wonders if this will really work. You don't change the req of
* the system here, it would require changes to the RMI PIC in order
* to get the TC to run at a differrent frequency.
*/
if (counter_timecounter.tc_frequency == 0)
return (EOPNOTSUPP);
freq = counter_freq;

14
sys/mips/rmi/uart_bus_xlr_iodi.c
View File

@ -1,5 +1,5 @@
/*-
* Copyright (c) 2006 Raza Microelectronics
* Copyright (c) 2006 Raza Microelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -46,10 +46,10 @@ static int uart_iodi_probe(device_t dev);
static device_method_t uart_iodi_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, uart_iodi_probe),
DEVMETHOD(device_attach, uart_bus_attach),
DEVMETHOD(device_detach, uart_bus_detach),
{ 0, 0 }
DEVMETHOD(device_probe, uart_iodi_probe),
DEVMETHOD(device_attach, uart_bus_attach),
DEVMETHOD(device_detach, uart_bus_detach),
{0, 0}
};
static driver_t uart_iodi_driver = {
@ -64,9 +64,9 @@ uart_iodi_probe(device_t dev)
struct uart_softc *sc;
sc = device_get_softc(dev);
sc->sc_class = &uart_ns8250_class;
sc->sc_class = &uart_ns8250_class;
/* regshft = 2, rclk = 66000000, rid = 0, chan = 0 */
/* regshft = 2, rclk = 66000000, rid = 0, chan = 0 */
return (uart_bus_probe(dev, 2, 66000000, 0, 0));
}

58
sys/mips/rmi/uart_cpu_mips_xlr.c
View File

@ -30,7 +30,7 @@
* code written by Olivier Houchard.
*/
/*
* XLRMIPS: This file is hacked from arm/...
* XLRMIPS: This file is hacked from arm/...
*/
#include "opt_uart.h"
@ -55,9 +55,10 @@ static int xlr_uart_probe(struct uart_bas *bas);
static void xlr_uart_init(struct uart_bas *bas, int, int, int, int);
static void xlr_uart_term(struct uart_bas *bas);
static void xlr_uart_putc(struct uart_bas *bas, int);
/*static int xlr_uart_poll(struct uart_bas *bas);*/
static int xlr_uart_getc(struct uart_bas *bas, struct mtx *hwmtx);
struct mtx xlr_uart_mtx; /*UartLock*/
struct mtx xlr_uart_mtx; /* UartLock */
extern struct uart_ops uart_ns8250_ops;
@ -66,61 +67,68 @@ struct uart_ops xlr_uart_ns8250_ops = {
.init = xlr_uart_init,
.term = xlr_uart_term,
.putc = xlr_uart_putc,
/* .poll = xlr_uart_poll, ?? */
/* .poll = xlr_uart_poll, ?? */
.getc = xlr_uart_getc,
};
bus_space_tag_t uart_bus_space_io;
bus_space_tag_t uart_bus_space_mem;
static __inline void xlr_uart_lock(struct mtx *hwmtx)
static __inline void
xlr_uart_lock(struct mtx *hwmtx)
{
if(!mtx_initialized(hwmtx))
if (!mtx_initialized(hwmtx))
return;
if(!kdb_active && hwmtx != NULL)
mtx_lock_spin(hwmtx);
if (!kdb_active && hwmtx != NULL)
mtx_lock_spin(hwmtx);
}
static __inline void xlr_uart_unlock(struct mtx *hwmtx)
static __inline void
xlr_uart_unlock(struct mtx *hwmtx)
{
if(!mtx_initialized(hwmtx))
if (!mtx_initialized(hwmtx))
return;
if(!kdb_active && hwmtx != NULL)
mtx_unlock_spin(hwmtx);
if (!kdb_active && hwmtx != NULL)
mtx_unlock_spin(hwmtx);
}
static int xlr_uart_probe(struct uart_bas *bas)
static int
xlr_uart_probe(struct uart_bas *bas)
{
int res;
xlr_uart_lock(&xlr_uart_mtx);
res = uart_ns8250_ops.probe(bas);
xlr_uart_unlock(&xlr_uart_mtx);
return res;
}
static void xlr_uart_init(struct uart_bas *bas, int baudrate, int databits,
int stopbits, int parity)
static void
xlr_uart_init(struct uart_bas *bas, int baudrate, int databits,
int stopbits, int parity)
{
xlr_uart_lock(&xlr_uart_mtx);
uart_ns8250_ops.init(bas,baudrate,databits,stopbits,parity);
uart_ns8250_ops.init(bas, baudrate, databits, stopbits, parity);
xlr_uart_unlock(&xlr_uart_mtx);
}
static void xlr_uart_term(struct uart_bas *bas)
static void
xlr_uart_term(struct uart_bas *bas)
{
xlr_uart_lock(&xlr_uart_mtx);
uart_ns8250_ops.term(bas);
xlr_uart_unlock(&xlr_uart_mtx);
}
static void xlr_uart_putc(struct uart_bas *bas, int c)
static void
xlr_uart_putc(struct uart_bas *bas, int c)
{
xlr_uart_lock(&xlr_uart_mtx);
uart_ns8250_ops.putc(bas,c);
uart_ns8250_ops.putc(bas, c);
xlr_uart_unlock(&xlr_uart_mtx);
}
/*
static int xlr_uart_poll(struct uart_bas *bas)
{
@ -132,7 +140,8 @@ static int xlr_uart_poll(struct uart_bas *bas)
}
*/
static int xlr_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
static int
xlr_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
{
return uart_ns8250_ops.getc(bas, hwmtx);
}
@ -151,7 +160,7 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
di->bas.chan = 0;
di->bas.bst = uart_bus_space_mem;
/* TODO Need to call bus_space_map() here */
di->bas.bsh = 0xbef14000; /* Try with UART0 */
di->bas.bsh = 0xbef14000; /* Try with UART0 */
di->bas.regshft = 2;
/* divisor = rclk / (baudrate * 16); */
di->bas.rclk = 66000000;
@ -166,9 +175,10 @@ uart_cpu_getdev(int devtype, struct uart_devinfo *di)
return (0);
}
static void xlr_uart_mtx_init(void *dummy __unused)
static void
xlr_uart_mtx_init(void *dummy __unused)
{
mtx_init(&xlr_uart_mtx, "uart lock",NULL,MTX_SPIN);
mtx_init(&xlr_uart_mtx, "uart lock", NULL, MTX_SPIN);
}
SYSINIT(xlr_init_uart_mtx, SI_SUB_LOCK, SI_ORDER_ANY, xlr_uart_mtx_init, NULL);
SYSINIT(xlr_init_uart_mtx, SI_SUB_LOCK, SI_ORDER_ANY, xlr_uart_mtx_init, NULL);

16
sys/mips/rmi/xlr_boot1_console.c
View File

@ -52,12 +52,12 @@ __FBSDID("$FreeBSD$");
#include <ddb/ddb.h>
#if 0
static cn_probe_t xlr_boot1_cnprobe;
static cn_init_t xlr_boot1_cninit;
static cn_term_t xlr_boot1_cnterm;
static cn_getc_t xlr_boot1_cngetc;
static cn_checkc_t xlr_boot1_cncheckc;
static cn_putc_t xlr_boot1_cnputc;
static cn_probe_t xlr_boot1_cnprobe;
static cn_init_t xlr_boot1_cninit;
static cn_term_t xlr_boot1_cnterm;
static cn_getc_t xlr_boot1_cngetc;
static cn_checkc_t xlr_boot1_cncheckc;
static cn_putc_t xlr_boot1_cnputc;
CONS_DRIVER(xlrboot, xlr_boot1_cnprobe, xlr_boot1_cninit, xlr_boot1_cnterm, xlr_boot1_cngetc,
xlr_boot1_cncheckc, xlr_boot1_cnputc, NULL);
@ -70,8 +70,8 @@ xlr_boot1_cnprobe(struct consdev *cp)
{
cp->cn_pri = CN_NORMAL;
cp->cn_tp = NULL;
cp->cn_arg = NULL; /* softc */
cp->cn_unit = -1; /* ? */
cp->cn_arg = NULL; /* softc */
cp->cn_unit = -1; /* ? */
cp->cn_flags = 0;
}

447
sys/mips/rmi/xlr_i2c.c
View File

@ -39,7 +39,7 @@ __FBSDID("$FreeBSD: src/sys/mips/xlr/xlr_i2c.c,v 1.20.8.1 2008/08/25 23:17:51 co
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <sys/bus.h>
#include <sys/rman.h>
@ -65,7 +65,7 @@ __FBSDID("$FreeBSD: src/sys/mips/xlr/xlr_i2c.c,v 1.20.8.1 2008/08/25 23:17:51 co
#define I2C_PALM_HDSTATIM 0x09
/* TEST Values!! Change as required */
#define I2C_PALM_CFG_DEF 0x000000F8 /* 8-Bit Addr + POR Values */
#define I2C_PALM_CFG_DEF 0x000000F8 /* 8-Bit Addr + POR Values */
#define I2C_PALM_CLKDIV_DEF 0x14A //0x00000052
#define I2C_PALM_HDSTATIM_DEF 0x107 //0x00000000
@ -78,12 +78,12 @@ __FBSDID("$FreeBSD: src/sys/mips/xlr/xlr_i2c.c,v 1.20.8.1 2008/08/25 23:17:51 co
#define ARIZONA_I2c_BUS 1
int bus =1;
int bus = 1;
uint8_t current_slave;
uint8_t read_address;
static xlr_reg_t* iobase_i2c_regs;
static xlr_reg_t *iobase_i2c_regs;
static devclass_t xlr_i2c_devclass;
@ -96,20 +96,19 @@ static int xlr_i2c_detach(device_t);
static int xlr_i2c_start(device_t dev, u_char slave, int timeout);
static int xlr_i2c_stop(device_t dev);
static int xlr_i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay );
static int xlr_i2c_write(device_t dev, char *buf, int len, int *sent, int timeout );
static int xlr_i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay);
static int xlr_i2c_write(device_t dev, char *buf, int len, int *sent, int timeout);
struct xlr_i2c_softc
{
device_t dev; /* Myself */
struct resource *mem_res; /* Memory resource */
volatile int flags;
struct xlr_i2c_softc {
device_t dev; /* Myself */
struct resource *mem_res; /* Memory resource */
volatile int flags;
#define RXRDY 4
#define TXRDY 0x10
int sc_started;
int twi_addr;
device_t iicbus;
int sc_started;
int twi_addr;
device_t iicbus;
};
@ -118,164 +117,176 @@ struct xlr_i2c_softc
while(local_loop--); \
}\
static void get_i2c_base(void)
static void
get_i2c_base(void)
{
if(bus == 0)
iobase_i2c_regs = xlr_io_mmio(PHOENIX_IO_I2C_0_OFFSET);
else
iobase_i2c_regs = xlr_io_mmio(PHOENIX_IO_I2C_1_OFFSET);
return;
if (bus == 0)
iobase_i2c_regs = xlr_io_mmio(PHOENIX_IO_I2C_0_OFFSET);
else
iobase_i2c_regs = xlr_io_mmio(PHOENIX_IO_I2C_1_OFFSET);
return;
}
static void palm_write(int reg, int value)
static void
palm_write(int reg, int value)
{
get_i2c_base();
xlr_write_reg(iobase_i2c_regs, reg, value);
return;
get_i2c_base();
xlr_write_reg(iobase_i2c_regs, reg, value);
return;
}
static int palm_read(int reg)
static int
palm_read(int reg)
{
uint32_t val;
get_i2c_base();
val = xlr_read_reg(iobase_i2c_regs, reg);
return ((int) val);
uint32_t val;
get_i2c_base();
val = xlr_read_reg(iobase_i2c_regs, reg);
return ((int)val);
}
static int palm_addr_only(uint8_t addr, uint8_t offset)
static int
palm_addr_only(uint8_t addr, uint8_t offset)
{
volatile uint32_t regVal=0x00;
volatile uint32_t regVal = 0x00;
palm_write(I2C_PALM_ADDR, offset);
palm_write(I2C_PALM_DEVADDR, addr);
palm_write(I2C_PALM_CFG, 0xfa);
palm_write(I2C_PALM_STARTXFR,0x02);
regVal = palm_read(I2C_PALM_STATUS);
if (regVal & 0x0008) {
printf("palm_addr_only: ACKERR. Aborting...\n");
return -1;
}
return 0;
palm_write(I2C_PALM_ADDR, offset);
palm_write(I2C_PALM_DEVADDR, addr);
palm_write(I2C_PALM_CFG, 0xfa);
palm_write(I2C_PALM_STARTXFR, 0x02);
regVal = palm_read(I2C_PALM_STATUS);
if (regVal & 0x0008) {
printf("palm_addr_only: ACKERR. Aborting...\n");
return -1;
}
return 0;
}
static int palm_rx(uint8_t addr, uint8_t offset, uint8_t len,
uint8_t *buf)
static int
palm_rx(uint8_t addr, uint8_t offset, uint8_t len,
uint8_t * buf)
{
volatile uint32_t regVal=0x00, ctr=0x00;
int timeOut, numBytes=0x00;
volatile uint32_t regVal = 0x00, ctr = 0x00;
int timeOut, numBytes = 0x00;
palm_write(I2C_PALM_CFG, 0xfa);
palm_write(I2C_PALM_BYTECNT, len);
palm_write(I2C_PALM_DEVADDR, addr); //DEVADDR=0x4c, 0x68
MDELAY(1);
palm_write(I2C_PALM_CFG, 0xfa);
palm_write(I2C_PALM_BYTECNT, len);
palm_write(I2C_PALM_DEVADDR, addr);
//DEVADDR = 0x4c, 0x68
MDELAY(1);
for (numBytes=0x00; numBytes < len; numBytes++) {
palm_write(I2C_PALM_ADDR, offset+numBytes);//I2C_PALM_ADDR:offset
MDELAY(1);
if (!ctr) {
/* Trigger a READ Transaction */
palm_write(I2C_PALM_STARTXFR, I2C_PALM_STARTXFR_RD);
ctr++;
}
/* Error Conditions [Begin] */
regVal = palm_read(I2C_PALM_STATUS);
MDELAY(1);
if (regVal & 0x0008) {
printf("palm_rx: ACKERR. Aborting...\n");
return -1;
}
timeOut=10;
while ((regVal & 0x0030) && timeOut--) {
palm_write(I2C_PALM_STARTXFR, I2C_PALM_STARTXFR_RD);
regVal = palm_read(I2C_PALM_STATUS);
}
if (timeOut==0x00) {
printf("palm_rx: TimedOut on Valid STARTXFR/Arbitration\n");
return -1;
}
timeOut=10;
/* Do we have valid data from the device yet..? */
regVal &= 0x0004;
while (!regVal && timeOut--) {
regVal = palm_read(I2C_PALM_STATUS) & 0x0004;
}
if (timeOut==0x00) {
printf("palm_rx: TimedOut Waiting for Valid Data\n");
return -1;
}
/* Error Conditions [End] */
/* Read the data */
buf[numBytes] = (uint8_t)palm_read(I2C_PALM_DATAIN);
}
return 0;
for (numBytes = 0x00; numBytes < len; numBytes++) {
palm_write(I2C_PALM_ADDR, offset + numBytes);
//I2C_PALM_ADDR:offset
MDELAY(1);
if (!ctr) {
/* Trigger a READ Transaction */
palm_write(I2C_PALM_STARTXFR, I2C_PALM_STARTXFR_RD);
ctr++;
}
/* Error Conditions [Begin] */
regVal = palm_read(I2C_PALM_STATUS);
MDELAY(1);
if (regVal & 0x0008) {
printf("palm_rx: ACKERR. Aborting...\n");
return -1;
}
timeOut = 10;
while ((regVal & 0x0030) && timeOut--) {
palm_write(I2C_PALM_STARTXFR, I2C_PALM_STARTXFR_RD);
regVal = palm_read(I2C_PALM_STATUS);
}
if (timeOut == 0x00) {
printf("palm_rx: TimedOut on Valid STARTXFR/Arbitration\n");
return -1;
}
timeOut = 10;
/* Do we have valid data from the device yet..? */
regVal &= 0x0004;
while (!regVal && timeOut--) {
regVal = palm_read(I2C_PALM_STATUS) & 0x0004;
}
if (timeOut == 0x00) {
printf("palm_rx: TimedOut Waiting for Valid Data\n");
return -1;
}
/* Error Conditions [End] */
/* Read the data */
buf[numBytes] = (uint8_t) palm_read(I2C_PALM_DATAIN);
}
return 0;
}
static int wait_for_idle(void)
static int
wait_for_idle(void)
{
int timeOut=0x1000;
volatile uint32_t regVal=0x00;
regVal = palm_read(I2C_PALM_STATUS) & 0x0001;
while (regVal && timeOut--) {
regVal = palm_read(I2C_PALM_STATUS) & 0x0001;
}
if (timeOut == 0x00)
return -1; /* Timed Out */
else
return 0;
int timeOut = 0x1000;
volatile uint32_t regVal = 0x00;
regVal = palm_read(I2C_PALM_STATUS) & 0x0001;
while (regVal && timeOut--) {
regVal = palm_read(I2C_PALM_STATUS) & 0x0001;
}
if (timeOut == 0x00)
return -1; /* Timed Out */
else
return 0;
}
static int palm_tx(uint8_t addr, uint8_t offset, uint8_t* buf, uint8_t len)
static int
palm_tx(uint8_t addr, uint8_t offset, uint8_t * buf, uint8_t len)
{
volatile uint32_t regVal=0x00;
int timeOut, ctr=0x00, numBytes=len;
volatile uint32_t regVal = 0x00;
int timeOut, ctr = 0x00, numBytes = len;
for (ctr=0x00; ctr<len; ctr++) {
if (wait_for_idle() < 0) {
printf("TimedOut on Waiting for I2C Bus Idle.\n");
return -EIO;
}
palm_write(I2C_PALM_CFG, 0xF8);
palm_write(I2C_PALM_BYTECNT, 0x00);
palm_write(I2C_PALM_DEVADDR, addr); //0x4c, 0x68
palm_write(I2C_PALM_ADDR, offset+numBytes-1); //offset
palm_write(I2C_PALM_DATAOUT, buf[ctr]);
palm_write(I2C_PALM_STARTXFR, I2C_PALM_STARTXFR_WR );
MDELAY(1);
for (ctr = 0x00; ctr < len; ctr++) {
if (wait_for_idle() < 0) {
printf("TimedOut on Waiting for I2C Bus Idle.\n");
return -EIO;
}
palm_write(I2C_PALM_CFG, 0xF8);
palm_write(I2C_PALM_BYTECNT, 0x00);
palm_write(I2C_PALM_DEVADDR, addr);
//0x4c, 0x68
palm_write(I2C_PALM_ADDR, offset + numBytes - 1);
//offset
palm_write(I2C_PALM_DATAOUT, buf[ctr]);
palm_write(I2C_PALM_STARTXFR, I2C_PALM_STARTXFR_WR);
MDELAY(1);
regVal = palm_read(I2C_PALM_STATUS);
MDELAY(1);
if (regVal & 0x0008) {
printf("palm_tx: ACKERR. Aborting...\n");
return -1;
}
timeOut= 0x1000;
while (!(regVal & 0x0002) && timeOut) {
regVal = palm_read(I2C_PALM_STATUS);
timeOut--;
}
if (timeOut==0x00) {
printf("palm_tx: [TimeOut] SDOEMPTY Not Set\n");
return -1;
}
timeOut=1000;
while ((regVal & 0x0030) && timeOut) {
palm_write(I2C_PALM_STARTXFR, I2C_PALM_STARTXFR_WR);
regVal = palm_read(I2C_PALM_STATUS);
timeOut--;
}
if (timeOut==0x00) {
printf("palm_rx: TimedOut on Valid STARTXFR/Arbitration\n");
return -1;
}
numBytes--;
}
return 0;
regVal = palm_read(I2C_PALM_STATUS);
MDELAY(1);
if (regVal & 0x0008) {
printf("palm_tx: ACKERR. Aborting...\n");
return -1;
}
timeOut = 0x1000;
while (!(regVal & 0x0002) && timeOut) {
regVal = palm_read(I2C_PALM_STATUS);
timeOut--;
}
if (timeOut == 0x00) {
printf("palm_tx: [TimeOut] SDOEMPTY Not Set\n");
return -1;
}
timeOut = 1000;
while ((regVal & 0x0030) && timeOut) {
palm_write(I2C_PALM_STARTXFR, I2C_PALM_STARTXFR_WR);
regVal = palm_read(I2C_PALM_STATUS);
timeOut--;
}
if (timeOut == 0x00) {
printf("palm_rx: TimedOut on Valid STARTXFR/Arbitration\n");
return -1;
}
numBytes--;
}
return 0;
}
@ -298,34 +309,32 @@ xlr_i2c_probe(device_t dev)
static int
xlr_i2c_attach(device_t dev)
{
struct xlr_i2c_softc *sc;
int rid;
struct xlr_i2c_softc *sc;
int rid;
sc = device_get_softc(dev);
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (sc->mem_res == NULL)
{
printf("not able to allocate the bus resource\n");
}
if((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL)
printf("could not allocate iicbus instance\n");
sc = device_get_softc(dev);
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (sc->mem_res == NULL) {
printf("not able to allocate the bus resource\n");
}
if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL)
printf("could not allocate iicbus instance\n");
bus_generic_attach(dev);
return (0);
return (0);
}
static int
xlr_i2c_detach(device_t dev)
{
bus_generic_detach(dev);
return (0);
}
/*
/*
static int
xlr_i2c_add_child(device_t dev, int order, const char *name, int unit)
{
@ -338,105 +347,109 @@ xlr_i2c_add_child(device_t dev, int order, const char *name, int unit)
}
*/
static int xlr_i2c_start(device_t dev, u_char slave, int timeout)
static int
xlr_i2c_start(device_t dev, u_char slave, int timeout)
{
int error =0;
struct xlr_i2c_softc *sc;
int error = 0;
struct xlr_i2c_softc *sc;
sc = device_get_softc(dev);
sc->sc_started = 1;
sc = device_get_softc(dev);
sc->sc_started = 1;
current_slave = (slave >> 1);
return error;
current_slave = (slave >> 1);
return error;
}
static int xlr_i2c_stop(device_t dev)
static int
xlr_i2c_stop(device_t dev)
{
int error =0;
int error = 0;
return error;
return error;
}
static int xlr_i2c_read(device_t dev, char *buf, int len, int *read, int last,
int delay )
static int
xlr_i2c_read(device_t dev, char *buf, int len, int *read, int last,
int delay)
{
int error =0;
int error = 0;
if(palm_addr_only(current_slave,read_address) == -1){
printf("I2C ADDRONLY Phase Fail.\n");
return -1;
}
if(palm_rx(current_slave,read_address,len,buf)== -1){
printf("I2C Read Fail.\n");
return -1;
}
*read = len;
return error;
if (palm_addr_only(current_slave, read_address) == -1) {
printf("I2C ADDRONLY Phase Fail.\n");
return -1;
}
if (palm_rx(current_slave, read_address, len, buf) == -1) {
printf("I2C Read Fail.\n");
return -1;
}
*read = len;
return error;
}
static int xlr_i2c_write(device_t dev, char *buf, int len, int *sent, int timeout /* us */)
static int
xlr_i2c_write(device_t dev, char *buf, int len, int *sent, int timeout /* us */ )
{
int error =0;
uint8_t write_address;
int error = 0;
uint8_t write_address;
if(len == 1){
/* address for the next read*/
read_address=buf[0];
return error;
}
if(len < 2)
return (-1);
if (len == 1) {
/* address for the next read */
read_address = buf[0];
return error;
}
if (len < 2)
return (-1);
write_address = buf[0];
write_address = buf[0];
/*for write operation, buf[0] contains the register offset and
buf[1] onwards contains the value*/
palm_tx(current_slave,write_address, &buf[1], len-1);
return error;
/*
* for write operation, buf[0] contains the register offset and
* buf[1] onwards contains the value
*/
palm_tx(current_slave, write_address, &buf[1], len - 1);
return error;
}
static int
xlr_i2c_callback(device_t dev, int index, caddr_t *data)
{
return 0;
return 0;
}
static int
xlr_i2c_repeated_start(device_t dev, u_char slave, int timeout)
{
return 0;
return 0;
}
static device_method_t xlr_i2c_methods[] = {
/* device interface */
DEVMETHOD(device_probe, xlr_i2c_probe),
DEVMETHOD(device_attach, xlr_i2c_attach),
DEVMETHOD(device_detach, xlr_i2c_detach),
/* device interface */
DEVMETHOD(device_probe, xlr_i2c_probe),
DEVMETHOD(device_attach, xlr_i2c_attach),
DEVMETHOD(device_detach, xlr_i2c_detach),
/* iicbus interface */
DEVMETHOD(iicbus_callback, xlr_i2c_callback),
DEVMETHOD(iicbus_repeated_start, xlr_i2c_repeated_start),
DEVMETHOD(iicbus_start, xlr_i2c_start),
DEVMETHOD(iicbus_stop, xlr_i2c_stop),
DEVMETHOD(iicbus_write, xlr_i2c_write),
DEVMETHOD(iicbus_read, xlr_i2c_read),
{ 0, 0 }
/* iicbus interface */
DEVMETHOD(iicbus_callback, xlr_i2c_callback),
DEVMETHOD(iicbus_repeated_start, xlr_i2c_repeated_start),
DEVMETHOD(iicbus_start, xlr_i2c_start),
DEVMETHOD(iicbus_stop, xlr_i2c_stop),
DEVMETHOD(iicbus_write, xlr_i2c_write),
DEVMETHOD(iicbus_read, xlr_i2c_read),
{0, 0}
};
static driver_t xlr_i2c_driver = {
"xlr_i2c",
xlr_i2c_methods,
sizeof(struct xlr_i2c_softc),
"xlr_i2c",
xlr_i2c_methods,
sizeof(struct xlr_i2c_softc),
};
DRIVER_MODULE(xlr_i2c, iodi, xlr_i2c_driver, xlr_i2c_devclass, 0, 0);

345
sys/mips/rmi/xlr_machdep.c
View File

@ -46,7 +46,7 @@
#include <sys/sysctl.h>
#include <sys/unistd.h>
#include <sys/cons.h> /* cinit() */
#include <sys/cons.h> /* cinit() */
#include <sys/reboot.h>
#include <sys/queue.h>
#include <sys/smp.h>
@ -88,7 +88,7 @@ void platform_prep_smp_launch(void);
unsigned long xlr_io_base = (unsigned long)(DEFAULT_XLR_IO_BASE);
/* 4KB static data aread to keep a copy of the bootload env until
/* 4KB static data aread to keep a copy of the bootload env until
the dynamic kenv is setup */
char boot1_env[4096];
extern unsigned long _gp;
@ -96,34 +96,37 @@ extern unsigned long _gp;
/*
* Parameters from boot loader
*/
struct boot1_info xlr_boot1_info;
struct xlr_loader_info xlr_loader_info; /* FIXME : Unused */
int xlr_run_mode;
int xlr_argc;
char **xlr_argv, **xlr_envp;
uint64_t cpu_mask_info;
uint32_t xlr_online_cpumask;
struct boot1_info xlr_boot1_info;
struct xlr_loader_info xlr_loader_info; /* FIXME : Unused */
int xlr_run_mode;
int xlr_argc;
char **xlr_argv, **xlr_envp;
uint64_t cpu_mask_info;
uint32_t xlr_online_cpumask;
#ifdef SMP
static unsigned long xlr_secondary_gp[MAXCPU];
static unsigned long xlr_secondary_sp[MAXCPU];
#endif
extern int mips_cpu_online_mask;
extern int mips_cpu_logical_mask;
uint32_t cpu_ltop_map[MAXCPU];
uint32_t cpu_ptol_map[MAXCPU];
uint32_t xlr_core_cpu_mask=0x1; /* Core 0 thread 0 is always there */
uint32_t xlr_core_cpu_mask = 0x1; /* Core 0 thread 0 is always there */
void
platform_reset(void)
{
/* FIXME : use proper define */
u_int32_t *mmio = (u_int32_t *)0xbef18000;
u_int32_t *mmio = (u_int32_t *) 0xbef18000;
printf("Rebooting the system now\n");
mmio[8] = 0x1;
}
void platform_secondary_init(void)
void
platform_secondary_init(void)
{
#ifdef SMP
xlr_msgring_cpu_init();
@ -143,8 +146,9 @@ void platform_secondary_init(void)
}
int xlr_asid_pcpu=256; /* This the default */
int xlr_shtlb_enabled=0;
int xlr_asid_pcpu = 256; /* This the default */
int xlr_shtlb_enabled = 0;
/* This function sets up the number of tlb entries available
to the kernel based on the number of threads brought up.
The ASID range also gets divided similarly.
@ -153,7 +157,8 @@ NOTE: This function will mark all 64TLB entries as available
to the threads brought up in the core. If kernel is brought with say mask
0x33333333, no TLBs will be available to the threads in each core.
*/
static void setup_tlb_resource(void)
static void
setup_tlb_resource(void)
{
int mmu_setup;
int value = 0;
@ -161,18 +166,18 @@ static void setup_tlb_resource(void)
uint32_t thr_mask = cpu_map >> (xlr_cpu_id() << 2);
uint8_t core0 = xlr_boot1_info.cpu_online_map & 0xf;
uint8_t core_thr_mask;
int i=0, count=0;
int i = 0, count = 0;
/* If CPU0 did not enable shared TLB, other cores need to follow */
if((xlr_cpu_id() != 0) && (xlr_shtlb_enabled == 0))
if ((xlr_cpu_id() != 0) && (xlr_shtlb_enabled == 0))
return;
/* First check if each core is brought up with the same mask */
for(i=1; i < 8; i++) {
for (i = 1; i < 8; i++) {
core_thr_mask = cpu_map >> (i << 2);
core_thr_mask &= 0xf;
if(core_thr_mask && core_thr_mask != core0){
if (core_thr_mask && core_thr_mask != core0) {
printf
("Each core must be brought with same cpu mask\n");
("Each core must be brought with same cpu mask\n");
printf("Cannot enabled shared TLB. ");
printf("Falling back to split TLB mode\n");
return;
@ -180,19 +185,21 @@ static void setup_tlb_resource(void)
}
xlr_shtlb_enabled = 1;
for(i=0;i<4;i++) if (thr_mask & (1<<i)) count++;
switch(count) {
case 1:
xlr_asid_pcpu = 256;
break;
case 2:
xlr_asid_pcpu = 128;
value = 0x2;
break;
default:
xlr_asid_pcpu = 64;
value = 0x3;
break;
for (i = 0; i < 4; i++)
if (thr_mask & (1 << i))
count++;
switch (count) {
case 1:
xlr_asid_pcpu = 256;
break;
case 2:
xlr_asid_pcpu = 128;
value = 0x2;
break;
default:
xlr_asid_pcpu = 64;
value = 0x3;
break;
}
mmu_setup = read_32bit_phnx_ctrl_reg(4, 0);
@ -205,33 +212,33 @@ static void setup_tlb_resource(void)
write_32bit_phnx_ctrl_reg(4, 0, mmu_setup);
}
/*
* Platform specific register setup for CPUs
* Platform specific register setup for CPUs
* XLR has control registers accessible with MFCR/MTCR instructions, this
* code initialized them from the environment variable xlr.cr of form:
* xlr.cr=reg:val[,reg:val]*, all values in hex.
* To enable shared TLB option use xlr.shtlb=1
*/
void platform_cpu_init()
void
platform_cpu_init()
{
char *hw_env;
char *start, *end;
uint32_t reg,val;
uint32_t reg, val;
int thr_id = xlr_thr_id();
if(thr_id == 0) {
if (thr_id == 0) {
if ((hw_env = getenv("xlr.shtlb")) != NULL) {
start = hw_env;
reg = strtoul(start, &end, 16);
if(start != end && reg != 0)
if (start != end && reg != 0)
setup_tlb_resource();
} else {
/* By default TLB entries are shared in a core */
setup_tlb_resource();
}
}
if ((hw_env = getenv("xlr.cr")) == NULL)
return;
@ -240,32 +247,30 @@ void platform_cpu_init()
reg = strtoul(start, &end, 16);
if (start == end) {
printf("Invalid value in xlr.cr %s, cannot read a hex value at %d\n",
hw_env, start - hw_env);
hw_env, start - hw_env);
goto err_return;
}
if (*end != ':') {
printf("Invalid format in xlr.cr %s, ':' expected at pos %d\n",
hw_env, end - hw_env);
hw_env, end - hw_env);
goto err_return;
}
start = end + 1; /* step over ':' */
start = end + 1;/* step over ':' */
val = strtoul(start, &end, 16);
if (start == end) {
printf("Invalid value in xlr.cr %s, cannot read a hex value at pos %d\n",
hw_env, start - hw_env);
hw_env, start - hw_env);
goto err_return;
}
if (*end != ',' && *end != '\0') {
printf("Invalid format in xlr.cr %s, ',' expected at pos %d\n",
hw_env, end - hw_env);
hw_env, end - hw_env);
goto err_return;
}
xlr_mtcr(reg, val);
if (*end == ',')
start = end + 1; /* skip over ',' */
else
start = end + 1; /* skip over ',' */
else
start = end;
}
freeenv(hw_env);
@ -279,24 +284,27 @@ err_return:
#ifdef SMP
extern void xlr_secondary_start(unsigned long, unsigned long, unsigned long);
static void xlr_secondary_entry(void *data)
static void
xlr_secondary_entry(void *data)
{
unsigned long sp,gp;
unsigned int cpu = (xlr_cpu_id()<<2)+xlr_thr_id();
unsigned long sp, gp;
unsigned int cpu = (xlr_cpu_id() << 2) + xlr_thr_id();
sp = xlr_secondary_sp[cpu];
gp = xlr_secondary_gp[cpu];
xlr_secondary_start((unsigned long)mips_secondary_wait, sp, gp);
}
#endif
static void xlr_set_boot_flags(void)
static void
xlr_set_boot_flags(void)
{
char *p;
for (p = getenv("boot_flags"); p && *p != '\0'; p++) {
switch(*p) {
switch (*p) {
case 'd':
case 'D':
boothowto |= RB_KDB;
@ -310,7 +318,7 @@ static void xlr_set_boot_flags(void)
boothowto |= RB_VERBOSE;
break;
case 's': /* single-user (default, supported for sanity) */
case 's': /* single-user (default, supported for sanity) */
case 'S':
boothowto |= RB_SINGLE;
break;
@ -321,12 +329,12 @@ static void xlr_set_boot_flags(void)
}
}
if (p)
if (p)
freeenv(p);
return;
}
extern uint32_t _end;
extern uint32_t _end;
static void
@ -336,12 +344,12 @@ mips_init(void)
init_param2(physmem);
/* XXX: Catch 22. Something touches the tlb. */
mips_cpu_init();
pmap_bootstrap();
mips_proc0_init();
write_c0_register32(MIPS_COP_0_OSSCRATCH,7, pcpup->pc_curthread);
write_c0_register32(MIPS_COP_0_OSSCRATCH, 7, pcpup->pc_curthread);
mutex_init();
@ -349,8 +357,8 @@ mips_init(void)
#ifdef DDB
#ifdef SMP
setup_nmi();
#endif /* SMP */
setup_nmi();
#endif /* SMP */
kdb_init();
if (boothowto & RB_KDB) {
kdb_enter("Boot flags requested debugger");
@ -362,23 +370,25 @@ void tick_init(void);
void
platform_start(__register_t a0 __unused,
__register_t a1 __unused,
__register_t a2 __unused,
__register_t a3 __unused)
__register_t a1 __unused,
__register_t a2 __unused,
__register_t a3 __unused)
{
vm_size_t physsz = 0;
int i, j;
struct xlr_boot1_mem_map *boot_map;
#ifdef SMP
uint32_t tmp;
void (*wakeup)(void *, void *, unsigned int);
void (*wakeup) (void *, void *, unsigned int);
#endif
/* XXX FIXME the code below is not 64 bit clean */
/* Save boot loader and other stuff from scratch regs */
xlr_boot1_info = *(struct boot1_info *)read_c0_register32(MIPS_COP_0_OSSCRATCH, 0);
cpu_mask_info = read_c0_register64(MIPS_COP_0_OSSCRATCH, 1);
cpu_mask_info = read_c0_register64(MIPS_COP_0_OSSCRATCH, 1);
xlr_online_cpumask = read_c0_register32(MIPS_COP_0_OSSCRATCH, 2);
xlr_run_mode = read_c0_register32(MIPS_COP_0_OSSCRATCH, 3);
xlr_argc = read_c0_register32(MIPS_COP_0_OSSCRATCH, 4);
@ -386,28 +396,29 @@ platform_start(__register_t a0 __unused,
xlr_envp = (char **)read_c0_register32(MIPS_COP_0_OSSCRATCH, 6);
/* TODO: Verify the magic number here */
/*FIXMELATER: xlr_boot1_info.magic_number */
/* FIXMELATER: xlr_boot1_info.magic_number */
/* initialize console so that we have printf */
boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */
/* clockrate used by delay, so initialize it here */
cpu_clock = xlr_boot1_info.cpu_frequency/1000000 ;
boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */
/* Note the time counter on CPU0 runs not at system
* clock speed, but at PIC time counter speed (which is
* returned by platform_get_frequency(). Thus we do not
* use xlr_boot1_info.cpu_frequency here.
/* clockrate used by delay, so initialize it here */
cpu_clock = xlr_boot1_info.cpu_frequency / 1000000;
/*
* Note the time counter on CPU0 runs not at system clock speed, but
* at PIC time counter speed (which is returned by
* platform_get_frequency(). Thus we do not use
* xlr_boot1_info.cpu_frequency here.
*/
mips_timer_early_init(platform_get_frequency());
mips_timer_init_params(platform_get_frequency(), 0);
cninit();
init_static_kenv(boot1_env, sizeof(boot1_env));
printf("Environment (from %d args):\n", xlr_argc-1);
printf("Environment (from %d args):\n", xlr_argc - 1);
if (xlr_argc == 1)
printf("\tNone\n");
for(i=1; i<xlr_argc; i++) {
for (i = 1; i < xlr_argc; i++) {
char *n;
printf("\t%s\n", xlr_argv[i]);
@ -420,28 +431,28 @@ platform_start(__register_t a0 __unused,
xlr_set_boot_flags();
/* get physical memory info from boot loader*/
/* get physical memory info from boot loader */
boot_map = (struct xlr_boot1_mem_map *)
(unsigned long)xlr_boot1_info.psb_mem_map;
for(i=0, j=0; i<boot_map->num_entries; i++, j+=2) {
(unsigned long)xlr_boot1_info.psb_mem_map;
for (i = 0, j = 0; i < boot_map->num_entries; i++, j += 2) {
if (boot_map->physmem_map[i].type == BOOT1_MEM_RAM) {
if (j == 14) {
printf("*** ERROR *** memory map too large ***\n");
printf("*** ERROR *** memory map too large ***\n");
break;
}
if (j == 0) {
/*TODO FIXME */
/* TODO FIXME */
/* start after kernel end */
phys_avail[0] = (vm_paddr_t)
MIPS_KSEG0_TO_PHYS(&_end) + 0x20000;
MIPS_KSEG0_TO_PHYS(&_end) + 0x20000;
/* boot loader start */
/* HACK to Use bootloaders memory region */
/*TODO FIXME */
if(boot_map->physmem_map[0].size == 0x0c000000) {
/* TODO FIXME */
if (boot_map->physmem_map[0].size == 0x0c000000) {
boot_map->physmem_map[0].size = 0x0ff00000;
}
phys_avail[1] = boot_map->physmem_map[0].addr +
boot_map->physmem_map[0].size;
boot_map->physmem_map[0].size;
} else {
/*
@ -450,11 +461,11 @@ platform_start(__register_t a0 __unused,
* to map from the second are which is not in KSEG0 and not mapped
*/
phys_avail[j] = (vm_paddr_t)
boot_map->physmem_map[i].addr;
phys_avail[j+1] = phys_avail[j] +
boot_map->physmem_map[i].size;
#if 0 /* FIXME TOD0 */
phys_avail[j] = phys_avail[j+1] = 0;
boot_map->physmem_map[i].addr;
phys_avail[j + 1] = phys_avail[j] +
boot_map->physmem_map[i].size;
#if 0 /* FIXME TOD0 */
phys_avail[j] = phys_avail[j + 1] = 0;
#endif
}
physsz += boot_map->physmem_map[i].size;
@ -462,67 +473,71 @@ platform_start(__register_t a0 __unused,
}
/* FIXME XLR TODO */
phys_avail[j] = phys_avail[j+1] = 0;
phys_avail[j] = phys_avail[j + 1] = 0;
realmem = physmem = btoc(physsz);
/*Store pcpu in scratch 5*/
write_c0_register32(MIPS_COP_0_OSSCRATCH,5,pcpup);
/* Store pcpu in scratch 5 */
write_c0_register32(MIPS_COP_0_OSSCRATCH, 5, pcpup);
/* Set up hz, among others. */
mips_init();
pcpup = (struct pcpu *)NULL; /* TODO To be removed */
pcpup = (struct pcpu *)NULL; /* TODO To be removed */
#ifdef SMP
/*If thread 0 of any core is not available then mark whole core as
not available*/
/*
* If thread 0 of any core is not available then mark whole core as
* not available
*/
tmp = xlr_boot1_info.cpu_online_map;
for(i=4; i<MAXCPU; i += 4){
if((tmp & (0xf<<i)) && !(tmp & (0x1<<i))){
/*Oopps.. thread 0 is not available. Disable whole
core*/
tmp = tmp & ~(0xf<<i);
for (i = 4; i < MAXCPU; i += 4) {
if ((tmp & (0xf << i)) && !(tmp & (0x1 << i))) {
/*
* Oopps.. thread 0 is not available. Disable whole
* core
*/
tmp = tmp & ~(0xf << i);
printf("WARNING: Core %d is disabled because thread 0"
" of this core is not enabled.\n",i/4);
" of this core is not enabled.\n", i / 4);
}
}
xlr_boot1_info.cpu_online_map = tmp;
/* Wakeup Other cpus, and put them in bsd park code. */
for(i=1,j=1;i<32;i++){
for (i = 1, j = 1; i < 32; i++) {
/* Allocate stack for all other cpus from fbsd kseg0 memory. */
if((1U<<i) & xlr_boot1_info.cpu_online_map){
xlr_secondary_gp[i] =
pmap_steal_memory(PAGE_SIZE) ;
if(!xlr_secondary_gp[i])
if ((1U << i) & xlr_boot1_info.cpu_online_map) {
xlr_secondary_gp[i] =
pmap_steal_memory(PAGE_SIZE);
if (!xlr_secondary_gp[i])
panic("Allocation failed for secondary cpu stacks");
xlr_secondary_sp[i] =
xlr_secondary_gp[i]+PAGE_SIZE-CALLFRAME_SIZ;
xlr_secondary_sp[i] =
xlr_secondary_gp[i] + PAGE_SIZE - CALLFRAME_SIZ;
xlr_secondary_gp[i] = (unsigned long)&_gp;
/*Build ltop and ptol cpu map.*/
/* Build ltop and ptol cpu map. */
cpu_ltop_map[j] = i;
cpu_ptol_map[i] = j;
if((i & 0x3) == 0) /*store thread0 of each core */
xlr_core_cpu_mask |= (1<<j);
mips_cpu_logical_mask |= (1<<j);
if ((i & 0x3) == 0) /* store thread0 of each core */
xlr_core_cpu_mask |= (1 << j);
mips_cpu_logical_mask |= (1 << j);
j++;
}
}
mips_cpu_online_mask |= xlr_boot1_info.cpu_online_map;
wakeup = ((void (*)(void *, void *, unsigned int))
(unsigned long)(xlr_boot1_info.wakeup));
wakeup = ((void (*) (void *, void *, unsigned int))
(unsigned long)(xlr_boot1_info.wakeup));
printf("Waking up CPUs 0x%llx.\n", xlr_boot1_info.cpu_online_map & ~(0x1U));
if(xlr_boot1_info.cpu_online_map & ~(0x1U))
wakeup(xlr_secondary_entry, 0,
(unsigned int)xlr_boot1_info.cpu_online_map);
if (xlr_boot1_info.cpu_online_map & ~(0x1U))
wakeup(xlr_secondary_entry, 0,
(unsigned int)xlr_boot1_info.cpu_online_map);
#endif
/* xlr specific post initialization */
/* The expectation is that mutex_init() is already done
* in mips_init()
* XXX NOTE: We may need to move this to SMP based init code
* for each CPU, later.
*/
/* xlr specific post initialization */
/*
* The expectation is that mutex_init() is already done in
* mips_init() XXX NOTE: We may need to move this to SMP based init
* code for each CPU, later.
*/
on_chip_init();
tick_init();
}
@ -530,8 +545,8 @@ platform_start(__register_t a0 __unused,
void
platform_identify(void)
{
printf("Board [%d:%d], processor 0x%08x\n", (int) xlr_boot1_info.board_major_version,
(int) xlr_boot1_info.board_minor_version, mips_rd_prid());
printf("Board [%d:%d], processor 0x%08x\n", (int)xlr_boot1_info.board_major_version,
(int)xlr_boot1_info.board_minor_version, mips_rd_prid());
}
@ -559,16 +574,18 @@ platform_trap_exit(void)
}
*/
void disable_msgring_int(void *arg) ;
void enable_msgring_int(void *arg) ;
void
disable_msgring_int(void *arg);
void
enable_msgring_int(void *arg);
void xlr_msgring_handler(struct trapframe *tf);
void msgring_process_fast_intr(void *arg);
struct msgring_ithread {
struct thread *i_thread;
u_int i_pending;
u_int i_flags;
int i_cpu;
u_int i_pending;
u_int i_flags;
int i_cpu;
};
struct msgring_ithread msgring_ithreads[MAXCPU];
char ithd_name[MAXCPU][32];
@ -580,32 +597,35 @@ msgring_process_fast_intr(void *arg)
volatile struct msgring_ithread *it;
struct proc *p;
struct thread *td;
/* wakeup an appropriate intr_thread for processing this interrupt */
it = (volatile struct msgring_ithread *)&msgring_ithreads[cpu];
td = it->i_thread;
p = td->td_proc;
/* Interrupt thread will enable the interrupts after processing
all messages
*/
/*
* Interrupt thread will enable the interrupts after processing all
* messages
*/
disable_msgring_int(NULL);
it->i_pending = 1;
if (TD_AWAITING_INTR(td)) {
thread_lock(td);
thread_lock(td);
CTR3(KTR_INTR, "%s: schedule pid %d (%s)", __func__, p->p_pid,
p->p_comm);
p->p_comm);
TD_CLR_IWAIT(td);
sched_add(td, SRQ_INTR);
thread_unlock(td);
thread_unlock(td);
} else {
CTR4(KTR_INTR, "%s: pid %d (%s): state %d",
__func__, p->p_pid, p->p_comm, td->td_state);
__func__, p->p_pid, p->p_comm, td->td_state);
}
}
#define MIT_DEAD 4
static void
msgring_process(void * arg)
msgring_process(void *arg)
{
volatile struct msgring_ithread *ithd;
struct thread *td;
@ -615,43 +635,43 @@ msgring_process(void * arg)
p = td->td_proc;
ithd = (volatile struct msgring_ithread *)arg;
KASSERT(ithd->i_thread == td,
("%s:msg_ithread and proc linkage out of sync", __func__));
("%s:msg_ithread and proc linkage out of sync", __func__));
/* First bind this thread to the right CPU */
thread_lock(td);
sched_bind(td, ithd->i_cpu);
thread_unlock(td);
// printf("Started %s on CPU %d\n", __FUNCTION__, ithd->i_cpu);
//printf("Started %s on CPU %d\n", __FUNCTION__, ithd->i_cpu);
while(1) {
while (1) {
if (ithd->i_flags & MIT_DEAD) {
CTR3(KTR_INTR, "%s: pid %d (%s) exiting", __func__,
p->p_pid, p->p_comm);
p->p_pid, p->p_comm);
kthread_exit();
}
while (ithd->i_pending) {
/*
* This might need a full read and write barrier
* to make sure that this write posts before any
* of the memory or device accesses in the
* handlers.
* This might need a full read and write barrier to
* make sure that this write posts before any of the
* memory or device accesses in the handlers.
*/
atomic_store_rel_int(&ithd->i_pending, 0);
xlr_msgring_handler(NULL);
}
if (!ithd->i_pending && !(ithd->i_flags & MIT_DEAD)) {
thread_lock(td);
thread_lock(td);
sched_class(td, PRI_ITHD);
TD_SET_IWAIT(td);
thread_unlock(td);
thread_unlock(td);
enable_msgring_int(NULL);
mi_switch(SW_VOL, NULL);
}
}
}
void platform_prep_smp_launch(void)
void
platform_prep_smp_launch(void)
{
int cpu;
uint32_t cpu_mask;
@ -664,26 +684,26 @@ void platform_prep_smp_launch(void)
/* Create kernel threads for message ring interrupt processing */
/* Currently create one task for thread 0 of each core */
for(cpu=0; cpu < MAXCPU; cpu+=1) {
for (cpu = 0; cpu < MAXCPU; cpu += 1) {
if(!((1 << cpu) & cpu_mask))
if (!((1 << cpu) & cpu_mask))
continue;
if((cpu_ltop_map[cpu]%4) != 0)
if ((cpu_ltop_map[cpu] % 4) != 0)
continue;
ithd = &msgring_ithreads[cpu];
sprintf(ithd_name[cpu], "msg_intr%d", cpu);
error = kproc_create(msgring_process,
(void *)ithd,
&p,
(RFSTOPPED | RFHIGHPID),
2,
ithd_name[cpu]);
(void *)ithd,
&p,
(RFSTOPPED | RFHIGHPID),
2,
ithd_name[cpu]);
if (error)
panic("kproc_create() failed with %d", error);
td = FIRST_THREAD_IN_PROC(p); /* XXXKSE */
td = FIRST_THREAD_IN_PROC(p); /* XXXKSE */
thread_lock(td);
sched_class(td, PRI_ITHD);
@ -695,4 +715,3 @@ void platform_prep_smp_launch(void)
CTR2(KTR_INTR, "%s: created %s", __func__, ithd_name[cpu]);
}
}

264
sys/mips/rmi/xlr_pci.c
View File

@ -71,24 +71,24 @@
#define MSI_MIPS_ADDR_DEST 0x000ff000
#define MSI_MIPS_ADDR_RH 0x00000008
# define MSI_MIPS_ADDR_RH_OFF 0x00000000
# define MSI_MIPS_ADDR_RH_ON 0x00000008
#define MSI_MIPS_ADDR_RH_OFF 0x00000000
#define MSI_MIPS_ADDR_RH_ON 0x00000008
#define MSI_MIPS_ADDR_DM 0x00000004
# define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000
# define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004
#define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000
#define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004
/* Fields in data for Intel MSI messages. */
#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */
# define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */
# define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */
#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */
#define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */
#define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */
#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */
# define MSI_MIPS_DATA_DEASSERT 0x00000000
# define MSI_MIPS_DATA_ASSERT 0x00004000
#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */
#define MSI_MIPS_DATA_DEASSERT 0x00000000
#define MSI_MIPS_DATA_ASSERT 0x00004000
#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */
# define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */
# define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */
#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */
#define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */
#define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */
#define MSI_MIPS_DATA_INTVEC 0x000000ff
@ -105,9 +105,9 @@
MSI_MIPS_DATA_ASSERT | (irq))
struct xlr_hose_softc {
int junk; /* no softc */
int junk; /* no softc */
};
static devclass_t pcib_devclass;
static devclass_t pcib_devclass;
static int pci_bus_status = 0;
static void *pci_config_base;
@ -127,13 +127,13 @@ xlr_pcib_probe(device_t dev)
}
static int
xlr_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
xlr_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t * result)
{
#if 0
device_printf(dev, "xlr_pcib_read_ivar : read ivar %d for child %s\n", which, device_get_nameunit(child));
#endif
switch (which) {
case PCIB_IVAR_BUS:
case PCIB_IVAR_BUS:
*result = 0;
return 0;
}
@ -151,33 +151,37 @@ xlr_pcib_maxslots(device_t dev)
#define pci_cfg_offset(bus,slot,devfn,where) (((bus)<<16) + ((slot) << 11)+((devfn)<<8)+(where))
static __inline__ void disable_and_clear_cache_error(void)
{
uint64_t lsu_cfg0 = read_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CFG0_REGID);
lsu_cfg0 = lsu_cfg0 & ~0x2e;
write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CFG0_REGID, lsu_cfg0);
/* Clear cache error log */
write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID, 0);
}
static __inline__ void clear_and_enable_cache_error(void)
{
uint64_t lsu_cfg0 = 0;
/* first clear the cache error logging register */
write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID, 0);
write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERROVF_REGID, 0);
write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERRINT_REGID, 0);
lsu_cfg0 = read_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CFG0_REGID);
lsu_cfg0 = lsu_cfg0 | 0x2e;
write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CFG0_REGID, lsu_cfg0);
}
static uint32_t phoenix_pciread(u_int b, u_int s, u_int f,
u_int reg, int width)
static __inline__ void
disable_and_clear_cache_error(void)
{
uint32_t data = 0;
uint64_t lsu_cfg0 = read_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CFG0_REGID);
lsu_cfg0 = lsu_cfg0 & ~0x2e;
write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CFG0_REGID, lsu_cfg0);
/* Clear cache error log */
write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID, 0);
}
static __inline__ void
clear_and_enable_cache_error(void)
{
uint64_t lsu_cfg0 = 0;
/* first clear the cache error logging register */
write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID, 0);
write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERROVF_REGID, 0);
write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERRINT_REGID, 0);
lsu_cfg0 = read_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CFG0_REGID);
lsu_cfg0 = lsu_cfg0 | 0x2e;
write_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CFG0_REGID, lsu_cfg0);
}
static uint32_t
phoenix_pciread(u_int b, u_int s, u_int f,
u_int reg, int width)
{
uint32_t data = 0;
if ((width == 2) && (reg & 1))
return 0xFFFFFFFF;
@ -197,19 +201,20 @@ static uint32_t phoenix_pciread(u_int b, u_int s, u_int f,
return data;
}
static void phoenix_pciwrite(u_int b, u_int s, u_int f,
u_int reg, u_int val, int width)
{
static void
phoenix_pciwrite(u_int b, u_int s, u_int f,
u_int reg, u_int val, int width)
{
uint32_t cfgaddr = pci_cfg_offset(b, s, f, reg);
uint32_t data = 0;
if ((width == 2) && (reg & 1))
return ;
return;
else if ((width == 4) && (reg & 3))
return ;
return;
if (!pci_bus_status)
return ;
return;
if (width == 1) {
data = pci_cfg_read_32bit(cfgaddr);
@ -220,88 +225,89 @@ static void phoenix_pciwrite(u_int b, u_int s, u_int f,
data = (data & ~(0xffff << ((reg & 3) << 3))) |
(val << ((reg & 3) << 3));
} else {
data = val;
data = val;
}
pci_cfg_write_32bit(cfgaddr, data);
return ;
return;
}
static uint32_t pci_cfg_read_32bit(uint32_t addr)
static uint32_t
pci_cfg_read_32bit(uint32_t addr)
{
uint32_t temp = 0;
uint32_t *p = (uint32_t *) ((uint32_t)pci_config_base + (addr & ~3));
uint64_t cerr_cpu_log = 0;
uint32_t temp = 0;
uint32_t *p = (uint32_t *) ((uint32_t) pci_config_base + (addr & ~3));
uint64_t cerr_cpu_log = 0;
disable_and_clear_cache_error();
temp = SWAP32(*p);
temp = SWAP32(*p);
/* Read cache err log */
cerr_cpu_log = read_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID);
/* Read cache err log */
cerr_cpu_log = read_64bit_phnx_ctrl_reg(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID);
if(cerr_cpu_log)
{
/* Device don't exist. */
temp = ~0x0;
}
if (cerr_cpu_log) {
/* Device don't exist. */
temp = ~0x0;
}
clear_and_enable_cache_error();
return temp;
return temp;
}
static void pci_cfg_write_32bit(uint32_t addr, uint32_t data)
static void
pci_cfg_write_32bit(uint32_t addr, uint32_t data)
{
unsigned int *p = (unsigned int *)((uint32_t)pci_config_base + (addr & ~3));
unsigned int *p = (unsigned int *)((uint32_t) pci_config_base + (addr & ~3));
*p = SWAP32(data);
*p = SWAP32(data);
}
static u_int32_t
xlr_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
u_int reg, int width)
u_int reg, int width)
{
return phoenix_pciread(b, s, f, reg, width);
}
static void
xlr_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
u_int reg, u_int32_t val, int width)
u_int reg, u_int32_t val, int width)
{
phoenix_pciwrite(b, s, f, reg, val, width);
}
static int xlr_pcib_attach(device_t dev)
static int
xlr_pcib_attach(device_t dev)
{
device_add_child(dev, "pci", 0);
bus_generic_attach(dev);
return 0;
}
#define PCIE_LINK_STATE 0x4000
#define PCIE_LINK_STATE 0x4000
static void
xlr_pcib_identify(driver_t *driver, device_t parent)
xlr_pcib_identify(driver_t * driver, device_t parent)
{
xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET);
xlr_reg_t reg_link0 = xlr_read_reg(pcie_mmio_le, (0x80 >> 2));
xlr_reg_t reg_link1 = xlr_read_reg(pcie_mmio_le, (0x84 >> 2));
xlr_reg_t reg_link0 = xlr_read_reg(pcie_mmio_le, (0x80 >> 2));
xlr_reg_t reg_link1 = xlr_read_reg(pcie_mmio_le, (0x84 >> 2));
if ((uint16_t)reg_link0 & PCIE_LINK_STATE) {
if ((uint16_t) reg_link0 & PCIE_LINK_STATE) {
device_printf(parent, "Link 0 up\n");
}
if ((uint16_t)reg_link1 & PCIE_LINK_STATE) {
if ((uint16_t) reg_link1 & PCIE_LINK_STATE) {
device_printf(parent, "Link 1 up\n");
}
BUS_ADD_CHILD(parent, 0, "pcib", 0);
}
static int
xlr_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs);
xlr_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs);
static int
xlr_release_msi(device_t pcib, device_t dev, int count, int *irqs);
xlr_release_msi(device_t pcib, device_t dev, int count, int *irqs);
static int
xlr_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
@ -310,13 +316,13 @@ xlr_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
int i;
device_t parent, tmp;
/* find the lane on which the slot is connected to */
tmp = dev;
while (1) {
parent = device_get_parent(tmp);
parent = device_get_parent(tmp);
if (parent == NULL || parent == pcib) {
device_printf(dev, "Cannot find parent bus\n");
device_printf(dev, "Cannot find parent bus\n");
return ENXIO;
}
if (strcmp(device_get_nameunit(parent), "pci0") == 0)
@ -324,49 +330,58 @@ xlr_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
tmp = parent;
}
switch (pci_get_slot(tmp)) {
case 0: pciirq = PIC_PCIE_LINK0_IRQ; break;
case 1: pciirq = PIC_PCIE_LINK1_IRQ; break;
case 2: pciirq = PIC_PCIE_LINK2_IRQ; break;
case 3: pciirq = PIC_PCIE_LINK3_IRQ; break;
default: return ENXIO;
switch (pci_get_slot(tmp)) {
case 0:
pciirq = PIC_PCIE_LINK0_IRQ;
break;
case 1:
pciirq = PIC_PCIE_LINK1_IRQ;
break;
case 2:
pciirq = PIC_PCIE_LINK2_IRQ;
break;
case 3:
pciirq = PIC_PCIE_LINK3_IRQ;
break;
default:
return ENXIO;
}
irqs[0] = pciirq;
/*
For now put in some fixed values for the other requested MSI,
TODO handle multiple messages
*/
for (i=1; i<count; i++)
irqs[i] = pciirq + 64*i;
irqs[0] = pciirq;
/*
* For now put in some fixed values for the other requested MSI,
* TODO handle multiple messages
*/
for (i = 1; i < count; i++)
irqs[i] = pciirq + 64 * i;
return 0;
return 0;
}
static int
xlr_release_msi(device_t pcib, device_t dev, int count, int *irqs)
{
device_printf(dev, "%s: msi release %d\n", device_get_nameunit(pcib), count);
return 0;
return 0;
}
static int
xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, uint32_t *data);
xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t * addr, uint32_t * data);
static int
xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, uint32_t *data)
xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t * addr, uint32_t * data)
{
switch(irq) {
case PIC_PCIE_LINK0_IRQ:
case PIC_PCIE_LINK1_IRQ:
case PIC_PCIE_LINK2_IRQ:
case PIC_PCIE_LINK3_IRQ:
switch (irq) {
case PIC_PCIE_LINK0_IRQ:
case PIC_PCIE_LINK1_IRQ:
case PIC_PCIE_LINK2_IRQ:
case PIC_PCIE_LINK3_IRQ:
*addr = MIPS_MSI_ADDR(0);
*data = MIPS_MSI_DATA(irq);
return 0;
default:
device_printf(dev, "%s: map_msi for irq %d - ignored", device_get_nameunit(pcib),
irq);
irq);
return (ENXIO);
}
@ -374,32 +389,32 @@ xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, uint32_t *data
static device_method_t xlr_pcib_methods[] = {
/* Device interface */
DEVMETHOD(device_identify, xlr_pcib_identify),
DEVMETHOD(device_probe, xlr_pcib_probe),
DEVMETHOD(device_attach, xlr_pcib_attach),
DEVMETHOD(device_identify, xlr_pcib_identify),
DEVMETHOD(device_probe, xlr_pcib_probe),
DEVMETHOD(device_attach, xlr_pcib_attach),
/* Bus interface */
DEVMETHOD(bus_print_child, bus_generic_print_child),
DEVMETHOD(bus_read_ivar, xlr_pcib_read_ivar),
DEVMETHOD(bus_alloc_resource, xlr_pci_alloc_resource),
DEVMETHOD(bus_release_resource, pci_release_resource),
DEVMETHOD(bus_print_child, bus_generic_print_child),
DEVMETHOD(bus_read_ivar, xlr_pcib_read_ivar),
DEVMETHOD(bus_alloc_resource, xlr_pci_alloc_resource),
DEVMETHOD(bus_release_resource, pci_release_resource),
DEVMETHOD(bus_activate_resource, pci_activate_resource),
DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
DEVMETHOD(bus_setup_intr, mips_platform_pci_setup_intr),
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
DEVMETHOD(bus_setup_intr, mips_platform_pci_setup_intr),
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
/* pcib interface */
DEVMETHOD(pcib_maxslots, xlr_pcib_maxslots),
DEVMETHOD(pcib_read_config, xlr_pcib_read_config),
DEVMETHOD(pcib_write_config, xlr_pcib_write_config),
DEVMETHOD(pcib_maxslots, xlr_pcib_maxslots),
DEVMETHOD(pcib_read_config, xlr_pcib_read_config),
DEVMETHOD(pcib_write_config, xlr_pcib_write_config),
DEVMETHOD(pcib_route_interrupt, mips_pci_route_interrupt),
DEVMETHOD(pcib_alloc_msi, xlr_alloc_msi),
DEVMETHOD(pcib_release_msi, xlr_release_msi),
DEVMETHOD(pcib_map_msi, xlr_map_msi),
DEVMETHOD(pcib_route_interrupt, mips_pci_route_interrupt),
{ 0, 0 }
DEVMETHOD(pcib_alloc_msi, xlr_alloc_msi),
DEVMETHOD(pcib_release_msi, xlr_release_msi),
DEVMETHOD(pcib_map_msi, xlr_map_msi),
{0, 0}
};
static driver_t xlr_pcib_driver = {
@ -409,4 +424,3 @@ static driver_t xlr_pcib_driver = {
};
DRIVER_MODULE(pcib, nexus, xlr_pcib_driver, pcib_devclass, 0, 0);

219
sys/mips/rmi/xlrconfig.h
View File

@ -182,146 +182,155 @@
* bits 0...7 are same as status register 8...15
*/
static inline uint64_t read_c0_eirr64(void)
static inline uint64_t
read_c0_eirr64(void)
{
__uint32_t high, low;
__uint32_t high, low;
__asm__ __volatile__ (
".set push\n"
".set noreorder\n"
".set noat\n"
".set mips4\n"
__asm__ __volatile__(
".set push\n"
".set noreorder\n"
".set noat\n"
".set mips4\n"
".word 0x40214806 \n\t"
"nop \n\t"
"dsra32 %0, $1, 0 \n\t"
"sll %1, $1, 0 \n\t"
".word 0x40214806 \n\t"
"nop \n\t"
"dsra32 %0, $1, 0 \n\t"
"sll %1, $1, 0 \n\t"
".set pop\n"
".set pop\n"
: "=r" (high), "=r" (low)
);
: "=r"(high), "=r"(low)
);
return ( ((__uint64_t)high) << 32) | low;
return (((__uint64_t) high) << 32) | low;
}
static inline __uint64_t read_c0_eimr64(void)
static inline __uint64_t
read_c0_eimr64(void)
{
__uint32_t high, low;
__uint32_t high, low;
__asm__ __volatile__ (
".set push\n"
".set noreorder\n"
".set noat\n"
".set mips4\n"
__asm__ __volatile__(
".set push\n"
".set noreorder\n"
".set noat\n"
".set mips4\n"
".word 0x40214807 \n\t"
"nop \n\t"
"dsra32 %0, $1, 0 \n\t"
"sll %1, $1, 0 \n\t"
".word 0x40214807 \n\t"
"nop \n\t"
"dsra32 %0, $1, 0 \n\t"
"sll %1, $1, 0 \n\t"
".set pop\n"
".set pop\n"
: "=r" (high), "=r" (low)
);
: "=r"(high), "=r"(low)
);
return ( ((__uint64_t)high) << 32) | low;
return (((__uint64_t) high) << 32) | low;
}
static inline void write_c0_eirr64(__uint64_t value)
{
__uint32_t low, high;
high = value >> 32;
low = value & 0xffffffff;
__asm__ __volatile__ (
".set push\n"
".set noreorder\n"
".set noat\n"
".set mips4\n\t"
"dsll32 $2, %1, 0 \n\t"
"dsll32 $1, %0, 0 \n\t"
"dsrl32 $2, $2, 0 \n\t"
"or $1, $1, $2 \n\t"
".word 0x40a14806 \n\t"
"nop \n\t"
".set pop\n"
:
: "r" (high), "r" (low)
: "$1", "$2");
}
static inline void write_c0_eimr64(__uint64_t value)
static inline void
write_c0_eirr64(__uint64_t value)
{
__uint32_t low, high;
__uint32_t low, high;
high = value >> 32;
low = value & 0xffffffff;
high = value >> 32;
low = value & 0xffffffff;
__asm__ __volatile__ (
".set push\n"
".set noreorder\n"
".set noat\n"
".set mips4\n\t"
__asm__ __volatile__(
".set push\n"
".set noreorder\n"
".set noat\n"
".set mips4\n\t"
"dsll32 $2, %1, 0 \n\t"
"dsll32 $1, %0, 0 \n\t"
"dsrl32 $2, $2, 0 \n\t"
"or $1, $1, $2 \n\t"
".word 0x40a14807 \n\t"
"nop \n\t"
"dsll32 $2, %1, 0 \n\t"
"dsll32 $1, %0, 0 \n\t"
"dsrl32 $2, $2, 0 \n\t"
"or $1, $1, $2 \n\t"
".word 0x40a14806 \n\t"
"nop \n\t"
".set pop\n"
".set pop\n"
:
: "r" (high), "r" (low)
: "$1", "$2");
:
: "r"(high), "r"(low)
: "$1", "$2");
}
static __inline__ int xlr_test_and_set(int *lock)
static inline void
write_c0_eimr64(__uint64_t value)
{
int oldval = 0;
__uint32_t low, high;
__asm__ __volatile__ (".set push\n"
".set noreorder\n"
"move $9, %2\n"
"li $8, 1\n"
//"swapw $8, $9\n"
".word 0x71280014\n"
"move %1, $8\n"
".set pop\n"
: "+m" (*lock), "=r" (oldval)
: "r" ((unsigned long)lock)
: "$8", "$9"
);
return (oldval == 0 ? 1/*success*/ : 0/*failure*/);
high = value >> 32;
low = value & 0xffffffff;
__asm__ __volatile__(
".set push\n"
".set noreorder\n"
".set noat\n"
".set mips4\n\t"
"dsll32 $2, %1, 0 \n\t"
"dsll32 $1, %0, 0 \n\t"
"dsrl32 $2, $2, 0 \n\t"
"or $1, $1, $2 \n\t"
".word 0x40a14807 \n\t"
"nop \n\t"
".set pop\n"
:
: "r"(high), "r"(low)
: "$1", "$2");
}
static __inline__ uint32_t xlr_mfcr(uint32_t reg)
static __inline__ int
xlr_test_and_set(int *lock)
{
int oldval = 0;
__asm__ __volatile__(".set push\n"
".set noreorder\n"
"move $9, %2\n"
"li $8, 1\n"
// "swapw $8, $9\n"
".word 0x71280014\n"
"move %1, $8\n"
".set pop\n"
: "+m"(*lock), "=r"(oldval)
: "r"((unsigned long)lock)
: "$8", "$9"
);
return (oldval == 0 ? 1 /* success */ : 0 /* failure */ );
}
static __inline__ uint32_t
xlr_mfcr(uint32_t reg)
{
uint32_t val;
__asm__ __volatile__ (
"move $8, %1\n"
".word 0x71090018\n"
"move %0, $9\n"
: "=r"(val)
: "r"(reg) : "$8", "$9");
__asm__ __volatile__(
"move $8, %1\n"
".word 0x71090018\n"
"move %0, $9\n"
: "=r"(val)
: "r"(reg):"$8", "$9");
return val;
}
static __inline__ void xlr_mtcr(uint32_t reg, uint32_t val)
static __inline__ void
xlr_mtcr(uint32_t reg, uint32_t val)
{
__asm__ __volatile__ (
"move $8, %1\n"
"move $9, %0\n"
".word 0x71090019\n"
::"r"(val), "r"(reg)
: "$8", "$9");
__asm__ __volatile__(
"move $8, %1\n"
"move $9, %0\n"
".word 0x71090019\n"
:: "r"(val), "r"(reg)
: "$8", "$9");
}
#endif

17
sys/mips/rmi/xls_ehci.c
View File

@ -72,12 +72,13 @@ __FBSDID("$FreeBSD: src/sys/dev/usb/ehci_pci.c,v 1.18.2.4 2008/04/23 18:54:51 jh
/*#include <dev/usb/usb_mem.h> */
#include <mips/rmi/ehcireg.h>
#include <mips/rmi/ehcivar.h>
#include <mips/rmi/ehcivar.h>
#ifdef USB_DEBUG
#define EHCI_DEBUG USB_DEBUG
#define DPRINTF(x) do { if (ehcidebug) logprintf x; } while (0)
extern int ehcidebug;
#else
#define DPRINTF(x)
#endif
@ -158,8 +159,8 @@ ehci_xls_attach(device_t self)
sc->sc_bus.usbrev = USBREV_2_0;
rid = 0;
sc->io_res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid,
0ul, ~0ul, 0x400, RF_ACTIVE);
sc->io_res = bus_alloc_resource(self, SYS_RES_MEMORY, &rid,
0ul, ~0ul, 0x400, RF_ACTIVE);
if (!sc->io_res) {
device_printf(self, "Could not map memory\n");
return ENXIO;
@ -169,7 +170,7 @@ ehci_xls_attach(device_t self)
rid = 0;
sc->irq_res = bus_alloc_resource(self, SYS_RES_IRQ, &rid,
39, 39, 1, RF_SHAREABLE | RF_ACTIVE);
39, 39, 1, RF_SHAREABLE | RF_ACTIVE);
if (sc->irq_res == NULL) {
device_printf(self, "Could not allocate irq\n");
ehci_xls_detach(self);
@ -195,7 +196,6 @@ ehci_xls_attach(device_t self)
ehci_xls_detach(self);
return ENXIO;
}
/*
* Find companion controllers. According to the spec they always
* have lower function numbers so they should be enumerated already.
@ -207,7 +207,6 @@ ehci_xls_attach(device_t self)
ehci_xls_detach(self);
return ENXIO;
}
sc->sc_ncomp = 0;
ehci_xls_takecontroller(self);
@ -216,7 +215,6 @@ ehci_xls_attach(device_t self)
sc->sc_flags |= EHCI_SCFLG_DONEINIT;
err = device_probe_and_attach(sc->sc_bus.bdev);
}
if (err) {
device_printf(self, "USB init failed err=%d\n", err);
ehci_xls_detach(self);
@ -234,7 +232,6 @@ ehci_xls_detach(device_t self)
ehci_detach(sc, 0);
sc->sc_flags &= ~EHCI_SCFLG_DONEINIT;
}
/*
* disable interrupts that might have been switched on in ehci_init
*/
@ -270,13 +267,13 @@ ehci_xls_detach(device_t self)
static void
ehci_xls_takecontroller(device_t self)
{
//device_printf(self, "In func %s\n", __func__);
//device_printf(self, "In func %s\n", __func__);
}
static void
ehci_xls_givecontroller(device_t self)
{
//device_printf(self, "In func %s\n", __func__);
//device_printf(self, "In func %s\n", __func__);
}
static device_method_t ehci_methods[] = {