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Doug noticed that the bit values for _MCPCIA_INT_ACK0/_MCPCIA_INT_ACK1

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made no sense in the context of wrapping them within the _SYBRIDGE macro-
or anything like it- so we concluded that this must have been a typo
in the docs.  This also doesn't use the same bridge offset as anything
else.

Add some defines for the INT_CTL register.
This commit is contained in:
Matt Jacob 2001-02-13 22:44:21 +00:00
parent 0346cda4f9
commit fcd34891a6
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=72464
1 changed files with 13 additions and 4 deletions
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17
sys/alpha/mcbus/mcpciareg.h
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@ -165,8 +165,8 @@
#define _MCPCIA_INT_MASK0 0x000000640 /* PCI Int Mask 0 */
#define _MCPCIA_INT_MASK1 0x000000680 /* PCI Int Mask 1 */
#define _MCPCIA_INT_ACK0 0x100003F00 /* PCI Int Ack 0 */
#define _MCPCIA_INT_ACK1 0x100003F40 /* PCI Int Ack 1 */
#define _MCPCIA_INT_ACK0 0x010003F00 /* PCI Int Ack 0 */
#define _MCPCIA_INT_ACK1 0x010003F40 /* PCI Int Ack 1 */
#define _MCPCIA_PERF_MON 0x000000300 /* PCI Perf Monitor */
#define _MCPCIA_PERF_CONT 0x000000340 /* PCI Perf Monitor Control */
@ -226,8 +226,6 @@
#define MCPCIA_INT_ADR_EXT(ccp) (_SYBRIDGE(ccp) | _MCPCIA_INT_ADR_EXT)
#define MCPCIA_INT_MASK0(ccp) (_SYBRIDGE(ccp) | _MCPCIA_INT_MASK0)
#define MCPCIA_INT_MASK1(ccp) (_SYBRIDGE(ccp) | _MCPCIA_INT_MASK1)
#define MCPCIA_INT_ACK0(ccp) (_SYBRIDGE(ccp) | _MCPCIA_INT_ACK0)
#define MCPCIA_INT_ACK1(ccp) (_SYBRIDGE(ccp) | _MCPCIA_INT_ACK1)
#define MCPCIA_PERF_MON(ccp) (_SYBRIDGE(ccp) | _MCPCIA_PERF_MON)
#define MCPCIA_PERF_CONT(ccp) (_SYBRIDGE(ccp) | _MCPCIA_PERF_CONT)
#define MCPCIA_CAP_DIAG(ccp) (_SYBRIDGE(ccp) | _MCPCIA_CAP_DIAG)
@ -260,6 +258,11 @@
#define MCPCIA_T3_BASE(ccp) (_SYBRIDGE(ccp) | _MCPCIA_T3_BASE)
#define MCPCIA_W_DAC(ccp) (_SYBRIDGE(ccp) | _MCPCIA_W_DAC)
#define MCPCIA_INT_ACK0(ccp) \
((ccp)->sysbase | MCPCIA_PCI_IACK | _MCPCIA_INT_ACK0)
#define MCPCIA_INT_ACK1(ccp) \
((ccp)->sysbase | MCPCIA_PCI_IACK | _MCPCIA_INT_ACK1)
/*
* This is here for what error handling will get as a collected subpacket.
*/
@ -385,8 +388,14 @@ struct mcpcia_iodsnap {
* in imask0 if we want to have them vectored to PALcode for appropriate
* dispatch.
*/
/*
* Bits for INT_CTL register
*/
#define MCPCIA_INTCTL_EN_INT 0x1 /* enable interrupts */
#define MCPCIA_INTCTL_EN_INT_NUM 0x2 /* enable INT_ADR/ADR_EXT */
/*
* Bits for MASK0 registers.
* bits 0-15 correspond to 4 slots (time 4 buspins) for each PCI bus.
* bit 16 is the NCR810 onboard SCSI interrupt.
* bits 19-20 are reserved.