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6b06709221
Copy the support files for the Octeon 1 CPU from sys/mips/octeon1 on the projects/mips side to sys/mips/cavium on the head side to conform to the other vendor code. This code was contributed by Cavium to the project and forward ported by Warner Losh, with some additional code from Randal Stewart. # I'll fix the building problems the move creates in a future commit.
36 lines
1.2 KiB
C
36 lines
1.2 KiB
C
/*
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* octeon_ebt3000_cf.h
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*
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*/
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#ifndef __OCTEON_EBT3000_H__
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#define __OCTEON_EBT3000_H__
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#define OCTEON_CF_COMMON_BASE_ADDR (0x1d000000 | (1 << 11))
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#define OCTEON_MIO_BOOT_REG_CFGX(offset) (0x8001180000000000ull + ((offset) * 8))
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typedef union
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{
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uint64_t word64;
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struct
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{
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uint64_t reserved : 27; /**< Reserved */
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uint64_t sam : 1; /**< Region 0 SAM */
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uint64_t we_ext : 2; /**< Region 0 write enable count extension */
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uint64_t oe_ext : 2; /**< Region 0 output enable count extension */
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uint64_t en : 1; /**< Region 0 enable */
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uint64_t orbit : 1; /**< No function for region 0 */
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uint64_t ale : 1; /**< Region 0 ALE mode */
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uint64_t width : 1; /**< Region 0 bus width */
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uint64_t size : 12; /**< Region 0 size */
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uint64_t base : 16; /**< Region 0 base address */
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} bits;
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} octeon_mio_boot_reg_cfgx_t;
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#endif /* __OCTEON_EBT3000_H__ */
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