mirror of
https://github.com/freebsd/freebsd-src.git
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257c916acf
compile and many of them may disappear. For example the xlr_boot1_console.c is old code that is ifdef'd out. I will clean these sorts of things up as I make progress on the port. So far the only thing I have I think straightened out is the bits around the interupt handling... and hey that may be broke ;-)
1183 lines
20 KiB
INI
1183 lines
20 KiB
INI
/*-
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* Copyright (c) 2003-2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of RMI Corporation, nor the names of its contributors,
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RMI_BSD */
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/*
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* This file defines the message ring configuration for phoenix-8. It tries to allow
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* many different point-point communications between the message stations on the message ring
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* and as result is _not_ the best configuration for performance
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*
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* The message ring on phoenix family of processors connects the cpus, gmacs, xgmac/spi4,
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* security engine and the general purpose DMA engines. It provides a high bandwidth,
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* low latency communication links. On traditional processors, this communication goes through
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* which inherently does not scale very well with increasing number of cpus.
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*
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* Message ring has an in-built flow control mechanism. Every agent/station on the ring has to
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* have software configured credits to send messages to any agent. Every receiving agent on the
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* ring has a 256 entry FIFO that can divided into "buckets". All addressing on the ring is
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* in terms of buckets. There are a total 128 buckets on the ring. The total number of credits
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* across all sending agents should not exceed the bucket size.
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*
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* Below are the receiving agents and the max number of buckets they can have
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* CPU 0 : 8 buckets
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* CPU 1 : 8 buckets
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* CPU 2 : 8 buckets
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* CPU 3 : 8 buckets
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* CPU 4 : 8 buckets
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* CPU 5 : 8 buckets
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* CPU 6 : 8 buckets
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* CPU 7 : 8 buckets
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*
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* XGMAC 0 / SPI4 0
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* TX : 16 buckets
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* FREE : 2 buckets
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* XGMAC 1 / SPI4 1
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* TX : 16 buckets
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* FREE : 2 buckets
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*
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* GMAC : 8 buckets
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*
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* SEC : 8 buckets
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*
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* DMA : 8 buckets
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*
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* The bucket size of a bucket should be aligned to the bucket's starting index in that
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* receiving station's FIFO. For example, if sizes of bucket0 and bucket1 of a station
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* are 32 and 32, bucket2's size has to be 64. bucket size 0 is valid.
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*
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* The format of the file is pretty straight forward. Each bucket definition has the size
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* and the list of sending agents to that bucket with the number of credits to send.
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*
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* Undefined buckets have a size of 0 and Tx stations have 0 credits to send to that bucket.
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*
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* Following are the currently supported bucket names
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* cpu_0_0
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* cpu_0_1
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* cpu_0_2
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* cpu_0_3
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* cpu_0_4
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* cpu_0_5
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* cpu_0_6
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* cpu_0_7
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*
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* cpu_1_0
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* cpu_1_1
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* cpu_1_2
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* cpu_1_3
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* cpu_1_4
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* cpu_1_5
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* cpu_1_6
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* cpu_1_7
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*
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* cpu_2_0
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* cpu_2_1
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* cpu_2_2
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* cpu_2_3
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* cpu_2_4
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* cpu_2_5
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* cpu_2_6
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* cpu_2_7
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*
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* cpu_3_0
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* cpu_3_1
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* cpu_3_2
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* cpu_3_3
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* cpu_3_4
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* cpu_3_5
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* cpu_3_6
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* cpu_3_7
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*
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* cpu_4_0
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* cpu_4_1
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* cpu_4_2
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* cpu_4_3
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* cpu_4_4
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* cpu_4_5
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* cpu_4_6
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* cpu_4_7
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*
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* cpu_5_0
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* cpu_5_1
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* cpu_5_2
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* cpu_5_3
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* cpu_5_4
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* cpu_5_5
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* cpu_5_6
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* cpu_5_7
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*
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* cpu_6_0
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* cpu_6_1
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* cpu_6_2
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* cpu_6_3
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* cpu_6_4
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* cpu_6_5
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* cpu_6_6
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* cpu_6_7
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*
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* cpu_7_0
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* cpu_7_1
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* cpu_7_2
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* cpu_7_3
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* cpu_7_4
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* cpu_7_5
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* cpu_7_6
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* cpu_7_7
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*
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* xgs_0_tx_0
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* xgs_0_tx_1
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* xgs_0_tx_2
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* xgs_0_tx_3
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* xgs_0_tx_4
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* xgs_0_tx_5
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* xgs_0_tx_6
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* xgs_0_tx_7
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* xgs_0_tx_8
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* xgs_0_tx_9
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* xgs_0_tx_10
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* xgs_0_tx_11
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* xgs_0_tx_12
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* xgs_0_tx_13
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* xgs_0_tx_14
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* xgs_0_tx_15
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*
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* xgs_1_tx_0
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* xgs_1_tx_1
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* xgs_1_tx_2
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* xgs_1_tx_3
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* xgs_1_tx_4
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* xgs_1_tx_5
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* xgs_1_tx_6
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* xgs_1_tx_7
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* xgs_1_tx_8
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* xgs_1_tx_9
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* xgs_1_tx_10
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* xgs_1_tx_11
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* xgs_1_tx_12
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* xgs_1_tx_13
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* xgs_1_tx_14
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* xgs_1_tx_15
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*
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* gmac_rsvd_0
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* gmac_rfr_0
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* gmac_tx_0
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* gmac_tx_1
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* gmac_tx_2
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* gmac_tx_3
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* gmac_rsvd_1
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* gmac_rfr_1
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*
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* xgs_0_rsvd
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* xgs_0_rfr
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*
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* xgs_1_rsvd
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* xgs_1_rfr
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*
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* sec_pipe_0
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* sec_pipe_1
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* sec_pipe_2
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* sec_pipe_3
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* sec_rsa
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*
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* Following are the currently supported Tx Agent/Station names
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*
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* tx_stn_cpu_0
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* tx_stn_cpu_1
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* tx_stn_cpu_2
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* tx_stn_cpu_3
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* tx_stn_cpu_4
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* tx_stn_cpu_5
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* tx_stn_cpu_6
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* tx_stn_cpu_7
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*
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* tx_stn_xgs_0
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* tx_stn_xgs_1
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*
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* tx_stn_gmac
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*
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* tx_stn_dma
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*
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* tx_stn_sec
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*
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*
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*
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*/
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/*************************************************************/
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// CPU_0 Message Station
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bucket "cpu_0_0" {
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size 32;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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"tx_stn_gmac" 8;
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"tx_stn_sec" 8;
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}
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bucket "cpu_0_1" {
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size 32;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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"tx_stn_gmac" 8;
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"tx_stn_sec" 8;
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}
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bucket "cpu_0_2" {
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size 32;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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"tx_stn_gmac" 8;
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"tx_stn_sec" 8;
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}
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bucket "cpu_0_3" {
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size 32;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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"tx_stn_gmac" 8;
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"tx_stn_sec" 8;
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}
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bucket "cpu_0_4" {
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size 32;
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"tx_stn_gmac" 16;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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}
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bucket "cpu_0_5" {
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size 32;
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"tx_stn_gmac" 16;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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}
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bucket "cpu_0_6" {
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size 32;
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"tx_stn_gmac" 16;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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}
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bucket "cpu_0_7" {
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size 32;
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"tx_stn_gmac" 16;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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}
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/*************************************************************/
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// CPU_1 Message Station
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bucket "cpu_1_0" {
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size 32;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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"tx_stn_gmac" 8;
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"tx_stn_sec" 8;
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}
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bucket "cpu_1_1" {
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size 32;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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"tx_stn_gmac" 8;
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"tx_stn_sec" 8;
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}
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bucket "cpu_1_2" {
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size 32;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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"tx_stn_gmac" 8;
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"tx_stn_sec" 8;
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}
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bucket "cpu_1_3" {
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size 32;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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"tx_stn_gmac" 8;
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"tx_stn_sec" 4;
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"tx_stn_cpu_0" 4; /* NEEDED BY RMIOS IPSEC */
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}
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bucket "cpu_1_4" {
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size 32;
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"tx_stn_gmac" 16;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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}
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bucket "cpu_1_5" {
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size 32;
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"tx_stn_gmac" 16;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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}
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bucket "cpu_1_6" {
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size 32;
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"tx_stn_gmac" 16;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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}
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bucket "cpu_1_7" {
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size 32;
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"tx_stn_gmac" 16;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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}
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/*************************************************************/
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// CPU_2 Message Station
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bucket "cpu_2_0" {
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size 32;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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"tx_stn_gmac" 8;
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"tx_stn_sec" 8;
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}
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bucket "cpu_2_1" {
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size 32;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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"tx_stn_gmac" 8;
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"tx_stn_sec" 8;
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}
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bucket "cpu_2_2" {
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size 32;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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"tx_stn_gmac" 8;
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"tx_stn_sec" 8;
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}
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bucket "cpu_2_3" {
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size 32;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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"tx_stn_gmac" 8;
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"tx_stn_sec" 8;
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}
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bucket "cpu_2_4" {
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size 32;
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"tx_stn_gmac" 16;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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}
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bucket "cpu_2_5" {
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size 32;
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"tx_stn_gmac" 16;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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}
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bucket "cpu_2_6" {
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size 32;
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"tx_stn_gmac" 16;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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}
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bucket "cpu_2_7" {
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size 32;
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"tx_stn_gmac" 16;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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}
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/*************************************************************/
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// CPU_3 Message Station
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bucket "cpu_3_0" {
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size 32;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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|
"tx_stn_gmac" 8;
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"tx_stn_sec" 8;
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}
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bucket "cpu_3_1" {
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size 32;
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"tx_stn_xgs_0" 8;
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"tx_stn_xgs_1" 8;
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"tx_stn_gmac" 8;
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"tx_stn_sec" 8;
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}
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bucket "cpu_3_2" {
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size 32;
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"tx_stn_xgs_0" 8;
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|
"tx_stn_xgs_1" 8;
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|
"tx_stn_gmac" 8;
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|
"tx_stn_sec" 8;
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}
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bucket "cpu_3_3" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
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|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
|
|
"tx_stn_sec" 8;
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|
}
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|
bucket "cpu_3_4" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
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|
"tx_stn_xgs_0" 8;
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|
"tx_stn_xgs_1" 8;
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|
}
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bucket "cpu_3_5" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
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|
"tx_stn_xgs_0" 8;
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|
"tx_stn_xgs_1" 8;
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|
}
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|
bucket "cpu_3_6" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
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|
"tx_stn_xgs_1" 8;
|
|
}
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|
bucket "cpu_3_7" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
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|
"tx_stn_xgs_1" 8;
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|
}
|
|
|
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/*************************************************************/
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// CPU_4 Message Station
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|
|
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bucket "cpu_4_0" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
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|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
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|
"tx_stn_sec" 8;
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|
}
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|
bucket "cpu_4_1" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
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|
"tx_stn_sec" 8;
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|
}
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|
bucket "cpu_4_2" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
|
|
"tx_stn_sec" 8;
|
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}
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|
bucket "cpu_4_3" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
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|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
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|
"tx_stn_sec" 8;
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}
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|
bucket "cpu_4_4" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
bucket "cpu_4_5" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
bucket "cpu_4_6" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
bucket "cpu_4_7" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
|
|
/*************************************************************/
|
|
// CPU_5 Message Station
|
|
|
|
bucket "cpu_5_0" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
|
|
"tx_stn_sec" 8;
|
|
}
|
|
bucket "cpu_5_1" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
|
|
"tx_stn_sec" 8;
|
|
}
|
|
bucket "cpu_5_2" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
|
|
"tx_stn_sec" 8;
|
|
}
|
|
bucket "cpu_5_3" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
|
|
"tx_stn_sec" 8;
|
|
}
|
|
bucket "cpu_5_4" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
bucket "cpu_5_5" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
bucket "cpu_5_6" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
bucket "cpu_5_7" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
|
|
|
|
/*************************************************************/
|
|
// CPU_6 Message Station
|
|
|
|
bucket "cpu_6_0" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
|
|
"tx_stn_sec" 8;
|
|
}
|
|
bucket "cpu_6_1" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
|
|
"tx_stn_sec" 8;
|
|
}
|
|
bucket "cpu_6_2" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
|
|
"tx_stn_sec" 8;
|
|
}
|
|
bucket "cpu_6_3" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
|
|
"tx_stn_sec" 8;
|
|
}
|
|
bucket "cpu_6_4" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
bucket "cpu_6_5" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
bucket "cpu_6_6" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
bucket "cpu_6_7" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
|
|
|
|
/*************************************************************/
|
|
// CPU_7 Message Station
|
|
|
|
bucket "cpu_7_0" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
|
|
"tx_stn_sec" 8;
|
|
}
|
|
bucket "cpu_7_1" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
|
|
"tx_stn_sec" 8;
|
|
}
|
|
bucket "cpu_7_2" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
|
|
"tx_stn_sec" 8;
|
|
}
|
|
bucket "cpu_7_3" {
|
|
size 32;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
"tx_stn_gmac" 8;
|
|
"tx_stn_sec" 8;
|
|
}
|
|
bucket "cpu_7_4" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
bucket "cpu_7_5" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
bucket "cpu_7_6" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
bucket "cpu_7_7" {
|
|
size 32;
|
|
"tx_stn_gmac" 16;
|
|
"tx_stn_xgs_0" 8;
|
|
"tx_stn_xgs_1" 8;
|
|
}
|
|
|
|
|
|
/*************************************************************/
|
|
// GMAC Message Station
|
|
|
|
bucket "gmac_rfr_0" {
|
|
size 32;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 4;
|
|
"tx_stn_cpu_3" 4;
|
|
"tx_stn_cpu_4" 4;
|
|
"tx_stn_cpu_5" 4;
|
|
"tx_stn_cpu_6" 4;
|
|
"tx_stn_cpu_7" 4;
|
|
"tx_stn_gmac" 4;
|
|
}
|
|
|
|
bucket "gmac_tx_0" {
|
|
size 32;
|
|
"tx_stn_cpu_0" 4;
|
|
"tx_stn_cpu_1" 4;
|
|
"tx_stn_cpu_2" 4;
|
|
"tx_stn_cpu_3" 4;
|
|
"tx_stn_cpu_4" 4;
|
|
"tx_stn_cpu_5" 4;
|
|
"tx_stn_cpu_6" 4;
|
|
"tx_stn_cpu_7" 4;
|
|
}
|
|
|
|
bucket "gmac_tx_1" {
|
|
size 32;
|
|
"tx_stn_cpu_0" 4;
|
|
"tx_stn_cpu_1" 4;
|
|
"tx_stn_cpu_2" 4;
|
|
"tx_stn_cpu_3" 4;
|
|
"tx_stn_cpu_4" 4;
|
|
"tx_stn_cpu_5" 4;
|
|
"tx_stn_cpu_6" 4;
|
|
"tx_stn_cpu_7" 4;
|
|
}
|
|
|
|
bucket "gmac_tx_2" {
|
|
size 32;
|
|
"tx_stn_cpu_0" 4;
|
|
"tx_stn_cpu_1" 4;
|
|
"tx_stn_cpu_2" 4;
|
|
"tx_stn_cpu_3" 4;
|
|
"tx_stn_cpu_4" 4;
|
|
"tx_stn_cpu_5" 4;
|
|
"tx_stn_cpu_6" 4;
|
|
"tx_stn_cpu_7" 4;
|
|
}
|
|
|
|
bucket "gmac_tx_3" {
|
|
size 32;
|
|
"tx_stn_cpu_0" 4;
|
|
"tx_stn_cpu_1" 4;
|
|
"tx_stn_cpu_2" 4;
|
|
"tx_stn_cpu_3" 4;
|
|
"tx_stn_cpu_4" 4;
|
|
"tx_stn_cpu_5" 4;
|
|
"tx_stn_cpu_6" 4;
|
|
"tx_stn_cpu_7" 4;
|
|
}
|
|
|
|
bucket "gmac_rfr_1" {
|
|
size 32;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 4;
|
|
"tx_stn_cpu_3" 4;
|
|
"tx_stn_cpu_4" 4;
|
|
"tx_stn_cpu_5" 4;
|
|
"tx_stn_cpu_6" 4;
|
|
"tx_stn_cpu_7" 4;
|
|
"tx_stn_gmac" 4;
|
|
}
|
|
/*********************************************/
|
|
// xgmac
|
|
bucket "xgs_0_rfr" {
|
|
size 32;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 4;
|
|
"tx_stn_cpu_3" 4;
|
|
"tx_stn_cpu_4" 4;
|
|
"tx_stn_cpu_5" 4;
|
|
"tx_stn_cpu_6" 4;
|
|
"tx_stn_cpu_7" 4;
|
|
"tx_stn_xgs_0" 4;
|
|
}
|
|
|
|
bucket "xgs_0_tx_0" {
|
|
size 32;
|
|
"tx_stn_cpu_0" 4;
|
|
"tx_stn_cpu_1" 4;
|
|
"tx_stn_cpu_2" 4;
|
|
"tx_stn_cpu_3" 4;
|
|
"tx_stn_cpu_4" 4;
|
|
"tx_stn_cpu_5" 4;
|
|
"tx_stn_cpu_6" 4;
|
|
"tx_stn_cpu_7" 4;
|
|
}
|
|
|
|
bucket "xgs_0_tx_1" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_0_tx_2" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_0_tx_3" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_0_tx_4" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
bucket "xgs_0_tx_5" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_0_tx_6" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_0_tx_7" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_0_tx_8" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_0_tx_9" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_0_tx_10" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
|
|
bucket "xgs_0_tx_11" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_0_tx_12" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_0_tx_13" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_0_tx_14" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
|
|
bucket "xgs_1_rfr" {
|
|
size 32;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 4;
|
|
"tx_stn_cpu_3" 4;
|
|
"tx_stn_cpu_4" 4;
|
|
"tx_stn_cpu_5" 4;
|
|
"tx_stn_cpu_6" 4;
|
|
"tx_stn_cpu_7" 4;
|
|
"tx_stn_xgs_1" 4;
|
|
}
|
|
|
|
bucket "xgs_1_tx_0" {
|
|
size 32;
|
|
"tx_stn_cpu_0" 4;
|
|
"tx_stn_cpu_1" 4;
|
|
"tx_stn_cpu_2" 4;
|
|
"tx_stn_cpu_3" 4;
|
|
"tx_stn_cpu_4" 4;
|
|
"tx_stn_cpu_5" 4;
|
|
"tx_stn_cpu_6" 4;
|
|
"tx_stn_cpu_7" 4;
|
|
}
|
|
|
|
|
|
bucket "xgs_1_tx_1" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_1_tx_2" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_1_tx_3" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_1_tx_4" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_1_tx_5" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_1_tx_6" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_1_tx_7" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
|
|
bucket "xgs_1_tx_8" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
|
|
bucket "xgs_1_tx_9" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
|
|
bucket "xgs_1_tx_10" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_1_tx_11" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_1_tx_12" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_1_tx_13" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
bucket "xgs_1_tx_14" {
|
|
size 16;
|
|
"tx_stn_cpu_0" 2;
|
|
"tx_stn_cpu_1" 2;
|
|
"tx_stn_cpu_2" 2;
|
|
"tx_stn_cpu_3" 2;
|
|
"tx_stn_cpu_4" 2;
|
|
"tx_stn_cpu_5" 2;
|
|
"tx_stn_cpu_6" 2;
|
|
"tx_stn_cpu_7" 2;
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
|
|
/*************************************************************/
|
|
// Security Message Station
|
|
|
|
bucket "sec_pipe_0" {
|
|
size 128;
|
|
"tx_stn_cpu_0" 16;
|
|
"tx_stn_cpu_1" 16;
|
|
"tx_stn_cpu_2" 16;
|
|
"tx_stn_cpu_3" 16;
|
|
"tx_stn_cpu_4" 16;
|
|
"tx_stn_cpu_5" 16;
|
|
"tx_stn_cpu_6" 16;
|
|
"tx_stn_cpu_7" 16;
|
|
}
|
|
|
|
bucket "sec_rsa" {
|
|
size 128;
|
|
"tx_stn_cpu_0" 16;
|
|
"tx_stn_cpu_1" 16;
|
|
"tx_stn_cpu_2" 16;
|
|
"tx_stn_cpu_3" 16;
|
|
"tx_stn_cpu_4" 16;
|
|
"tx_stn_cpu_5" 16;
|
|
"tx_stn_cpu_6" 16;
|
|
"tx_stn_cpu_7" 16;
|
|
}
|
|
|