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145 lines
4.1 KiB
C
145 lines
4.1 KiB
C
/*-
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* Copyright (c) 2003-2009 RMI Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of RMI Corporation, nor the names of its contributors,
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RMI_BSD */
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#ifndef __MIPS_EXTS_H__
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#define __MIPS_EXTS_H__
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#define enable_KX(flags) __asm__ __volatile__ ( \
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".set push\n" \
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".set noat\n" \
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".set noreorder\n" \
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"mfc0 %0, $12\n\t" \
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"ori $1, %0, 0x81\n\t" \
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"xori $1, 1\n\t" \
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"mtc0 $1, $12\n" \
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".set pop\n" \
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: "=r"(flags) )
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#define disable_KX(flags) __asm__ __volatile__ ( \
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".set push\n" \
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"mtc0 %0, $12\n" \
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".set pop\n" \
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: : "r"(flags) )
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#define CPU_BLOCKID_IFU 0
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#define CPU_BLOCKID_ICU 1
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#define CPU_BLOCKID_IEU 2
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#define CPU_BLOCKID_LSU 3
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#define CPU_BLOCKID_MMU 4
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#define CPU_BLOCKID_PRF 5
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#define LSU_CERRLOG_REGID 9
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static __inline__ unsigned int read_32bit_phnx_ctrl_reg(int block, int reg)
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{
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unsigned int __res;
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__asm__ __volatile__(
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".set\tpush\n\t"
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".set\tnoreorder\n\t"
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"move $9, %1\n"
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/* "mfcr\t$8, $9\n\t" */
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".word 0x71280018\n"
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"move %0, $8\n"
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".set\tpop"
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: "=r" (__res) : "r"((block<<8)|reg)
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: "$8", "$9"
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);
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return __res;
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}
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static __inline__ void write_32bit_phnx_ctrl_reg(int block, int reg, unsigned int value)
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{
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__asm__ __volatile__(
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".set\tpush\n\t"
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".set\tnoreorder\n\t"
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"move $8, %0\n"
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"move $9, %1\n"
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/* "mtcr\t$8, $9\n\t" */
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".word 0x71280019\n"
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".set\tpop"
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:
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: "r" (value), "r"((block<<8)|reg)
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: "$8", "$9"
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);
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}
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static __inline__ unsigned long long read_64bit_phnx_ctrl_reg(int block, int reg)
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{
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unsigned int high, low;
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__asm__ __volatile__(
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".set\tmips64\n\t"
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"move $9, %2\n"
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/* "mfcr $8, $9\n" */
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".word 0x71280018\n"
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"dsrl32 %0, $8, 0\n\t"
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"dsll32 $8, $8, 0\n\t"
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"dsrl32 %1, $8, 0\n\t"
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".set mips0"
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: "=r" (high), "=r"(low)
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: "r"((block<<8)|reg)
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: "$8", "$9"
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);
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return ( (((unsigned long long)high)<<32) | low);
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}
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static __inline__ void write_64bit_phnx_ctrl_reg(int block, int reg,unsigned long long value)
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{
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__uint32_t low, high;
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high = value >> 32;
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low = value & 0xffffffff;
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__asm__ __volatile__(
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".set push\n"
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".set noreorder\n"
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".set mips4\n\t"
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/* Set up "rs" */
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"move $9, %0\n"
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/* Store 64 bit value in "rt" */
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"dsll32 $10, %1, 0 \n\t"
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"dsll32 $8, %2, 0 \n\t"
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"dsrl32 $8, $8, 0 \n\t"
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"or $10, $8, $8 \n\t"
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".word 0x71280019\n" /* mtcr $8, $9 */
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".set pop\n"
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: /* No outputs */
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: "r"((block<<8)|reg), "r" (high), "r" (low)
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: "$8", "$9", "$10"
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);
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}
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#endif
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