Ruslan Bukin b803d0b790 Add support for HiFive Unleashed -- the board with a multi-core RISC-V SoC ... from SiFive, Inc. The first core on this SoC (hart 0) is a 64-bit microcontroller. o Pick a hart to run boot process using hart lottery. This allows to exclude hart 0 from running the boot process. (BBL releases hart 0 after the main harts, so it never wins the lottery). o Renumber CPUs early on boot. Exclude non-MMU cores. Store the original hart ID in struct pcpu. This allows to find out the correct destination for IPIs and remote sfence calls. Thanks to SiFive, Inc for the board provided. Reviewed by: markj Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D20225		2019-05-12 16:17:05 +00:00
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_align.h
_bus.h
_inttypes.h
_limits.h
_stdint.h
_types.h
asm.h	Permit supervisor to access user VA space for certain functions only.	2018-09-05 11:34:58 +00:00
atomic.h	Implement atomic_swap_{int,long,ptr}(9).	2018-08-07 18:56:51 +00:00
bus_dma_impl.h	Provide a template for busdma code for RISC-V.	2019-05-07 13:41:43 +00:00
bus_dma.h	Provide a template for busdma code for RISC-V.	2019-05-07 13:41:43 +00:00
bus.h
clock.h
counter.h	Back pcpu zone with domain correct pages	2018-07-06 02:06:03 +00:00
cpu.h	RISC-V: Implement get_cyclecount(9).	2018-11-13 18:20:27 +00:00
cpufunc.h	Provide a template for busdma code for RISC-V.	2019-05-07 13:41:43 +00:00
db_machdep.h
dump.h
efi.h
elf.h	Consolidate identical ELF auxargs type defintions.	2018-10-22 22:24:32 +00:00
encoding.h	Add RISC-V instructions encoding.	2018-08-13 16:07:18 +00:00
endian.h
exec.h
float.h
floatingpoint.h
fpe.h	Various fixes for floating point on RISC-V.	2018-09-19 23:45:18 +00:00
frame.h	Replace uses of sbadaddr with stval.	2018-12-19 17:52:09 +00:00
ieeefp.h
in_cksum.h
intr.h
kdb.h	Various fixes for TLB management on RISC-V.	2018-10-15 18:56:54 +00:00
machdep.h
md_var.h
memdev.h
minidump.h
ofw_machdep.h
param.h	Implement transparent 2MB superpage promotion for RISC-V.	2019-02-13 17:19:37 +00:00
pcb.h	Implement per-CPU pmap activation tracking for RISC-V.	2019-02-13 17:50:01 +00:00
pcpu.h	Add support for HiFive Unleashed -- the board with a multi-core RISC-V SoC	2019-05-12 16:17:05 +00:00
pmap.h	Add kernel support for Intel userspace protection keys feature on	2019-02-20 09:51:13 +00:00
pmc_mdep.h
proc.h
procctl.h	amd64 KPTI: add control from procctl(2).	2019-03-16 11:44:33 +00:00
profile.h
psl.h
pte.h	Implement transparent 2MB superpage promotion for RISC-V.	2019-02-13 17:19:37 +00:00
ptrace.h
reg.h
reloc.h
resource.h
riscvreg.h	Optimize RISC-V copyin(9)/copyout(9) routines.	2019-01-21 19:38:53 +00:00
runq.h
sbi.h	Various fixes for TLB management on RISC-V.	2018-10-15 18:56:54 +00:00
setjmp.h	Fix setjmp for RISC-V:	2018-07-23 09:54:28 +00:00
sf_buf.h
sigframe.h	Follow arm[32] and sparc64 KAPI and provide the FreeBSD standard spelling	2019-01-29 20:10:27 +00:00
signal.h
smp.h
stack.h
stdarg.h
sysarch.h
trap.h
ucontext.h
vdso.h
vm.h
vmparam.h	Implement transparent 2MB superpage promotion for RISC-V.	2019-02-13 17:19:37 +00:00