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799e5f277f
New version with improved support for WIDE SCSI using the NCR 53c825. Test for buggy secondary cache implementations. PCI Int to IRQ mapping now specified per slot.
297 lines
8.8 KiB
C
297 lines
8.8 KiB
C
/**************************************************************************
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**
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** $Id: pci_intel.c,v 2.1 94/09/16 08:02:42 wolf Rel $
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**
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** Device driver for INTEL PCI chipsets.
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**
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** 386bsd / FreeBSD
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**
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**-------------------------------------------------------------------------
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**
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** Written for 386bsd and FreeBSD by
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** wolf@dentaro.gun.de Wolfgang Stanglmeier
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** se@mi.Uni-Koeln.de Stefan Esser
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**
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**-------------------------------------------------------------------------
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**
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** Copyright (c) 1994 Stefan Esser. All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without
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** modification, are permitted provided that the following conditions
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** are met:
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** 1. Redistributions of source code must retain the above copyright
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** notice, this list of conditions and the following disclaimer.
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** 2. Redistributions in binary form must reproduce the above copyright
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** notice, this list of conditions and the following disclaimer in the
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** documentation and/or other materials provided with the distribution.
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** 3. The name of the author may not be used to endorse or promote products
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** derived from this software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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**-------------------------------------------------------------------------
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*/
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/*==========================================================
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**
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** Include files
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**
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**==========================================================
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*/
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#include <sys/types.h>
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#include <i386/pci/pci.h>
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#include <i386/pci/pcibios.h>
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#include <i386/pci/pci_device.h>
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static int probe1(pcici_t config_id);
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static int return0(int unit);
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static int intel_attach(pcici_t config_id);
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static int intel_82424zx_attach(pcici_t config_id);
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static int intel_82434lx_attach(pcici_t config_id);
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extern void printf();
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static char confread(pcici_t config_id, int port);
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struct condmsg {
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unsigned char port;
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unsigned char mask;
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unsigned char value;
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char flags;
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char *text;
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};
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#define M_EQ 0 /* mask and return true if equal */
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#define M_NE 1 /* mask and return true if not equal */
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#define TRUE 2 /* don't read config, always true */
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struct pci_driver intel82378_device = {
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probe1,
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intel_attach,
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0x04848086,
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"intel 82378IB pci-isa bridge",
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return0
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};
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struct pci_driver intel82424_device = {
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probe1,
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intel_82424zx_attach,
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0x04838086,
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"intel 82424ZX cache dram controller",
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return0
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};
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struct pci_driver intel82375_device = {
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probe1,
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intel_attach,
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0x04828086,
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"intel 82375EB pci-eisa bridge",
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return0
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};
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struct pci_driver intel82434_device = {
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probe1,
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intel_82434lx_attach,
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0x04a38086,
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"intel 82434LX pci cache memory controller",
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return0
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};
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struct condmsg conf82424zx[] =
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{
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{ 0x00, 0x00, 0x00, TRUE, "\tCPU: " },
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{ 0x50, 0xe0, 0x00, M_EQ, "486DX" },
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{ 0x50, 0xe0, 0x20, M_EQ, "486SX" },
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{ 0x50, 0xe0, 0x40, M_EQ, "486DX2 or 486DX4" },
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{ 0x50, 0xe0, 0x80, M_EQ, "Overdrive (writeback)" },
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{ 0x00, 0x00, 0x00, TRUE, ", bus=" },
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{ 0x50, 0x03, 0x00, M_EQ, "25MHz" },
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{ 0x50, 0x03, 0x01, M_EQ, "33MHz" },
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{ 0x53, 0x01, 0x01, TRUE, ", CPU->Memory posting "},
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{ 0x53, 0x01, 0x00, M_EQ, "OFF" },
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{ 0x53, 0x01, 0x01, M_EQ, "ON" },
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{ 0x56, 0x30, 0x00, M_NE, "\n\tWarning:" },
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{ 0x56, 0x20, 0x00, M_NE, " NO cache parity!" },
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{ 0x56, 0x10, 0x00, M_NE, " NO DRAM parity!" },
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{ 0x55, 0x04, 0x04, M_EQ, "\n\tWarning: refresh OFF! " },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tCache: " },
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{ 0x52, 0x01, 0x00, M_EQ, "None" },
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{ 0x52, 0xc1, 0x01, M_EQ, "64KB" },
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{ 0x52, 0xc1, 0x41, M_EQ, "128KB" },
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{ 0x52, 0xc1, 0x81, M_EQ, "256KB" },
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{ 0x52, 0xc1, 0xc1, M_EQ, "512KB" },
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{ 0x52, 0x03, 0x01, M_EQ, " writethrough" },
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{ 0x52, 0x03, 0x03, M_EQ, " writeback" },
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{ 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" },
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{ 0x52, 0x05, 0x01, M_EQ, "3-1-1-1" },
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{ 0x52, 0x05, 0x05, M_EQ, "2-1-1-1" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tDRAM:" },
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{ 0x55, 0x43, 0x00, M_NE, " page mode" },
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{ 0x55, 0x02, 0x02, M_EQ, " code fetch" },
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{ 0x55, 0x43, 0x43, M_EQ, "," },
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{ 0x55, 0x43, 0x42, M_EQ, " and" },
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{ 0x55, 0x40, 0x40, M_EQ, " read" },
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{ 0x55, 0x03, 0x03, M_EQ, " and" },
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{ 0x55, 0x43, 0x41, M_EQ, " and" },
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{ 0x55, 0x01, 0x01, M_EQ, " write" },
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{ 0x55, 0x43, 0x00, M_NE, "," },
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{ 0x00, 0x00, 0x00, TRUE, " memory clocks=" },
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{ 0x55, 0x20, 0x00, M_EQ, "X-2-2-2" },
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{ 0x55, 0x20, 0x20, M_EQ, "X-1-2-1" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tPCI: CPU->PCI posting " },
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{ 0x53, 0x02, 0x02, M_EQ, "ON" },
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{ 0x53, 0x02, 0x00, M_EQ, "OFF" },
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{ 0x00, 0x00, 0x00, TRUE, ", CPU->PCI burst mode " },
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{ 0x54, 0x02, 0x02, M_EQ, "ON" },
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{ 0x54, 0x02, 0x00, M_EQ, "OFF" },
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{ 0x00, 0x00, 0x00, TRUE, ", PCI->Memory posting " },
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{ 0x54, 0x01, 0x01, M_EQ, "ON" },
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{ 0x54, 0x01, 0x00, M_EQ, "OFF" },
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{ 0x00, 0x00, 0x00, TRUE, "\n" },
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/* end marker */
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{ 0 }
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};
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struct condmsg conf82434lx[] =
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{
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{ 0x00, 0x00, 0x00, TRUE, "\tCPU: " },
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{ 0x50, 0xe0, 0x80, M_EQ, "Pentium" },
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{ 0x50, 0xe0, 0x80, M_NE, "???" },
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{ 0x50, 0x02, 0x00, M_EQ, ", ???MHz" },
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{ 0x50, 0x03, 0x02, M_EQ, ", 60MHz" },
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{ 0x50, 0x03, 0x03, M_EQ, ", 66MHz" },
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{ 0x50, 0x04, 0x00, M_EQ, " (primary cache OFF)" },
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{ 0x53, 0x01, 0x01, TRUE, ", CPU->Memory posting "},
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{ 0x53, 0x01, 0x00, M_EQ, "OFF" },
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{ 0x53, 0x01, 0x01, M_NE, "ON" },
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{ 0x53, 0x04, 0x00, M_NE, ", read around write"},
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{ 0x71, 0xc0, 0x00, M_NE, "\n\tWarning: NO cache parity!" },
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{ 0x57, 0x20, 0x00, M_NE, "\n\tWarning: NO DRAM parity!" },
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{ 0x55, 0x01, 0x01, M_EQ, "\n\tWarning: refresh OFF! " },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tCache: " },
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{ 0x52, 0x01, 0x00, M_EQ, "None" },
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{ 0x52, 0x81, 0x01, M_EQ, "" },
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{ 0x52, 0xc1, 0x81, M_EQ, "256KB" },
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{ 0x52, 0xc1, 0xc1, M_EQ, "512KB" },
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{ 0x52, 0x03, 0x01, M_EQ, " writethrough" },
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{ 0x52, 0x03, 0x03, M_EQ, " writeback" },
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{ 0x52, 0x01, 0x01, M_EQ, ", cache clocks=" },
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{ 0x52, 0x20, 0x00, M_EQ, "3-2-2-2/4-2-2-2" },
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{ 0x52, 0x20, 0x00, M_NE, "3-1-1-1" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tDRAM:" },
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{ 0x57, 0x10, 0x00, M_EQ, " page mode" },
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{ 0x00, 0x00, 0x00, TRUE, " memory clocks=" },
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{ 0x57, 0xc0, 0x00, M_EQ, "X-4-4-4 (70ns)" },
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{ 0x57, 0xc0, 0x40, M_EQ, "X-4-4-4/X-3-3-3 (60ns)" },
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{ 0x57, 0xc0, 0x80, M_EQ, "???" },
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{ 0x57, 0xc0, 0xc0, M_EQ, "X-3-3-3 (50ns)" },
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{ 0x00, 0x00, 0x00, TRUE, "\n\tPCI: CPU->PCI posting " },
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{ 0x53, 0x02, 0x02, M_EQ, "ON" },
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{ 0x53, 0x02, 0x00, M_EQ, "OFF" },
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{ 0x00, 0x00, 0x00, TRUE, ", CPU->PCI burst mode " },
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{ 0x54, 0x02, 0x00, M_NE, "ON" },
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{ 0x54, 0x02, 0x00, M_EQ, "OFF" },
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{ 0x00, 0x00, 0x00, TRUE, ", PCI->Memory posting " },
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{ 0x54, 0x01, 0x00, M_NE, "ON" },
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{ 0x54, 0x01, 0x00, M_EQ, "OFF" },
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{ 0x54, 0x04, 0x00, TRUE, ", PCI clocks=" },
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{ 0x54, 0x04, 0x00, M_EQ, "2-2-2-2" },
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{ 0x54, 0x04, 0x00, M_NE, "2-1-1-1" },
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{ 0x00, 0x00, 0x00, TRUE, "\n" },
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/* end marker */
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{ 0 }
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};
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int return0(int unit)
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{
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return (0);
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}
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int probe1(pcici_t config_id)
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{
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return (1);
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}
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static char confread (pcici_t config_id, int port)
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{
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unsigned long portw = port & ~3;
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unsigned long ports = (port - portw) << 3;
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unsigned long l = pci_conf_read (config_id, portw);
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return (l >> ports);
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}
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static void writeconfig(pcici_t config_id, struct condmsg *tbl)
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{
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while (tbl->text) {
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int cond = 0;
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if (tbl->flags == TRUE) {
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cond = 1;
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} else {
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unsigned char v = (unsigned char) confread(config_id, tbl->port);
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switch (tbl->flags) {
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case M_EQ:
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if ((v & tbl->mask) == tbl->value) cond = 1;
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break;
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case M_NE:
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if ((v & tbl->mask) != tbl->value) cond = 1;
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break;
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}
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}
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if (cond) printf ("%s", tbl->text);
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tbl++;
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}
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}
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int intel_attach(pcici_t config_id)
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{
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printf ("\t[40] %lx [50] %lx [54] %lx\n",
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pci_conf_read (config_id, 0x40),
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pci_conf_read (config_id, 0x50),
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pci_conf_read (config_id, 0x54));
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return(0);
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}
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int intel_82424zx_attach(pcici_t config_id)
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{
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writeconfig (config_id, conf82424zx);
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return (0);
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}
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int intel_82434lx_attach(pcici_t config_id)
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{
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writeconfig (config_id, conf82434lx);
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return (0);
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}
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