John Baldwin 232d0b87e0 Various fixes for floating point on RISC-V. ... - Explicitly load an empty initial state into FP registers when taking the fault on the first FP instruction in a thread. Setting SSTATE.FS to INITIAL is just a marker to let context switch restore code know that it can load FP registers with zeroes instead of memory loads. It does not imply that the hardware will reset all registers to zero on first access. In addition, set the state to CLEAN instead of INITIAL after the first FP instruction. cpu_switch() doesn't do anything for INITIAL and only restores from the pcb if the state is CLEAN. We could perhaps change cpu_switch to call fpe_state_clear if the state was INITIAL and leave SSTATE.FS set to INITIAL instead of CLEAN after the first FP instruction. However, adding this complexity to cpu_switch() doesn't seem worth the supposed gain. - Only save the current FPU registers in fill_fpregs() if the request is made to save the current thread's registers. Previously if a debugger requested FP registers via ptrace() it was getting a copy of the debugger's FP registers rather than the debugee's. - Zero the entire FP register set structure returned for ptrace() if a thread hasn't used FP registers rather than leaking garbage in the fp_fcsr field. - If a debugger writes FP registers via ptrace(), always mark the pcb as having valid FP registers and set SSTATUS.FS_MASK to CLEAN so that the registers will be restored when the debugged thread resumes. - Be more explicit about clearing the SSTATUS.FS field before setting it to CLEAN on the first FP instruction trap. Submitted by: br, markj Approved by: re (rgrimes) Sponsored by: DARPA Differential Revision: https://reviews.freebsd.org/D17141		2018-09-19 23:45:18 +00:00
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conf	Enable VIMAGE support for RISC-V.	2018-09-12 08:13:54 +00:00
include	Various fixes for floating point on RISC-V.	2018-09-19 23:45:18 +00:00
riscv	Various fixes for floating point on RISC-V.	2018-09-19 23:45:18 +00:00