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d2aaaeac19
o Introduce a uart bus space so that we don't have to hack dev/uart to do 8 byte reads. This also handles the shift properly, so reset the shift we want dev/uart doing to 0. In effect, this bus space makes the octeon registers have an interface to dev/uart that looks just like the old ISA bus, but does the necessary 64-bit read/write to the bus. We only support read/write operations. We do all the widths, but likely could get away with only 64-bit and 8-bit given the restricted nature of use of this bus. o use bus_space_map to set the .bsh rather than a direct assignment. o Minor cleanup of uart_cpu_getdev to make it conform more to the other implementations. o Add some coments for future work. # with these changes, we now make it through cninit, but there's still some # problem that's preventing output, as well as another problem that causes # us to call panic just after we return from cninit() in platform_start.
192 lines
4.8 KiB
C
192 lines
4.8 KiB
C
/*-
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* Copyright (c) 2009 M. Warner Losh <imp@FreeBSD.org>
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* Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id$
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*/
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#include "opt_uart.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/cons.h>
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#include <machine/bus.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <mips/octeon1/octeonreg.h>
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#include <mips/octeon1/octeon_pcmap_regs.h>
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bus_space_tag_t uart_bus_space_io;
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bus_space_tag_t uart_bus_space_mem;
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/ktr.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_extern.h>
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#include <machine/bus.h>
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#include <machine/cache.h>
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/*
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* Specailized uart bus space. We present a 1 apart byte oriented
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* bus to the outside world, but internally translate to/from the 8-apart
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* 64-bit word bus that's on the octeon. We only support simple read/write
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* in this space. Everything else is undefined.
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*/
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static uint8_t
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ou_bs_r_1(void *t, bus_space_handle_t handle, bus_size_t offset)
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{
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return (oct_read64(handle + (offset << 3)));
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}
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static uint16_t
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ou_bs_r_2(void *t, bus_space_handle_t handle, bus_size_t offset)
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{
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return (oct_read64(handle + (offset << 3)));
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}
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static uint32_t
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ou_bs_r_4(void *t, bus_space_handle_t handle, bus_size_t offset)
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{
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return (oct_read64(handle + (offset << 3)));
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}
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static uint64_t
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ou_bs_r_8(void *t, bus_space_handle_t handle, bus_size_t offset)
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{
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return (oct_read64(handle + (offset << 3)));
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}
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static void
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ou_bs_w_1(void *t, bus_space_handle_t bsh, bus_size_t offset, uint8_t value)
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{
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oct_write64(bsh + (offset << 3), value);
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}
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static void
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ou_bs_w_2(void *t, bus_space_handle_t bsh, bus_size_t offset, uint16_t value)
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{
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oct_write64(bsh + (offset << 3), value);
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}
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static void
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ou_bs_w_4(void *t, bus_space_handle_t bsh, bus_size_t offset, uint32_t value)
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{
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oct_write64(bsh + (offset << 3), value);
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}
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static void
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ou_bs_w_8(void *t, bus_space_handle_t bsh, bus_size_t offset, uint64_t value)
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{
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oct_write64(bsh + (offset << 3), value);
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}
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static struct bus_space octeon_uart_tag = {
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.bs_map = generic_bs_map,
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.bs_unmap = generic_bs_unmap,
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.bs_subregion = generic_bs_subregion,
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.bs_barrier = generic_bs_barrier,
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.bs_r_1 = ou_bs_r_1,
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.bs_r_2 = ou_bs_r_2,
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.bs_r_4 = ou_bs_r_4,
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.bs_r_8 = ou_bs_r_8,
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.bs_w_1 = ou_bs_w_1,
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.bs_w_2 = ou_bs_w_2,
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.bs_w_4 = ou_bs_w_4,
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.bs_w_8 = ou_bs_w_8,
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};
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extern struct uart_class uart_oct16550_class;
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int
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uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
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{
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return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
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}
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int
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uart_cpu_getdev(int devtype, struct uart_devinfo *di)
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{
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struct uart_class *class = &uart_oct16550_class;
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/*
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* These fields need to be setup corretly for uart_getenv to
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* work in all cases.
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*/
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uart_bus_space_io = NULL; /* No io map for this device */
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uart_bus_space_mem = &octeon_uart_tag;
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di->bas.bst = uart_bus_space_mem;
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/*
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* If env specification for UART exists it takes precedence:
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* hw.uart.console="mm:0xf1012000" or similar
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*/
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if (uart_getenv(devtype, di, class) == 0)
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return (0);
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/*
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* Fallback to UART0 for console.
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*/
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di->ops = uart_getops(class);
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di->bas.chan = 0;
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if (bus_space_map(di->bas.bst, OCTEON_UART0ADR, OCTEON_UART_SIZE,
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0, &di->bas.bsh) != 0)
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return (ENXIO);
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di->bas.regshft = 0;
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di->bas.rclk = 0;
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di->baudrate = 115200;
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di->databits = 8;
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di->stopbits = 1;
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di->parity = UART_PARITY_NONE;
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return (0);
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}
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