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560 lines
14 KiB
C
560 lines
14 KiB
C
/*-
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* Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/interrupt.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_extern.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/pmap.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include "pcib_if.h"
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#include <mips/atheros/ar71xxreg.h>
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#include <mips/atheros/ar71xx_pci_bus_space.h>
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#undef AR71XX_PCI_DEBUG
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#ifdef AR71XX_PCI_DEBUG
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#define dprintf printf
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#else
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#define dprintf(x, arg...)
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#endif
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struct ar71xx_pci_softc {
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device_t sc_dev;
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int sc_busno;
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struct rman sc_mem_rman;
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struct rman sc_irq_rman;
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struct intr_event *sc_eventstab[AR71XX_PCI_NIRQS];
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struct resource *sc_irq;
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void *sc_ih;
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};
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static int ar71xx_pci_setup_intr(device_t, device_t, struct resource *, int,
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driver_filter_t *, driver_intr_t *, void *, void **);
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static int ar71xx_pci_teardown_intr(device_t, device_t, struct resource *,
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void *);
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static int ar71xx_pci_intr(void *);
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static void
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ar71xx_pci_mask_irq(void *source)
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{
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uint32_t reg;
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unsigned int irq = (unsigned int)source;
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reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
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/* flush */
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reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
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ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg & ~(1 << irq));
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}
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static void
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ar71xx_pci_unmask_irq(void *source)
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{
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uint32_t reg;
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unsigned int irq = (unsigned int)source;
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reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
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ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, reg | (1 << irq));
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/* flush */
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reg = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
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}
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/*
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* get bitmask for bytes of interest:
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* 0 - we want this byte, 1 - ignore it. e.g: we read 1 byte
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* from register 7. Bitmask would be: 0111
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*/
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static uint32_t
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ar71xx_get_bytes_to_read(int reg, int bytes)
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{
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uint32_t bytes_to_read = 0;
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if ((bytes % 4) == 0)
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bytes_to_read = 0;
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else if ((bytes % 4) == 1)
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bytes_to_read = (~(1 << (reg % 4))) & 0xf;
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else if ((bytes % 4) == 2)
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bytes_to_read = (~(3 << (reg % 4))) & 0xf;
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else
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panic("%s: wrong combination", __func__);
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return (bytes_to_read);
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}
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static int
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ar71xx_pci_check_bus_error(void)
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{
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uint32_t error, addr, has_errors = 0;
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error = ATH_READ_REG(AR71XX_PCI_ERROR) & 0x3;
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dprintf("%s: PCI error = %02x\n", __func__, error);
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if (error) {
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addr = ATH_READ_REG(AR71XX_PCI_ERROR_ADDR);
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/* Do not report it yet */
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#if 0
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printf("PCI bus error %d at addr 0x%08x\n", error, addr);
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#endif
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ATH_WRITE_REG(AR71XX_PCI_ERROR, error);
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has_errors = 1;
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}
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error = ATH_READ_REG(AR71XX_PCI_AHB_ERROR) & 0x1;
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dprintf("%s: AHB error = %02x\n", __func__, error);
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if (error) {
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addr = ATH_READ_REG(AR71XX_PCI_AHB_ERROR_ADDR);
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/* Do not report it yet */
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#if 0
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printf("AHB bus error %d at addr 0x%08x\n", error, addr);
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#endif
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ATH_WRITE_REG(AR71XX_PCI_AHB_ERROR, error);
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has_errors = 1;
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}
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return (has_errors);
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}
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static uint32_t
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ar71xx_pci_make_addr(int bus, int slot, int func, int reg)
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{
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if (bus == 0) {
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return ((1 << slot) | (func << 8) | (reg & ~3));
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} else {
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return ((bus << 16) | (slot << 11) | (func << 8)
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| (reg & ~3) | 1);
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}
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}
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static int
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ar71xx_pci_conf_setup(int bus, int slot, int func, int reg, int bytes,
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uint32_t cmd)
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{
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uint32_t addr = ar71xx_pci_make_addr(bus, slot, func, (reg & ~3));
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cmd |= (ar71xx_get_bytes_to_read(reg, bytes) << 4);
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ATH_WRITE_REG(AR71XX_PCI_CONF_ADDR, addr);
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ATH_WRITE_REG(AR71XX_PCI_CONF_CMD, cmd);
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dprintf("%s: tag (%x, %x, %x) %d/%d addr=%08x, cmd=%08x\n", __func__,
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bus, slot, func, reg, bytes, addr, cmd);
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return ar71xx_pci_check_bus_error();
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}
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static uint32_t
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ar71xx_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, int bytes)
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{
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uint32_t data;
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uint32_t cmd, shift, mask;
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/* register access is 32-bit aligned */
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shift = (reg & 3) * 8;
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if (shift)
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mask = (1 << shift) - 1;
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else
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mask = 0xffffffff;
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dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
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func, reg, bytes);
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if ((bus == 0) && (slot == 0) && (func == 0)) {
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cmd = PCI_LCONF_CMD_READ | (reg & ~3);
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ATH_WRITE_REG(AR71XX_PCI_LCONF_CMD, cmd);
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data = ATH_READ_REG(AR71XX_PCI_LCONF_READ_DATA);
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} else {
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if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes,
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PCI_CONF_CMD_READ) == 0)
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data = ATH_READ_REG(AR71XX_PCI_CONF_READ_DATA);
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else
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data = -1;
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}
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/* get request bytes from 32-bit word */
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data = (data >> shift) & mask;
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dprintf("%s: read 0x%x\n", __func__, data);
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return (data);
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}
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static void
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ar71xx_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
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u_int reg, uint32_t data, int bytes)
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{
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uint32_t cmd;
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dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot,
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func, reg, bytes);
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data = data << (8*(reg % 4));
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if ((bus == 0) && (slot == 0) && (func == 0)) {
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cmd = PCI_LCONF_CMD_WRITE | (reg & ~3);
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cmd |= ar71xx_get_bytes_to_read(reg, bytes) << 20;
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ATH_WRITE_REG(AR71XX_PCI_LCONF_CMD, cmd);
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ATH_WRITE_REG(AR71XX_PCI_LCONF_WRITE_DATA, data);
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} else {
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if (ar71xx_pci_conf_setup(bus, slot, func, reg, bytes,
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PCI_CONF_CMD_WRITE) == 0)
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ATH_WRITE_REG(AR71XX_PCI_CONF_WRITE_DATA, data);
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}
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}
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static int
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ar71xx_pci_probe(device_t dev)
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{
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return (0);
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}
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static int
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ar71xx_pci_attach(device_t dev)
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{
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int busno = 0;
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int rid = 0;
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uint32_t reset;
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struct ar71xx_pci_softc *sc = device_get_softc(dev);
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sc->sc_mem_rman.rm_type = RMAN_ARRAY;
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sc->sc_mem_rman.rm_descr = "ar71xx PCI memory window";
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if (rman_init(&sc->sc_mem_rman) != 0 ||
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rman_manage_region(&sc->sc_mem_rman, AR71XX_PCI_MEM_BASE,
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AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1) != 0) {
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panic("ar71xx_pci_attach: failed to set up I/O rman");
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}
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sc->sc_irq_rman.rm_type = RMAN_ARRAY;
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sc->sc_irq_rman.rm_descr = "ar71xx PCI IRQs";
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if (rman_init(&sc->sc_irq_rman) != 0 ||
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rman_manage_region(&sc->sc_irq_rman, AR71XX_PCI_IRQ_START,
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AR71XX_PCI_IRQ_END) != 0)
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panic("ar71xx_pci_attach: failed to set up IRQ rman");
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ATH_WRITE_REG(AR71XX_PCI_INTR_STATUS, 0);
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ATH_WRITE_REG(AR71XX_PCI_INTR_MASK, 0);
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/* Hook up our interrupt handler. */
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if ((sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_SHAREABLE | RF_ACTIVE)) == NULL) {
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device_printf(dev, "unable to allocate IRQ resource\n");
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return ENXIO;
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}
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if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
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ar71xx_pci_intr, NULL, sc, &sc->sc_ih))) {
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device_printf(dev,
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"WARNING: unable to register interrupt handler\n");
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return ENXIO;
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}
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/* reset PCI core and PCI bus */
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reset = ATH_READ_REG(AR71XX_RST_RESET);
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reset |= (RST_RESET_PCI_CORE | RST_RESET_PCI_BUS);
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ATH_WRITE_REG(AR71XX_RST_RESET, reset);
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ATH_READ_REG(AR71XX_RST_RESET);
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DELAY(1000);
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reset &= ~(RST_RESET_PCI_CORE | RST_RESET_PCI_BUS);
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ATH_WRITE_REG(AR71XX_RST_RESET, reset);
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ATH_READ_REG(AR71XX_RST_RESET);
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DELAY(1000);
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/* Init PCI windows */
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ATH_WRITE_REG(AR71XX_PCI_WINDOW0, PCI_WINDOW0_ADDR);
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ATH_WRITE_REG(AR71XX_PCI_WINDOW1, PCI_WINDOW1_ADDR);
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ATH_WRITE_REG(AR71XX_PCI_WINDOW2, PCI_WINDOW2_ADDR);
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ATH_WRITE_REG(AR71XX_PCI_WINDOW3, PCI_WINDOW3_ADDR);
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ATH_WRITE_REG(AR71XX_PCI_WINDOW4, PCI_WINDOW4_ADDR);
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ATH_WRITE_REG(AR71XX_PCI_WINDOW5, PCI_WINDOW5_ADDR);
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ATH_WRITE_REG(AR71XX_PCI_WINDOW6, PCI_WINDOW6_ADDR);
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ATH_WRITE_REG(AR71XX_PCI_WINDOW7, PCI_WINDOW7_CONF_ADDR);
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DELAY(1000);
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ar71xx_pci_check_bus_error();
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/* Fixup internal PCI bridge */
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ar71xx_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND,
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PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN
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| PCIM_CMD_SERRESPEN | PCIM_CMD_BACKTOBACK
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| PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN, 2);
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device_add_child(dev, "pci", busno);
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return (bus_generic_attach(dev));
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}
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static int
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ar71xx_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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struct ar71xx_pci_softc *sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_DOMAIN:
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*result = 0;
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return (0);
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case PCIB_IVAR_BUS:
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*result = sc->sc_busno;
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return (0);
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}
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return (ENOENT);
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}
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static int
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ar71xx_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
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{
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struct ar71xx_pci_softc * sc = device_get_softc(dev);
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switch (which) {
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case PCIB_IVAR_BUS:
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sc->sc_busno = result;
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return (0);
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}
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return (ENOENT);
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}
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static struct resource *
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ar71xx_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags)
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{
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struct ar71xx_pci_softc *sc = device_get_softc(bus);
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struct resource *rv;
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struct rman *rm;
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switch (type) {
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case SYS_RES_IRQ:
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rm = &sc->sc_irq_rman;
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break;
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case SYS_RES_MEMORY:
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rm = &sc->sc_mem_rman;
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break;
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default:
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return (NULL);
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}
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rv = rman_reserve_resource(rm, start, end, count, flags, child);
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if (rv == NULL)
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return (NULL);
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rman_set_rid(rv, *rid);
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if (flags & RF_ACTIVE) {
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if (bus_activate_resource(child, type, *rid, rv)) {
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rman_release_resource(rv);
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return (NULL);
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}
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}
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return (rv);
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}
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static int
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ar71xx_pci_activate_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus),
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child, type, rid, r));
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if (!res) {
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switch(type) {
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case SYS_RES_MEMORY:
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case SYS_RES_IOPORT:
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rman_set_bustag(r, ar71xx_bus_space_pcimem);
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break;
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}
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}
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return (res);
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}
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static int
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ar71xx_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
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int flags, driver_filter_t *filt, driver_intr_t *handler,
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void *arg, void **cookiep)
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{
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struct ar71xx_pci_softc *sc = device_get_softc(bus);
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struct intr_event *event;
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int irq, error;
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irq = rman_get_start(ires);
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if (irq > AR71XX_PCI_IRQ_END)
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panic("%s: bad irq %d", __func__, irq);
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event = sc->sc_eventstab[irq];
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if (event == NULL) {
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error = intr_event_create(&event, (void *)irq, 0, irq,
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ar71xx_pci_mask_irq, ar71xx_pci_unmask_irq, NULL, NULL,
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"ar71xx_pci intr%d:", irq);
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sc->sc_eventstab[irq] = event;
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}
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intr_event_add_handler(event, device_get_nameunit(child), filt,
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handler, arg, intr_priority(flags), flags, cookiep);
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ar71xx_pci_unmask_irq((void*)irq);
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return (0);
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}
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static int
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ar71xx_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
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void *cookie)
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{
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struct ar71xx_pci_softc *sc = device_get_softc(dev);
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int irq, result;
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irq = rman_get_start(ires);
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if (irq > AR71XX_PCI_IRQ_END)
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panic("%s: bad irq %d", __func__, irq);
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if (sc->sc_eventstab[irq] == NULL)
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panic("Trying to teardown unoccupied IRQ");
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ar71xx_pci_mask_irq((void*)irq);
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result = intr_event_remove_handler(cookie);
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if (!result)
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sc->sc_eventstab[irq] = NULL;
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return (result);
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}
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static int
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ar71xx_pci_intr(void *arg)
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{
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struct ar71xx_pci_softc *sc = arg;
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struct intr_event *event;
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uint32_t reg, irq, mask;
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reg = ATH_READ_REG(AR71XX_PCI_INTR_STATUS);
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mask = ATH_READ_REG(AR71XX_PCI_INTR_MASK);
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/*
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* Handle only unmasked interrupts
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*/
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reg &= mask;
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for (irq = AR71XX_PCI_IRQ_START; irq <= AR71XX_PCI_IRQ_END; irq++) {
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if (reg & (1 << irq)) {
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event = sc->sc_eventstab[irq];
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if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
|
|
/* Ignore timer interrupts */
|
|
if (irq != 0)
|
|
printf("Stray IRQ %d\n", irq);
|
|
continue;
|
|
}
|
|
|
|
/* TODO: frame instead of NULL? */
|
|
intr_event_handle(event, NULL);
|
|
}
|
|
}
|
|
|
|
return (FILTER_HANDLED);
|
|
}
|
|
|
|
static int
|
|
ar71xx_pci_maxslots(device_t dev)
|
|
{
|
|
|
|
return (PCI_SLOTMAX);
|
|
}
|
|
|
|
static int
|
|
ar71xx_pci_route_interrupt(device_t pcib, device_t device, int pin)
|
|
{
|
|
if (pci_get_slot(device) < AR71XX_PCI_BASE_SLOT)
|
|
panic("%s: PCI slot %d is less then AR71XX_PCI_BASE_SLOT",
|
|
__func__, pci_get_slot(device));
|
|
|
|
return (pci_get_slot(device) - AR71XX_PCI_BASE_SLOT);
|
|
}
|
|
|
|
static device_method_t ar71xx_pci_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, ar71xx_pci_probe),
|
|
DEVMETHOD(device_attach, ar71xx_pci_attach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_print_child, bus_generic_print_child),
|
|
DEVMETHOD(bus_read_ivar, ar71xx_pci_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, ar71xx_pci_write_ivar),
|
|
DEVMETHOD(bus_alloc_resource, ar71xx_pci_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
|
DEVMETHOD(bus_activate_resource, ar71xx_pci_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, ar71xx_pci_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, ar71xx_pci_teardown_intr),
|
|
|
|
/* pcib interface */
|
|
DEVMETHOD(pcib_maxslots, ar71xx_pci_maxslots),
|
|
DEVMETHOD(pcib_read_config, ar71xx_pci_read_config),
|
|
DEVMETHOD(pcib_write_config, ar71xx_pci_write_config),
|
|
DEVMETHOD(pcib_route_interrupt, ar71xx_pci_route_interrupt),
|
|
|
|
{0, 0}
|
|
};
|
|
|
|
static driver_t ar71xx_pci_driver = {
|
|
"pcib",
|
|
ar71xx_pci_methods,
|
|
sizeof(struct ar71xx_pci_softc),
|
|
};
|
|
|
|
static devclass_t ar71xx_pci_devclass;
|
|
|
|
DRIVER_MODULE(ar71xx_pci, nexus, ar71xx_pci_driver, ar71xx_pci_devclass, 0, 0);
|