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2f68261c81
so credit its authors with contributions to this file. Remove prototype copyright notice, although one might be warranted if someone wanted to claim it badly enough. Noticed by: Simon Burge.
263 lines
9.8 KiB
C
263 lines
9.8 KiB
C
/* $NetBSD: cache.c,v 1.33 2005/12/24 23:24:01 perry Exp $ */
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/*-
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* Copyright 2001, 2002 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe and Simon Burge for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright 2000, 2001
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* Broadcom Corporation. All rights reserved.
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*
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* This software is furnished under license and may be used and copied only
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* in accordance with the following terms and conditions. Subject to these
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* conditions, you may download, copy, install, use, modify and distribute
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* modified or unmodified copies of this software in source and/or binary
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* form. No title or ownership is transferred hereby.
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*
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* 1) Any source code used, modified or distributed must reproduce and
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* retain this copyright notice and list of conditions as they appear in
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* the source file.
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*
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* 2) No right is granted to use any trade name, trademark, or logo of
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* Broadcom Corporation. The "Broadcom Corporation" name may not be
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* used to endorse or promote products derived from this software
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* without the prior written permission of Broadcom Corporation.
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*
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* 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR
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* NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE
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* FOR ANY DAMAGES WHATSOEVER, AND IN PARTICULAR, BROADCOM SHALL NOT BE
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* LIABLE FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE), EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <machine/cpuinfo.h>
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#include <machine/cache.h>
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struct mips_cache_ops mips_cache_ops;
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void
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mips_config_cache(struct mips_cpuinfo * cpuinfo)
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{
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switch (cpuinfo->l1.ic_linesize) {
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case 16:
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mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_16;
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mips_cache_ops.mco_icache_sync_range =
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mipsNN_icache_sync_range_16;
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mips_cache_ops.mco_icache_sync_range_index =
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mipsNN_icache_sync_range_index_16;
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break;
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case 32:
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mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_32;
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mips_cache_ops.mco_icache_sync_range =
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mipsNN_icache_sync_range_32;
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mips_cache_ops.mco_icache_sync_range_index =
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mipsNN_icache_sync_range_index_32;
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break;
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#ifdef TARGET_OCTEON
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case 128:
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mips_cache_ops.mco_icache_sync_all = mipsNN_icache_sync_all_128;
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mips_cache_ops.mco_icache_sync_range =
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mipsNN_icache_sync_range_128;
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mips_cache_ops.mco_icache_sync_range_index =
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mipsNN_icache_sync_range_index_128;
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break;
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#endif
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#ifdef MIPS_DISABLE_L1_CACHE
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case 0:
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mips_cache_ops.mco_icache_sync_all = cache_noop;
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mips_cache_ops.mco_icache_sync_range =
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(void (*)(vaddr_t, vsize_t))cache_noop;
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mips_cache_ops.mco_icache_sync_range_index =
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(void (*)(vaddr_t, vsize_t))cache_noop;
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break;
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#endif
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default:
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panic("no Icache ops for %d byte lines",
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cpuinfo->l1.ic_linesize);
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}
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switch (cpuinfo->l1.dc_linesize) {
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case 16:
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mips_cache_ops.mco_pdcache_wbinv_all =
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mips_cache_ops.mco_intern_pdcache_wbinv_all =
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mipsNN_pdcache_wbinv_all_16;
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mips_cache_ops.mco_pdcache_wbinv_range =
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mipsNN_pdcache_wbinv_range_16;
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mips_cache_ops.mco_pdcache_wbinv_range_index =
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mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
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mipsNN_pdcache_wbinv_range_index_16;
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mips_cache_ops.mco_pdcache_inv_range =
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mipsNN_pdcache_inv_range_16;
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mips_cache_ops.mco_pdcache_wb_range =
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mips_cache_ops.mco_intern_pdcache_wb_range =
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mipsNN_pdcache_wb_range_16;
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break;
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case 32:
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mips_cache_ops.mco_pdcache_wbinv_all =
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mips_cache_ops.mco_intern_pdcache_wbinv_all =
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mipsNN_pdcache_wbinv_all_32;
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mips_cache_ops.mco_pdcache_wbinv_range =
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mipsNN_pdcache_wbinv_range_32;
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mips_cache_ops.mco_pdcache_wbinv_range_index =
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mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
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mipsNN_pdcache_wbinv_range_index_32;
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mips_cache_ops.mco_pdcache_inv_range =
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mipsNN_pdcache_inv_range_32;
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mips_cache_ops.mco_pdcache_wb_range =
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mips_cache_ops.mco_intern_pdcache_wb_range =
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mipsNN_pdcache_wb_range_32;
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break;
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#ifdef TARGET_OCTEON
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case 128:
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mips_cache_ops.mco_pdcache_wbinv_all =
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mips_cache_ops.mco_intern_pdcache_wbinv_all =
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mipsNN_pdcache_wbinv_all_128;
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mips_cache_ops.mco_pdcache_wbinv_range =
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mipsNN_pdcache_wbinv_range_128;
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mips_cache_ops.mco_pdcache_wbinv_range_index =
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mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
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mipsNN_pdcache_wbinv_range_index_128;
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mips_cache_ops.mco_pdcache_inv_range =
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mipsNN_pdcache_inv_range_128;
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mips_cache_ops.mco_pdcache_wb_range =
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mips_cache_ops.mco_intern_pdcache_wb_range =
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mipsNN_pdcache_wb_range_128;
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break;
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#endif
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#ifdef MIPS_DISABLE_L1_CACHE
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case 0:
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mips_cache_ops.mco_pdcache_wbinv_all = cache_noop;
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mips_cache_ops.mco_intern_pdcache_wbinv_all = cache_noop;
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mips_cache_ops.mco_pdcache_wbinv_range =
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(void (*)(vaddr_t, vsize_t))cache_noop;
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mips_cache_ops.mco_pdcache_wbinv_range_index =
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(void (*)(vaddr_t, vsize_t))cache_noop;
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mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
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(void (*)(vaddr_t, vsize_t))cache_noop;
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mips_cache_ops.mco_pdcache_inv_range =
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(void (*)(vaddr_t, vsize_t))cache_noop;
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mips_cache_ops.mco_pdcache_wb_range =
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(void (*)(vaddr_t, vsize_t))cache_noop;
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mips_cache_ops.mco_intern_pdcache_wb_range =
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(void (*)(vaddr_t, vsize_t))cache_noop;
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break;
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#endif
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default:
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panic("no Dcache ops for %d byte lines",
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cpuinfo->l1.dc_linesize);
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}
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mipsNN_cache_init(cpuinfo);
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#if 0
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if (mips_cpu_flags &
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(CPU_MIPS_D_CACHE_COHERENT | CPU_MIPS_I_D_CACHE_COHERENT)) {
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#ifdef CACHE_DEBUG
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printf(" Dcache is coherent\n");
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#endif
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mips_cache_ops.mco_pdcache_wbinv_all = cache_noop;
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mips_cache_ops.mco_pdcache_wbinv_range =
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(void (*)(vaddr_t, vsize_t))cache_noop;
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mips_cache_ops.mco_pdcache_wbinv_range_index =
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(void (*)(vaddr_t, vsize_t))cache_noop;
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mips_cache_ops.mco_pdcache_inv_range =
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(void (*)(vaddr_t, vsize_t))cache_noop;
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mips_cache_ops.mco_pdcache_wb_range =
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(void (*)(vaddr_t, vsize_t))cache_noop;
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}
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if (mips_cpu_flags & CPU_MIPS_I_D_CACHE_COHERENT) {
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#ifdef CACHE_DEBUG
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printf(" Icache is coherent against Dcache\n");
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#endif
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mips_cache_ops.mco_intern_pdcache_wbinv_all =
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cache_noop;
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mips_cache_ops.mco_intern_pdcache_wbinv_range_index =
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(void (*)(vaddr_t, vsize_t))cache_noop;
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mips_cache_ops.mco_intern_pdcache_wb_range =
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(void (*)(vaddr_t, vsize_t))cache_noop;
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}
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#endif
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/* Check that all cache ops are set up. */
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if (mips_picache_size || 1) { /* XXX- must have primary Icache */
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if (!mips_cache_ops.mco_icache_sync_all)
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panic("no icache_sync_all cache op");
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if (!mips_cache_ops.mco_icache_sync_range)
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panic("no icache_sync_range cache op");
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if (!mips_cache_ops.mco_icache_sync_range_index)
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panic("no icache_sync_range_index cache op");
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}
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if (mips_pdcache_size || 1) { /* XXX- must have primary Icache */
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if (!mips_cache_ops.mco_pdcache_wbinv_all)
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panic("no pdcache_wbinv_all");
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if (!mips_cache_ops.mco_pdcache_wbinv_range)
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panic("no pdcache_wbinv_range");
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if (!mips_cache_ops.mco_pdcache_wbinv_range_index)
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panic("no pdcache_wbinv_range_index");
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if (!mips_cache_ops.mco_pdcache_inv_range)
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panic("no pdcache_inv_range");
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if (!mips_cache_ops.mco_pdcache_wb_range)
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panic("no pdcache_wb_range");
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}
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/* XXXMIPS: No secondary cache handlers yet */
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#ifdef notyet
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if (mips_sdcache_size) {
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if (!mips_cache_ops.mco_sdcache_wbinv_all)
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panic("no sdcache_wbinv_all");
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if (!mips_cache_ops.mco_sdcache_wbinv_range)
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panic("no sdcache_wbinv_range");
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if (!mips_cache_ops.mco_sdcache_wbinv_range_index)
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panic("no sdcache_wbinv_range_index");
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if (!mips_cache_ops.mco_sdcache_inv_range)
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panic("no sdcache_inv_range");
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if (!mips_cache_ops.mco_sdcache_wb_range)
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panic("no sdcache_wb_range");
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}
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#endif
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}
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