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45d426a34e
mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
340 lines
8.1 KiB
C
340 lines
8.1 KiB
C
/* $OpenBSD: db_machdep.c,v 1.2 1998/09/15 10:50:13 pefo Exp $ */
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/*-
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* Copyright (c) 1998 Per Fogelstrom, Opsycon AB
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed under OpenBSD by
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* Per Fogelstrom, Opsycon AB, Sweden.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* JNPR: db_interface.c,v 1.6.2.1 2007/08/29 12:24:49 girish
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/cons.h>
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#include <sys/lock.h>
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#include <vm/vm.h>
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#include <vm/vm_object.h>
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#include <vm/vm_page.h>
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#include <vm/pmap.h>
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#include <vm/vm_map.h>
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#include <sys/user.h>
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#include <sys/proc.h>
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#include <sys/reboot.h>
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#include <machine/cache.h>
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#include <machine/db_machdep.h>
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#include <machine/mips_opcode.h>
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#include <machine/vmparam.h>
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#include <machine/md_var.h>
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#define NO_REG_DEFS 1 /* Prevent asm.h from including regdef.h */
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#include <machine/asm.h>
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#include <machine/setjmp.h>
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#include <ddb/ddb.h>
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#include <ddb/db_sym.h>
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#include <ddb/db_access.h>
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#include <ddb/db_output.h>
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#include <ddb/db_variables.h>
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#include <sys/kdb.h>
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static db_varfcn_t db_frame;
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#define DB_OFFSET(x) (db_expr_t *)offsetof(struct trapframe, x)
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struct db_variable db_regs[] = {
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{ "at", DB_OFFSET(ast), db_frame },
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{ "v0", DB_OFFSET(v0), db_frame },
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{ "v1", DB_OFFSET(v1), db_frame },
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{ "a0", DB_OFFSET(a0), db_frame },
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{ "a1", DB_OFFSET(a1), db_frame },
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{ "a2", DB_OFFSET(a2), db_frame },
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{ "a3", DB_OFFSET(a3), db_frame },
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{ "t0", DB_OFFSET(t0), db_frame },
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{ "t1", DB_OFFSET(t1), db_frame },
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{ "t2", DB_OFFSET(t2), db_frame },
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{ "t3", DB_OFFSET(t3), db_frame },
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{ "t4", DB_OFFSET(t4), db_frame },
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{ "t5", DB_OFFSET(t5), db_frame },
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{ "t6", DB_OFFSET(t6), db_frame },
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{ "t7", DB_OFFSET(t7), db_frame },
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{ "s0", DB_OFFSET(s0), db_frame },
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{ "s1", DB_OFFSET(s1), db_frame },
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{ "s2", DB_OFFSET(s2), db_frame },
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{ "s3", DB_OFFSET(s3), db_frame },
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{ "s4", DB_OFFSET(s4), db_frame },
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{ "s5", DB_OFFSET(s5), db_frame },
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{ "s6", DB_OFFSET(s6), db_frame },
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{ "s7", DB_OFFSET(s7), db_frame },
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{ "t8", DB_OFFSET(t8), db_frame },
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{ "t9", DB_OFFSET(t9), db_frame },
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{ "k0", DB_OFFSET(k0), db_frame },
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{ "k1", DB_OFFSET(k1), db_frame },
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{ "gp", DB_OFFSET(gp), db_frame },
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{ "sp", DB_OFFSET(sp), db_frame },
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{ "s8", DB_OFFSET(s8), db_frame },
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{ "ra", DB_OFFSET(ra), db_frame },
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{ "sr", DB_OFFSET(sr), db_frame },
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{ "lo", DB_OFFSET(mullo), db_frame },
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{ "hi", DB_OFFSET(mulhi), db_frame },
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{ "bad", DB_OFFSET(badvaddr), db_frame },
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{ "cs", DB_OFFSET(cause), db_frame },
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{ "pc", DB_OFFSET(pc), db_frame },
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};
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struct db_variable *db_eregs = db_regs + sizeof(db_regs)/sizeof(db_regs[0]);
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int (*do_db_log_stack_trace_cmd)(char *);
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static int
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db_frame(struct db_variable *vp, db_expr_t *valuep, int op)
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{
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int *reg;
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if (kdb_frame == NULL)
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return (0);
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reg = (int *)((uintptr_t)kdb_frame + (db_expr_t)vp->valuep);
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if (op == DB_VAR_GET)
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*valuep = *reg;
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else
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*reg = *valuep;
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return (1);
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}
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int
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db_read_bytes(vm_offset_t addr, size_t size, char *data)
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{
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jmp_buf jb;
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void *prev_jb;
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int ret;
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prev_jb = kdb_jmpbuf(jb);
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ret = setjmp(jb);
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if (ret == 0) {
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/*
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* 'addr' could be a memory-mapped I/O address. Try to
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* do atomic load/store in unit of size requested.
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*/
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if ((size == 2 || size == 4 || size == 8) &&
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((addr & (size -1)) == 0) &&
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(((vm_offset_t)data & (size -1)) == 0)) {
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switch (size) {
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case 2:
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*(uint16_t *)data = *(uint16_t *)addr;
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break;
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case 4:
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*(uint32_t *)data = *(uint32_t *)addr;
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break;
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case 8:
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atomic_load_64((volatile u_int64_t *)addr,
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(u_int64_t *)data);
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break;
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}
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} else {
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char *src;
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src = (char *)addr;
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while (size-- > 0)
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*data++ = *src++;
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}
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}
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(void)kdb_jmpbuf(prev_jb);
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return (ret);
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}
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int
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db_write_bytes(vm_offset_t addr, size_t size, char *data)
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{
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int ret;
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jmp_buf jb;
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void *prev_jb;
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prev_jb = kdb_jmpbuf(jb);
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ret = setjmp(jb);
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if (ret == 0) {
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/*
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* 'addr' could be a memory-mapped I/O address. Try to
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* do atomic load/store in unit of size requested.
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*/
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if ((size == 2 || size == 4 || size == 8) &&
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((addr & (size -1)) == 0) &&
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(((vm_offset_t)data & (size -1)) == 0)) {
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switch (size) {
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case 2:
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*(uint16_t *)addr = *(uint16_t *)data;
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break;
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case 4:
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*(uint32_t *)addr = *(uint32_t *)data;
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break;
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case 8:
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atomic_store_64((volatile u_int64_t *)addr,
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(u_int64_t *)data);
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break;
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}
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} else {
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char *dst;
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size_t len = size;
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dst = (char *)addr;
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while (len-- > 0)
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*dst++ = *data++;
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}
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mips_icache_sync_range((db_addr_t) addr, size);
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mips_dcache_wbinv_range((db_addr_t) addr, size);
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}
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(void)kdb_jmpbuf(prev_jb);
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return (ret);
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}
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/*
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* To do a single step ddb needs to know the next address
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* that we will get to. It means that we need to find out
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* both the address for a branch taken and for not taken, NOT! :-)
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* MipsEmulateBranch will do the job to find out _exactly_ which
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* address we will end up at so the 'dual bp' method is not
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* requiered.
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*/
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db_addr_t
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next_instr_address(db_addr_t pc, boolean_t bd)
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{
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db_addr_t next;
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next = (db_addr_t)MipsEmulateBranch(kdb_frame, pc, 0, 0);
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return (next);
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}
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/*
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* Decode instruction and figure out type.
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*/
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int
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db_inst_type(int ins)
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{
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InstFmt inst;
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int ityp = 0;
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inst.word = ins;
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switch ((int)inst.JType.op) {
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case OP_SPECIAL:
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switch ((int)inst.RType.func) {
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case OP_JR:
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ityp = IT_BRANCH;
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break;
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case OP_JALR:
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case OP_SYSCALL:
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ityp = IT_CALL;
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break;
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}
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break;
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case OP_BCOND:
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switch ((int)inst.IType.rt) {
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case OP_BLTZ:
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case OP_BLTZL:
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case OP_BGEZ:
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case OP_BGEZL:
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ityp = IT_BRANCH;
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break;
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case OP_BLTZAL:
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case OP_BLTZALL:
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case OP_BGEZAL:
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case OP_BGEZALL:
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ityp = IT_CALL;
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break;
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}
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break;
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case OP_JAL:
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ityp = IT_CALL;
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break;
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case OP_J:
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case OP_BEQ:
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case OP_BEQL:
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case OP_BNE:
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case OP_BNEL:
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case OP_BLEZ:
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case OP_BLEZL:
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case OP_BGTZ:
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case OP_BGTZL:
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ityp = IT_BRANCH;
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break;
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case OP_COP1:
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switch (inst.RType.rs) {
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case OP_BCx:
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case OP_BCy:
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ityp = IT_BRANCH;
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break;
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}
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break;
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case OP_LB:
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case OP_LH:
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case OP_LW:
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case OP_LD:
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case OP_LBU:
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case OP_LHU:
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case OP_LWU:
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case OP_LWC1:
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ityp = IT_LOAD;
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break;
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case OP_SB:
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case OP_SH:
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case OP_SW:
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case OP_SD:
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case OP_SWC1:
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ityp = IT_STORE;
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break;
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}
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return (ityp);
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}
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/*
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* Return the next pc if the given branch is taken.
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* MachEmulateBranch() runs analysis for branch delay slot.
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*/
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db_addr_t
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branch_taken(int inst, db_addr_t pc)
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{
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db_addr_t ra;
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register_t fpucsr;
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/* TBD: when is fsr set */
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fpucsr = (curthread) ? curthread->td_pcb->pcb_regs.fsr : 0;
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ra = (db_addr_t)MipsEmulateBranch(kdb_frame, pc, fpucsr, 0);
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return (ra);
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}
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