Ruslan Bukin 75cf8837a9 Provide a template for busdma code for RISC-V. ... RISC-V ISA specifies no cache management instructions so leave cache operations in cpufunc.h as no-op for now. Note some new hardware comes with their own memory-mapped cache management controller. Tested on HiFive Unleashed board with cgem(4). Reviewed by: markj Obtained from: arm64 Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D20126		2019-05-07 13:41:43 +00:00
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conf	Configure hz=100 in the QEMU target.	2019-01-03 16:11:21 +00:00
include	Provide a template for busdma code for RISC-V.	2019-05-07 13:41:43 +00:00
riscv	Provide a template for busdma code for RISC-V.	2019-05-07 13:41:43 +00:00