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31e30d75d5
Unmasked exceptions (which can be fixed up using fpset*() before they trap) are very rare, especially on amd64 since SSE exceptions trap synchronously, but I want to merge the faster amd64 implementations of fpset*() back to i386 without introducing the bug on i386. The i386 implementation has always avoided the trap automatically by changing things using load/store of the FP environment, but this is very slow. Most changes only affect the control word, so they can usually be done much more efficiently, and amd64 has always done this, but loading the control word can trap. This version use the fast method only in the usual case where it will not trap. This only costs a couple of integer instructions (including one branch which I haven't optimized carefully yet) in the usual case, but bloats the inlines a lot. The inlines were already a bit too large to handle both the FPU and SSE.
304 lines
8.6 KiB
C
304 lines
8.6 KiB
C
/*-
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* Copyright (c) 2003 Peter Wemm.
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* Copyright (c) 1990 Andrew Moore, Talke Studio
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#) ieeefp.h 1.0 (Berkeley) 9/23/93
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* $FreeBSD$
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*/
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#ifndef _MACHINE_IEEEFP_H_
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#define _MACHINE_IEEEFP_H_
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/*
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* IEEE floating point type, constant and function definitions.
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* XXX: {FP,SSE}*FLD and {FP,SSE}*OFF are undocumented pollution.
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*/
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#ifndef _SYS_CDEFS_H_
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#error this file needs sys/cdefs.h as a prerequisite
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#endif
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/*
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* Rounding modes.
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*/
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typedef enum {
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FP_RN=0, /* round to nearest */
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FP_RM, /* round down towards minus infinity */
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FP_RP, /* round up towards plus infinity */
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FP_RZ /* truncate */
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} fp_rnd_t;
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/*
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* Precision (i.e., rounding precision) modes.
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*/
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typedef enum {
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FP_PS=0, /* 24 bit (single-precision) */
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FP_PRS, /* reserved */
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FP_PD, /* 53 bit (double-precision) */
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FP_PE /* 64 bit (extended-precision) */
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} fp_prec_t;
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#define fp_except_t int
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/*
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* Exception bit masks.
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*/
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#define FP_X_INV 0x01 /* invalid operation */
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#define FP_X_DNML 0x02 /* denormal */
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#define FP_X_DZ 0x04 /* zero divide */
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#define FP_X_OFL 0x08 /* overflow */
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#define FP_X_UFL 0x10 /* underflow */
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#define FP_X_IMP 0x20 /* (im)precision */
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#define FP_X_STK 0x40 /* stack fault */
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/*
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* FPU control word bit-field masks.
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*/
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#define FP_MSKS_FLD 0x3f /* exception masks field */
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#define FP_PRC_FLD 0x300 /* precision control field */
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#define FP_RND_FLD 0xc00 /* rounding control field */
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/*
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* FPU status word bit-field masks.
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*/
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#define FP_STKY_FLD 0x3f /* sticky flags field */
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/*
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* SSE mxcsr register bit-field masks.
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*/
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#define SSE_STKY_FLD 0x3f /* exception flags */
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#define SSE_DAZ_FLD 0x40 /* Denormals are zero */
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#define SSE_MSKS_FLD 0x1f80 /* exception masks field */
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#define SSE_RND_FLD 0x6000 /* rounding control */
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#define SSE_FZ_FLD 0x8000 /* flush to zero on underflow */
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/*
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* FPU control word bit-field offsets (shift counts).
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*/
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#define FP_MSKS_OFF 0 /* exception masks offset */
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#define FP_PRC_OFF 8 /* precision control offset */
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#define FP_RND_OFF 10 /* rounding control offset */
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/*
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* FPU status word bit-field offsets (shift counts).
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*/
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#define FP_STKY_OFF 0 /* sticky flags offset */
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/*
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* SSE mxcsr register bit-field offsets (shift counts).
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*/
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#define SSE_STKY_OFF 0 /* exception flags offset */
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#define SSE_DAZ_OFF 6 /* DAZ exception mask offset */
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#define SSE_MSKS_OFF 7 /* other exception masks offset */
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#define SSE_RND_OFF 13 /* rounding control offset */
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#define SSE_FZ_OFF 15 /* flush to zero offset */
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#ifdef __GNUCLIKE_ASM
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#define __fldcw(addr) __asm __volatile("fldcw %0" : : "m" (*(addr)))
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#define __fldenv(addr) __asm __volatile("fldenv %0" : : "m" (*(addr)))
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#define __fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
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#define __fnstenv(addr) __asm __volatile("fnstenv %0" : "=m" (*(addr)))
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#define __fnstsw(addr) __asm __volatile("fnstsw %0" : "=m" (*(addr)))
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#define __ldmxcsr(addr) __asm __volatile("ldmxcsr %0" : : "m" (*(addr)))
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#define __stmxcsr(addr) __asm __volatile("stmxcsr %0" : "=m" (*(addr)))
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/*
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* Load the control word. Be careful not to trap if there is a currently
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* unmasked exception (ones that will become freshly unmasked are not a
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* problem). This case must be handled by a save/restore of the
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* environment or even of the full x87 state. Accessing the environment
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* is very inefficient, so only do it when necessary.
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*/
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static __inline void
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__fnldcw(unsigned short _cw, unsigned short _newcw)
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{
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struct {
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unsigned _cw;
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unsigned _other[6];
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} _env;
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unsigned short _sw;
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if ((_cw & FP_MSKS_FLD) != FP_MSKS_FLD) {
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__fnstsw(&_sw);
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if (((_sw & ~_cw) & FP_STKY_FLD) != 0) {
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__fnstenv(&_env);
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_env._cw = _newcw;
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__fldenv(&_env);
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return;
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}
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}
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__fldcw(&_newcw);
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}
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/*
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* General notes about conflicting SSE vs FP status bits.
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* This code assumes that software will not fiddle with the control
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* bits of the SSE and x87 in such a way to get them out of sync and
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* still expect this to work. Break this at your peril.
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* Because I based this on the i386 port, the x87 state is used for
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* the fpget*() functions, and is shadowed into the SSE state for
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* the fpset*() functions. For dual source fpget*() functions, I
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* merge the two together. I think.
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*/
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static __inline fp_rnd_t
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__fpgetround(void)
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{
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unsigned short _cw;
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__fnstcw(&_cw);
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return ((fp_rnd_t)((_cw & FP_RND_FLD) >> FP_RND_OFF));
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}
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static __inline fp_rnd_t
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__fpsetround(fp_rnd_t _m)
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{
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fp_rnd_t _p;
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unsigned _mxcsr;
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unsigned short _cw, _newcw;
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__fnstcw(&_cw);
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_p = (fp_rnd_t)((_cw & FP_RND_FLD) >> FP_RND_OFF);
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_newcw = _cw & ~FP_RND_FLD;
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_newcw |= (_m << FP_RND_OFF) & FP_RND_FLD;
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__fnldcw(_cw, _newcw);
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__stmxcsr(&_mxcsr);
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_mxcsr &= ~SSE_RND_FLD;
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_mxcsr |= (_m << SSE_RND_OFF) & SSE_RND_FLD;
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__ldmxcsr(&_mxcsr);
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return (_p);
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}
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/*
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* Get or set the rounding precision for x87 arithmetic operations.
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* There is no equivalent SSE mode or control.
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*/
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static __inline fp_prec_t
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__fpgetprec(void)
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{
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unsigned short _cw;
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__fnstcw(&_cw);
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return ((fp_prec_t)((_cw & FP_PRC_FLD) >> FP_PRC_OFF));
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}
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static __inline fp_prec_t
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__fpsetprec(fp_prec_t _m)
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{
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fp_prec_t _p;
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unsigned short _cw, _newcw;
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__fnstcw(&_cw);
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_p = (fp_prec_t)((_cw & FP_PRC_FLD) >> FP_PRC_OFF);
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_newcw = _cw & ~FP_PRC_FLD;
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_newcw |= (_m << FP_PRC_OFF) & FP_PRC_FLD;
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__fnldcw(_cw, _newcw);
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return (_p);
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}
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/*
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* Get or set the exception mask.
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* Note that the x87 mask bits are inverted by the API -- a mask bit of 1
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* means disable for x87 and SSE, but for fp*mask() it means enable.
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*/
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static __inline fp_except_t
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__fpgetmask(void)
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{
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unsigned short _cw;
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__fnstcw(&_cw);
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return ((~_cw & FP_MSKS_FLD) >> FP_MSKS_OFF);
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}
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static __inline fp_except_t
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__fpsetmask(fp_except_t _m)
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{
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fp_except_t _p;
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unsigned _mxcsr;
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unsigned short _cw, _newcw;
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__fnstcw(&_cw);
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_p = (~_cw & FP_MSKS_FLD) >> FP_MSKS_OFF;
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_newcw = _cw & ~FP_MSKS_FLD;
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_newcw |= (~_m << FP_MSKS_OFF) & FP_MSKS_FLD;
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__fnldcw(_cw, _newcw);
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__stmxcsr(&_mxcsr);
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/* XXX should we clear non-ieee SSE_DAZ_FLD and SSE_FZ_FLD ? */
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_mxcsr &= ~SSE_MSKS_FLD;
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_mxcsr |= (~_m << SSE_MSKS_OFF) & SSE_MSKS_FLD;
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__ldmxcsr(&_mxcsr);
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return (_p);
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}
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static __inline fp_except_t
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__fpgetsticky(void)
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{
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unsigned _ex, _mxcsr;
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unsigned short _sw;
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__fnstsw(&_sw);
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_ex = (_sw & FP_STKY_FLD) >> FP_STKY_OFF;
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__stmxcsr(&_mxcsr);
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_ex |= (_mxcsr & SSE_STKY_FLD) >> SSE_STKY_OFF;
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return ((fp_except_t)_ex);
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}
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#endif /* __GNUCLIKE_ASM */
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#if !defined(__IEEEFP_NOINLINES__) && defined(__GNUCLIKE_ASM)
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#define fpgetmask() __fpgetmask()
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#define fpgetprec() __fpgetprec()
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#define fpgetround() __fpgetround()
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#define fpgetsticky() __fpgetsticky()
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#define fpsetmask(m) __fpsetmask(m)
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#define fpsetprec(m) __fpsetprec(m)
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#define fpsetround(m) __fpsetround(m)
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/* Suppress prototypes in the MI header. */
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#define _IEEEFP_INLINED_ 1
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#else /* !(!__IEEEFP_NOINLINES__ && __GNUCLIKE_ASM) */
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/* Augment the userland declarations. */
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__BEGIN_DECLS
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fp_prec_t fpgetprec(void);
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fp_prec_t fpsetprec(fp_prec_t);
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__END_DECLS
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#endif /* !__IEEEFP_NOINLINES__ && __GNUCLIKE_ASM */
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#endif /* !_MACHINE_IEEEFP_H_ */
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