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0cfab8ddc1
and Core Duo), models 0xF (Core2), model 0x17 (Core2Extreme) and
model 0x1C (Atom).
In these CPUs, the actual numbers, kinds and widths of PMCs present
need to queried at run time. Support for specific "architectural"
events also needs to be queried at run time.
Model 0xE CPUs support programmable PMCs, subsequent CPUs
additionally support "fixed-function" counters.
- Use event names that are close to vendor documentation, taking in
account that:
- events with identical semantics on two or more CPUs in this family
can have differing names in vendor documentation,
- identical vendor event names may map to differing events across
CPUs,
- each type of CPU supports a different subset of measurable
events.
Fixed-function and programmable counters both use the same vendor
names for events. The use of a class name prefix ("iaf-" or
"iap-" respectively) permits these to be distinguished.
- In libpmc, refactor pmc_name_of_event() into a public interface
and an internal helper function, for use by log handling code.
- Minor code tweaks: staticize a global, freshen a few comments.
Tested by: gnn
127 lines
4.1 KiB
C
127 lines
4.1 KiB
C
/*-
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* Copyright (c) 2003-2008 Joseph Koshy
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* Copyright (c) 2007 The FreeBSD Foundation
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* All rights reserved.
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*
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* Portions of this software were developed by A. Joseph Koshy under
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* sponsorship from the FreeBSD Foundation and Google, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/* Machine dependent interfaces */
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#ifndef _MACHINE_PMC_MDEP_H
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#define _MACHINE_PMC_MDEP_H 1
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#ifdef _KERNEL
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struct pmc_mdep;
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#endif
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#include <dev/hwpmc/hwpmc_amd.h>
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#include <dev/hwpmc/hwpmc_core.h>
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#include <dev/hwpmc/hwpmc_piv.h>
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#include <dev/hwpmc/hwpmc_tsc.h>
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/*
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* Intel processors implementing V2 and later of the Intel performance
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* measurement architecture have PMCs of the following classes: TSC,
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* IAF and IAP.
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*/
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#define PMC_MDEP_CLASS_INDEX_TSC 0
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#define PMC_MDEP_CLASS_INDEX_K8 1
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#define PMC_MDEP_CLASS_INDEX_P4 1
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#define PMC_MDEP_CLASS_INDEX_IAP 1
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#define PMC_MDEP_CLASS_INDEX_IAF 2
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/*
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* On the amd64 platform we support the following PMCs.
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*
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* TSC The timestamp counter
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* K8 AMD Athlon64 and Opteron PMCs in 64 bit mode.
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* PIV Intel P4/HTT and P4/EMT64
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* IAP Intel Core/Core2/Atom CPUs in 64 bits mode.
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* IAF Intel fixed-function PMCs in Core2 and later CPUs.
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*/
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union pmc_md_op_pmcallocate {
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struct pmc_md_amd_op_pmcallocate pm_amd;
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struct pmc_md_iaf_op_pmcallocate pm_iaf;
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struct pmc_md_iap_op_pmcallocate pm_iap;
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struct pmc_md_p4_op_pmcallocate pm_p4;
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uint64_t __pad[4];
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};
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/* Logging */
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#define PMCLOG_READADDR PMCLOG_READ64
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#define PMCLOG_EMITADDR PMCLOG_EMIT64
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#ifdef _KERNEL
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union pmc_md_pmc {
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struct pmc_md_amd_pmc pm_amd;
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struct pmc_md_iaf_pmc pm_iaf;
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struct pmc_md_iap_pmc pm_iap;
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struct pmc_md_p4_pmc pm_p4;
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};
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#define PMC_TRAPFRAME_TO_PC(TF) ((TF)->tf_rip)
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#define PMC_TRAPFRAME_TO_FP(TF) ((TF)->tf_rbp)
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#define PMC_TRAPFRAME_TO_USER_SP(TF) ((TF)->tf_rsp)
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#define PMC_TRAPFRAME_TO_KERNEL_SP(TF) ((TF)->tf_rsp)
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#define PMC_AT_FUNCTION_PROLOGUE_PUSH_BP(I) \
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(((I) & 0xffffffff) == 0xe5894855) /* pushq %rbp; movq %rsp,%rbp */
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#define PMC_AT_FUNCTION_PROLOGUE_MOV_SP_BP(I) \
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(((I) & 0x00ffffff) == 0x00e58948) /* movq %rsp,%rbp */
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#define PMC_AT_FUNCTION_EPILOGUE_RET(I) \
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(((I) & 0xFF) == 0xC3) /* ret */
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#define PMC_IN_TRAP_HANDLER(PC) \
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((PC) >= (uintptr_t) start_exceptions && \
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(PC) < (uintptr_t) end_exceptions)
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#define PMC_IN_KERNEL_STACK(S,START,END) \
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((S) >= (START) && (S) < (END))
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#define PMC_IN_KERNEL(va) (((va) >= DMAP_MIN_ADDRESS && \
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(va) < DMAP_MAX_ADDRESS) || ((va) >= VM_MIN_KERNEL_ADDRESS && \
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(va) < VM_MAX_KERNEL_ADDRESS))
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#define PMC_IN_USERSPACE(va) ((va) <= VM_MAXUSER_ADDRESS)
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/*
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* Prototypes
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*/
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void start_exceptions(void), end_exceptions(void);
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void pmc_x86_lapic_enable_pmc_interrupt(void);
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struct pmc_mdep *pmc_amd_initialize(void);
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void pmc_amd_finalize(struct pmc_mdep *_md);
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struct pmc_mdep *pmc_intel_initialize(void);
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void pmc_intel_finalize(struct pmc_mdep *_md);
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#endif /* _KERNEL */
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#endif /* _MACHINE_PMC_MDEP_H */
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