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https://github.com/freebsd/freebsd-src.git
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548d35fd69
Features: Jumbo frames (up to 9600), LRO (Large Receive Offload),
TSO (TCP segmentation offload), RTH (Receive Traffic Hash).
Submitted by: Sriram Rapuru at Exar
MFC after: 2 weeks
252 lines
8.7 KiB
C
252 lines
8.7 KiB
C
/*-
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* Copyright(c) 2002-2011 Exar Corp.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification are permitted provided the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the Exar Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*$FreeBSD$*/
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#ifndef VXGE_DEFS_H
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#define VXGE_DEFS_H
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#define VXGE_PCI_VENDOR_ID 0x17D5
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#define VXGE_PCI_DEVICE_ID_TITAN_1 0x5833
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#define VXGE_PCI_REVISION_TITAN_1 1
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#define VXGE_PCI_DEVICE_ID_TITAN_1A 0x5833
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#define VXGE_PCI_REVISION_TITAN_1A 2
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#define VXGE_PCI_DEVICE_ID_TITAN_2 0x5834
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#define VXGE_PCI_REVISION_TITAN_2 1
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#define VXGE_MIN_FW_MAJOR_VERSION 1
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#define VXGE_MIN_FW_MINOR_VERSION 8
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#define VXGE_MIN_FW_BUILD_NUMBER 1
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#define VXGE_DRIVER_VENDOR "Exar Corp."
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#define VXGE_CHIP_FAMILY "X3100"
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#define VXGE_SUPPORTED_MEDIA_0 "Fiber"
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#define VXGE_DRIVER_NAME \
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"Neterion X3100 10GbE PCIe Server Adapter Driver"
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/*
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* mBIT(loc) - set bit at offset
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*/
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#define mBIT(loc) (0x8000000000000000ULL >> (loc))
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/*
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* vBIT(val, loc, sz) - set bits at offset
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*/
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#define vBIT(val, loc, sz) (((u64)(val)) << (64-(loc)-(sz)))
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#define vBIT32(val, loc, sz) (((u32)(val)) << (32-(loc)-(sz)))
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/*
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* bVALx(bits, loc) - Get the value of x bits at location
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*/
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#define bVAL1(bits, loc) ((((u64)bits) >> (64-(loc+1))) & 0x1)
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#define bVAL2(bits, loc) ((((u64)bits) >> (64-(loc+2))) & 0x3)
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#define bVAL3(bits, loc) ((((u64)bits) >> (64-(loc+3))) & 0x7)
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#define bVAL4(bits, loc) ((((u64)bits) >> (64-(loc+4))) & 0xF)
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#define bVAL5(bits, loc) ((((u64)bits) >> (64-(loc+5))) & 0x1F)
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#define bVAL6(bits, loc) ((((u64)bits) >> (64-(loc+6))) & 0x3F)
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#define bVAL7(bits, loc) ((((u64)bits) >> (64-(loc+7))) & 0x7F)
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#define bVAL8(bits, loc) ((((u64)bits) >> (64-(loc+8))) & 0xFF)
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#define bVAL9(bits, loc) ((((u64)bits) >> (64-(loc+9))) & 0x1FF)
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#define bVAL11(bits, loc) ((((u64)bits) >> (64-(loc+11))) & 0x7FF)
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#define bVAL12(bits, loc) ((((u64)bits) >> (64-(loc+12))) & 0xFFF)
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#define bVAL14(bits, loc) ((((u64)bits) >> (64-(loc+14))) & 0x3FFF)
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#define bVAL15(bits, loc) ((((u64)bits) >> (64-(loc+15))) & 0x7FFF)
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#define bVAL16(bits, loc) ((((u64)bits) >> (64-(loc+16))) & 0xFFFF)
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#define bVAL17(bits, loc) ((((u64)bits) >> (64-(loc+17))) & 0x1FFFF)
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#define bVAL18(bits, loc) ((((u64)bits) >> (64-(loc+18))) & 0x3FFFF)
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#define bVAL20(bits, loc) ((((u64)bits) >> (64-(loc+20))) & 0xFFFFF)
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#define bVAL22(bits, loc) ((((u64)bits) >> (64-(loc+22))) & 0x3FFFFF)
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#define bVAL24(bits, loc) ((((u64)bits) >> (64-(loc+24))) & 0xFFFFFF)
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#define bVAL28(bits, loc) ((((u64)bits) >> (64-(loc+28))) & 0xFFFFFFF)
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#define bVAL32(bits, loc) ((((u64)bits) >> (64-(loc+32))) & 0xFFFFFFFF)
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#define bVAL36(bits, loc) ((((u64)bits) >> (64-(loc+36))) & 0xFFFFFFFFFULL)
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#define bVAL40(bits, loc) ((((u64)bits) >> (64-(loc+40))) & 0xFFFFFFFFFFULL)
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#define bVAL44(bits, loc) ((((u64)bits) >> (64-(loc+44))) & 0xFFFFFFFFFFFULL)
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#define bVAL48(bits, loc) ((((u64)bits) >> (64-(loc+48))) & 0xFFFFFFFFFFFFULL)
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#define bVAL52(bits, loc) ((((u64)bits) >> (64-(loc+52))) & 0xFFFFFFFFFFFFFULL)
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#define bVAL56(bits, loc) ((((u64)bits) >> (64-(loc+56))) & 0xFFFFFFFFFFFFFFULL)
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#define bVAL60(bits, loc) \
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((((u64)bits) >> (64-(loc+60))) & 0xFFFFFFFFFFFFFFFULL)
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#define bVAL61(bits, loc) \
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((((u64)bits) >> (64-(loc+61))) & 0x1FFFFFFFFFFFFFFFULL)
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#define VXGE_HAL_VPATH_BMAP_START 47
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#define VXGE_HAL_VPATH_BMAP_END 63
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#define VXGE_HAL_ALL_FOXES 0xFFFFFFFFFFFFFFFFULL
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#define VXGE_HAL_INTR_MASK_ALL 0xFFFFFFFFFFFFFFFFULL
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#define VXGE_HAL_MAX_VIRTUAL_PATHS 17
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#define VXGE_HAL_MAX_FUNCTIONS 8
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#define VXGE_HAL_MAX_ITABLE_ENTRIES 256
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#define VXGE_HAL_MAX_RSS_KEY_SIZE 40
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#define VXGE_HAL_MAC_MAX_WIRE_PORTS 2
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#define VXGE_HAL_MAC_SWITCH_PORT 2
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#define VXGE_HAL_MAC_MAX_AGGR_PORTS 2
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#define VXGE_HAL_MAC_MAX_PORTS 3
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#define VXGE_HAL_INTR_ALARM (1<<4)
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#define VXGE_HAL_INTR_TX (1<<(3-VXGE_HAL_VPATH_INTR_TX))
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#define VXGE_HAL_INTR_RX (1<<(3-VXGE_HAL_VPATH_INTR_RX))
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#define VXGE_HAL_INTR_EINTA (1<<(3-VXGE_HAL_VPATH_INTR_EINTA))
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#define VXGE_HAL_INTR_BMAP (1<<(3-VXGE_HAL_VPATH_INTR_BMAP))
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#define VXGE_HAL_PCI_CONFIG_SPACE_SIZE VXGE_OS_PCI_CONFIG_SIZE
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#define VXGE_HAL_DEFAULT_32 0xffffffff
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#define VXGE_HAL_DEFAULT_64 0xffffffffffffffff
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#define VXGE_HAL_DUMP_BUF_SIZE 0x10000
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#define VXGE_HAL_VPD_BUFFER_SIZE 128
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#define VXGE_HAL_VPD_LENGTH 80
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/* Check whether an address is multicast. */
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#define VXGE_HAL_IS_NULL(Address) (Address == 0x0000000000000000ULL)
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/* Check whether an address is multicast. */
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#define VXGE_HAL_IS_MULTICAST(Address) (Address & 0x0000010000000000ULL)
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/* Check whether an address is broadcast. */
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#define VXGE_HAL_IS_BROADCAST(Address) \
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((Address & 0x0000FFFF00000000ULL) == 0x0000FFFF00000000ULL)
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#define VXGE_HAL_IS_UNICAST(Address) \
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(!(VXGE_HAL_IS_NULL(Address) || \
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VXGE_HAL_IS_MULTICAST(Address) || \
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VXGE_HAL_IS_BROADCAST(Address)))
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/* frames sizes */
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#define VXGE_HAL_HEADER_ETHERNET_II_802_3_SIZE 14
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#define VXGE_HAL_HEADER_802_2_SIZE 3
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#define VXGE_HAL_HEADER_SNAP_SIZE 5
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#define VXGE_HAL_HEADER_VLAN_SIZE 4
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#define VXGE_HAL_MAC_HEADER_MAX_SIZE \
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(VXGE_HAL_HEADER_ETHERNET_II_802_3_SIZE + \
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VXGE_HAL_HEADER_802_2_SIZE + \
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VXGE_HAL_HEADER_SNAP_SIZE)
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#define VXGE_HAL_TCPIP_HEADER_MAX_SIZE (64 + 64)
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/* 32bit alignments */
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/* A receive data corruption can occur resulting in either a single-bit or
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double-bit ECC error being flagged in the ASIC if starting offset of a
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buffer in single buffer mode is 0x2 to 0xa. Single bit ECC error will not
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lock up the card but can hide the data corruption while the double-bit ECC
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error will lock up the card. Limiting the starting offset of the buffers to
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0x0, 0x1 or to a value greater than 0xF will workaround this issue.
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VXGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN of 2 causes the starting offset of
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buffer to be 0x2, 0x12 and so on, to have the start of the ip header dword
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aligned. The start of buffer of 0x2 will cause this problem to occur.
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To avoid this problem in all cases, add 0x10 to 0x2, to ensure that the start
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of buffer is outside of the problem causing offsets.
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*/
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#define VXGE_HAL_HEADER_ETHERNET_II_802_3_ALIGN 0x12
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#define VXGE_HAL_HEADER_802_2_SNAP_ALIGN 2
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#define VXGE_HAL_HEADER_802_2_ALIGN 3
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#define VXGE_HAL_HEADER_SNAP_ALIGN 1
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#define VXGE_HAL_MIN_MTU 46
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#define VXGE_HAL_MAX_MTU 9600
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#define VXGE_HAL_DEFAULT_MTU 1500
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#define VXGE_HAL_SEGEMENT_OFFLOAD_MAX_SIZE 81920
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#if defined(__EXTERN_BEGIN_DECLS)
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#undef __EXTERN_BEGIN_DECLS
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#endif
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#if defined(__EXTERN_END_DECLS)
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#undef __EXTERN_END_DECLS
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#endif
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#if defined(__cplusplus)
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#define __EXTERN_BEGIN_DECLS extern "C" {
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#define __EXTERN_END_DECLS }
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#else
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#define __EXTERN_BEGIN_DECLS
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#define __EXTERN_END_DECLS
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#endif
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__EXTERN_BEGIN_DECLS
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/* --------------------------- common stuffs ------------------------------ */
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/*
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* VXGE_OS_DMA_REQUIRES_SYNC - should be defined or
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* NOT defined in the Makefile
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*/
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#define VXGE_OS_DMA_CACHELINE_ALIGNED 0x1
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/*
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* Either STREAMING or CONSISTENT should be used.
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* The combination of both or none is invalid
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*/
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#define VXGE_OS_DMA_STREAMING 0x2
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#define VXGE_OS_DMA_CONSISTENT 0x4
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#define VXGE_OS_SPRINTF_STRLEN 64
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/* --------------------------- common stuffs ------------------------------ */
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#ifndef VXGE_OS_LLXFMT
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#define VXGE_OS_LLXFMT "%llx"
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#endif
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#ifndef VXGE_OS_LLDFMT
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#define VXGE_OS_LLDFMT "%lld"
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#endif
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#ifndef VXGE_OS_STXFMT
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#define VXGE_OS_STXFMT "%zx"
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#endif
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#ifndef VXGE_OS_STDFMT
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#define VXGE_OS_STDFMT "%zd"
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#endif
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__EXTERN_END_DECLS
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#endif /* VXGE_DEFS_H */
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