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548d35fd69
Features: Jumbo frames (up to 9600), LRO (Large Receive Offload),
TSO (TCP segmentation offload), RTH (Receive Traffic Hash).
Submitted by: Sriram Rapuru at Exar
MFC after: 2 weeks
266 lines
7.2 KiB
C
266 lines
7.2 KiB
C
/*-
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* Copyright(c) 2002-2011 Exar Corp.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification are permitted provided the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the Exar Corporation nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*$FreeBSD$*/
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#ifndef VXGE_HAL_DEVICE_H
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#define VXGE_HAL_DEVICE_H
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__EXTERN_BEGIN_DECLS
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struct __hal_mrpcim_t;
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struct __hal_srpcim_t;
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/*
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* vxge_hal_vpd_data_t
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*
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* Represents vpd capabilty structure
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*/
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typedef struct vxge_hal_vpd_data_t {
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u8 product_name[VXGE_HAL_VPD_LEN];
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u8 serial_num[VXGE_HAL_VPD_LEN];
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} vxge_hal_vpd_data_t;
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#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
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/*
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* __hal_tracebuf_t
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*
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* HAL trace buffer object.
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*/
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typedef struct __hal_tracebuf_t {
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u8 *data;
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u64 wrapped_count;
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volatile u32 offset;
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u32 size;
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} __hal_tracebuf_t;
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#endif
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/*
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* __hal_msix_map_t
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*
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* HAL msix to vpath map.
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*/
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typedef struct __hal_msix_map_t {
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u32 vp_id;
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u32 int_num;
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} __hal_msix_map_t;
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/*
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* __hal_device_t
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*
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* HAL device object. Represents X3100.
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*/
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typedef struct __hal_device_t {
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vxge_hal_device_t header;
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u32 host_type;
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u32 vh_id;
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u32 func_id;
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u32 srpcim_id;
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u32 access_rights;
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#define VXGE_HAL_DEVICE_ACCESS_RIGHT_VPATH 0x1
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#define VXGE_HAL_DEVICE_ACCESS_RIGHT_SRPCIM 0x2
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#define VXGE_HAL_DEVICE_ACCESS_RIGHT_MRPCIM 0x4
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u32 ifmsg_seqno;
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u32 manager_up;
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vxge_hal_pci_config_t pci_config_space;
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vxge_hal_pci_config_t pci_config_space_bios;
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vxge_hal_pci_caps_offset_t pci_caps;
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vxge_hal_pci_e_caps_offset_t pci_e_caps;
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vxge_hal_pci_e_ext_caps_offset_t pci_e_ext_caps;
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vxge_hal_legacy_reg_t *legacy_reg;
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vxge_hal_toc_reg_t *toc_reg;
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vxge_hal_common_reg_t *common_reg;
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vxge_hal_memrepair_reg_t *memrepair_reg;
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vxge_hal_pcicfgmgmt_reg_t
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*pcicfgmgmt_reg[VXGE_HAL_TITAN_PCICFGMGMT_REG_SPACES];
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vxge_hal_mrpcim_reg_t *mrpcim_reg;
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vxge_hal_srpcim_reg_t
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*srpcim_reg[VXGE_HAL_TITAN_SRPCIM_REG_SPACES];
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vxge_hal_vpmgmt_reg_t
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*vpmgmt_reg[VXGE_HAL_TITAN_VPMGMT_REG_SPACES];
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vxge_hal_vpath_reg_t
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*vpath_reg[VXGE_HAL_TITAN_VPATH_REG_SPACES];
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u8 *kdfc;
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u8 *usdc;
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__hal_virtualpath_t
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virtual_paths[VXGE_HAL_MAX_VIRTUAL_PATHS];
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u64 vpath_assignments;
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u64 vpaths_deployed;
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u32 first_vp_id;
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u64 tim_int_mask0[4];
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u32 tim_int_mask1[4];
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__hal_msix_map_t
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msix_map[VXGE_HAL_MAX_VIRTUAL_PATHS * VXGE_HAL_VPATH_MSIX_MAX];
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struct __hal_srpcim_t *srpcim;
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struct __hal_mrpcim_t *mrpcim;
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__hal_blockpool_t block_pool;
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vxge_list_t pending_channel_list;
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spinlock_t pending_channel_lock;
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vxge_hal_device_stats_t stats;
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volatile u32 msix_enabled;
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volatile u32 hw_is_initialized;
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volatile int device_resetting;
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volatile int is_promisc;
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int tti_enabled;
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spinlock_t titan_post_lock;
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u32 mtu_first_time_set;
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char *dump_buf;
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#if defined(VXGE_TRACE_INTO_CIRCULAR_ARR)
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__hal_tracebuf_t trace_buf;
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#endif
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volatile u32 in_poll;
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u32 d_err_mask;
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u32 d_info_mask;
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u32 d_trace_mask;
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} __hal_device_t;
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/*
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* I2C device id. Used in I2C control register for accessing EEPROM device
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* memory.
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*/
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#define VXGE_DEV_ID 5
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#define VXGE_HAL_DEVICE_MANAGER_STATE_SET(hldev, wmsg) { \
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((__hal_device_t *)hldev)->manager_up = \
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__hal_ifmsg_is_manager_up(wmsg); \
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}
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#define VXGE_HAL_DEVICE_LINK_STATE_SET(hldev, ls) { \
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((vxge_hal_device_t *)hldev)->link_state = ls; \
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}
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#define VXGE_HAL_DEVICE_DATA_RATE_SET(hldev, dr) { \
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((vxge_hal_device_t *)hldev)->data_rate = dr; \
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}
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#define VXGE_HAL_DEVICE_TIM_INT_MASK_SET(hldev, i) { \
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if (i < 16) { \
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((__hal_device_t *)hldev)->tim_int_mask0[0] |= \
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vBIT(0x8, (i*4), 4); \
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((__hal_device_t *)hldev)->tim_int_mask0[1] |= \
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vBIT(0x4, (i*4), 4); \
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((__hal_device_t *)hldev)->tim_int_mask0[3] |= \
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vBIT(0x1, (i*4), 4); \
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} else { \
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((__hal_device_t *)hldev)->tim_int_mask1[0] = 0x80000000; \
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((__hal_device_t *)hldev)->tim_int_mask1[1] = 0x40000000; \
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((__hal_device_t *)hldev)->tim_int_mask1[3] = 0x10000000; \
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} \
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}
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#define VXGE_HAL_DEVICE_TIM_INT_MASK_RESET(hldev, i) { \
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if (i < 16) { \
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((__hal_device_t *)hldev)->tim_int_mask0[0] &= \
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~vBIT(0x8, (i*4), 4); \
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((__hal_device_t *)hldev)->tim_int_mask0[1] &= \
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~vBIT(0x4, (i*4), 4); \
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((__hal_device_t *)hldev)->tim_int_mask0[3] &= \
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~vBIT(0x1, (i*4), 4); \
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} else { \
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((__hal_device_t *)hldev)->tim_int_mask1[0] = 0; \
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((__hal_device_t *)hldev)->tim_int_mask1[1] = 0; \
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((__hal_device_t *)hldev)->tim_int_mask1[3] = 0; \
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} \
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}
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/* ========================== PRIVATE API ================================= */
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void
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vxge_hal_pio_mem_write32_upper(pci_dev_h pdev,
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pci_reg_h regh,
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u32 val,
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void *addr);
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void
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vxge_hal_pio_mem_write32_lower(pci_dev_h pdev,
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pci_reg_h regh,
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u32 val,
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void *addr);
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void
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__hal_device_event_queued(void *data,
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u32 event_type);
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void
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__hal_device_pci_caps_list_process(__hal_device_t *hldev);
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void
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__hal_device_pci_e_init(__hal_device_t *hldev);
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vxge_hal_status_e
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vxge_hal_device_register_poll(pci_dev_h pdev,
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pci_reg_h regh,
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u64 *reg,
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u32 op,
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u64 mask,
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u32 max_millis);
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vxge_hal_status_e
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__hal_device_register_stall(pci_dev_h pdev,
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pci_reg_h regh,
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u64 *reg,
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u32 op,
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u64 mask,
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u32 max_millis);
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vxge_hal_status_e
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__hal_device_reg_addr_get(__hal_device_t *hldev);
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void
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__hal_device_id_get(__hal_device_t *hldev);
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u32
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__hal_device_access_rights_get(u32 host_type, u32 func_id);
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void
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__hal_device_host_info_get(__hal_device_t *hldev);
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vxge_hal_status_e
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__hal_device_hw_initialize(__hal_device_t *hldev);
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vxge_hal_status_e
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__hal_device_reset(__hal_device_t *hldev);
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vxge_hal_status_e
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__hal_device_handle_link_up_ind(__hal_device_t *hldev);
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vxge_hal_status_e
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__hal_device_handle_link_down_ind(__hal_device_t *hldev);
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void
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__hal_device_handle_error(
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__hal_device_t *hldev,
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u32 vp_id,
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vxge_hal_event_e type);
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__EXTERN_END_DECLS
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#endif /* VXGE_HAL_DEVICE_H */
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