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ae9742be10
bus number into the bus argument. The bus number occupies the least significant 8 bits. The PCI domain occupies the most significant 24 bits. On the Altix 350, the PCI domain is a required parameter, but changing the prototype of the pci_cfgreg*() functions to include a separate domain argument has wide-spread consequences across the supported architectures. We'd be changing a known interface. Multiplexing is an acceptable kluge to give us what we need with manageable impact. Note that the PCI bus number fits in 8 bits, so the multiplexing of the domain is a backward compatible change.
105 lines
2.9 KiB
C
105 lines
2.9 KiB
C
/*-
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* Copyright (c) 2010 Marcel Moolenaar
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* Copyright (c) 2001 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <machine/cpufunc.h>
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#include <machine/pci_cfgreg.h>
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#include <machine/sal.h>
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static u_long
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pci_sal_address(int dom, int bus, int slot, int func, int reg)
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{
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u_long addr;
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addr = ~0ul;
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if (dom >= 0 && dom <= 255 && bus >= 0 && bus <= 255 &&
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slot >= 0 && slot <= 31 && func >= 0 && func <= 7 &&
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reg >= 0 && reg <= 255) {
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addr = ((u_long)dom << 24) | ((u_long)bus << 16) |
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((u_long)slot << 11) | ((u_long)func << 8) | (u_long)reg;
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}
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return (addr);
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}
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static int
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pci_valid_access(int reg, int len)
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{
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int ok;
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ok = ((len == 1 || len == 2 || len == 4) && (reg & (len - 1)) == 0)
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? 1 : 0;
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return (ok);
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}
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int
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pci_cfgregopen(void)
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{
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return (1);
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}
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uint32_t
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pci_cfgregread(int bus, int slot, int func, int reg, int len)
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{
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struct ia64_sal_result res;
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register_t is;
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u_long addr;
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addr = pci_sal_address(bus >> 8, bus & 0xff, slot, func, reg);
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if (addr == ~0ul)
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return (~0);
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if (!pci_valid_access(reg, len))
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return (~0);
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is = intr_disable();
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res = ia64_sal_entry(SAL_PCI_CONFIG_READ, addr, len, 0, 0, 0, 0, 0);
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intr_restore(is);
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return ((res.sal_status < 0) ? ~0 : res.sal_result[0]);
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}
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void
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pci_cfgregwrite(int bus, int slot, int func, int reg, uint32_t data, int len)
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{
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struct ia64_sal_result res;
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register_t is;
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u_long addr;
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addr = pci_sal_address(bus >> 8, bus & 0xff, slot, func, reg);
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if (addr == ~0ul)
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return;
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if (!pci_valid_access(reg, len))
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return;
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is = intr_disable();
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res = ia64_sal_entry(SAL_PCI_CONFIG_WRITE, addr, len, data, 0, 0, 0, 0);
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intr_restore(is);
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}
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