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6ec3db1bb9
Change static max allocators to 30. Add atomic add/sub macros returning original value, based on CASIO. Add interfaces to add and remove generic allocator caches. Add atomic inc/dec/sub macros using MCAS primitives. Add inline assembly for x86_64 and shim for Solaris (9+) atomic operations, providing Solaris x86 and alternate shim for Solaris Sparc. Set interface adapted for iteration and generalized for use with opaque key, value pointers. File cas_skip_func.c provides kv interface, cas_skip_adt.c provides kv interface, plus iteration on skip lists. Casual dependencies on stdio and exit() defined out. LICENSE BSD Reviewed-on: http://gerrit.openafs.org/214 Reviewed-by: Derrick Brashear <shadow@dementia.org> Tested-by: Derrick Brashear <shadow@dementia.org>
130 lines
4.0 KiB
C
130 lines
4.0 KiB
C
/*
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Copyright (c) 2003, Keir Fraser All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution. Neither the name of the Keir Fraser
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* nor the names of its contributors may be used to endorse or
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* promote products derived from this software without specific
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* prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __IA64_DEFNS_H__
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#define __IA64_DEFNS_H__
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#include <pthread.h>
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#include <sched.h>
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#ifndef IA64
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#define IA64
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#endif
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#define CACHE_LINE_SIZE 64
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/*
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* I. Compare-and-swap.
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*/
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#define CAS32(_a, _o, _n) \
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({ __typeof__(_o) __o = _o; \
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__asm__ __volatile__("mov ar.ccv=%0 ;;" :: "rO" (_o)); \
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__asm__ __volatile__("cmpxchg4.acq %0=%1,%2,ar.ccv ;; " \
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: "=r" (__o), "=m" (*(_a)) \
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: "r"(_n)); \
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__o; \
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})
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#define CAS64(_a, _o, _n) \
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({ __typeof__(_o) __o = _o; \
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__asm__ __volatile__("mov ar.ccv=%0 ;;" :: "rO" (_o)); \
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__asm__ __volatile__("cmpxchg8.acq %0=%1,%2,ar.ccv ;; " \
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: "=r" (__o), "=m" (*(_a)) \
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: "r"(_n)); \
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__o; \
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})
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#define FAS32(_a, _n) \
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({ __typeof__(_n) __o; \
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__asm__ __volatile__("xchg4 %0=%1,%2 ;; " \
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: "=r" (__o), "=m" (*(_a)) \
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: "r"(_n)); \
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__o; \
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})
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#define FAS64(_a, _n) \
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({ __typeof__(_n) __o; \
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__asm__ __volatile__("xchg8 %0=%1,%2 ;; " \
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: "=r" (__o), "=m" (*(_a)) \
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: "r"(_n)); \
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__o; \
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})
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#define CAS(_x,_o,_n) ((sizeof (*_x) == 4)?CAS32(_x,_o,_n):CAS64(_x,_o,_n))
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#define FAS(_x,_n) ((sizeof (*_x) == 4)?FAS32(_x,_n) :FAS64(_x,_n))
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/* Update Integer location, return Old value. */
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#define CASIO CAS
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#define FASIO FAS
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/* Update Pointer location, return Old value. */
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#define CASPO CAS64
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#define FASPO FAS64
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/* Update 32/64-bit location, return Old value. */
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#define CAS32O CAS32
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#define CAS64O CAS64
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/*
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* II. Memory barriers.
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* WMB(): All preceding write operations must commit before any later writes.
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* RMB(): All preceding read operations must commit before any later reads.
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* MB(): All preceding memory accesses must commit before any later accesses.
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*
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* If the compiler does not observe these barriers (but any sane compiler
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* will!), then VOLATILE should be defined as 'volatile'.
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*/
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#define MB() __asm__ __volatile__ (";; mf ;; " : : : "memory")
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#define WMB() MB()
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#define RMB() MB()
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#define VOLATILE /*volatile*/
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/*
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* III. Cycle counter access.
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*/
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typedef unsigned long long tick_t;
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#define RDTICK() \
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({ tick_t __t; __asm__ __volatile__ ("mov %0=ar.itc ;;" : "=rO" (__t)); __t; })
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/*
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* IV. Types.
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*/
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typedef unsigned char _u8;
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typedef unsigned short _u16;
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typedef unsigned int _u32;
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typedef unsigned long long _u64;
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#endif /* __IA64_DEFNS_H__ */
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