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Merge pull request #20708 from alexrp/target-cleanup-2

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`std.Target`: Remove more dead architecture tags.
This commit is contained in:
Andrew Kelley 2024-07-21 19:24:04 -07:00 committed by GitHub
commit 179a6e61e8
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8 changed files with 32 additions and 199 deletions
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38
lib/compiler/aro/aro/target.zig vendored
View File

@ -17,8 +17,6 @@ pub fn intMaxType(target: std.Target) Type {
.riscv64,
.powerpc64,
.powerpc64le,
.tce,
.tcele,
.ve,
=> return .{ .specifier = .long },
@ -54,8 +52,6 @@ pub fn intPtrType(target: std.Target) Type {
.riscv32,
.xcore,
.hexagon,
.tce,
.tcele,
.m68k,
.spir,
.spirv32,
@ -153,7 +149,7 @@ pub fn isTlsSupported(target: std.Target) bool {
return supported;
}
return switch (target.cpu.arch) {
.tce, .tcele, .bpfel, .bpfeb, .msp430, .nvptx, .nvptx64, .x86, .arm, .armeb, .thumb, .thumbeb => false,
.bpfel, .bpfeb, .msp430, .nvptx, .nvptx64, .x86, .arm, .armeb, .thumb, .thumbeb => false,
else => true,
};
}
@ -470,25 +466,18 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
.mipsel,
.powerpc,
.powerpcle,
.r600,
.riscv32,
.sparc,
.sparcel,
.tce,
.tcele,
.thumb,
.thumbeb,
.x86,
.xcore,
.nvptx,
.amdil,
.hsail,
.spir,
.kalimba,
.shave,
.lanai,
.wasm32,
.renderscript32,
.aarch64_32,
.spirv32,
.loongarch32,
@ -498,13 +487,10 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
.aarch64 => copy.cpu.arch = .arm,
.aarch64_be => copy.cpu.arch = .armeb,
.amdil64 => copy.cpu.arch = .amdil,
.nvptx64 => copy.cpu.arch = .nvptx,
.wasm64 => copy.cpu.arch = .wasm32,
.hsail64 => copy.cpu.arch = .hsail,
.spir64 => copy.cpu.arch = .spir,
.spirv64 => copy.cpu.arch = .spirv32,
.renderscript64 => copy.cpu.arch = .renderscript32,
.loongarch64 => copy.cpu.arch = .loongarch32,
.mips64 => copy.cpu.arch = .mips,
.mips64el => copy.cpu.arch = .mipsel,
@ -529,12 +515,8 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.lanai,
.m68k,
.msp430,
.r600,
.shave,
.sparcel,
.spu_2,
.tce,
.tcele,
.xcore,
.xtensa,
=> return null,
@ -544,13 +526,10 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
.amdgcn,
.bpfeb,
.bpfel,
.amdil64,
.nvptx64,
.wasm64,
.hsail64,
.spir64,
.spirv64,
.renderscript64,
.loongarch64,
.mips64,
.mips64el,
@ -564,17 +543,14 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
=> {}, // Already 64 bit
.aarch64_32 => copy.cpu.arch = .aarch64,
.amdil => copy.cpu.arch = .amdil64,
.arm => copy.cpu.arch = .aarch64,
.armeb => copy.cpu.arch = .aarch64_be,
.hsail => copy.cpu.arch = .hsail64,
.loongarch32 => copy.cpu.arch = .loongarch64,
.mips => copy.cpu.arch = .mips64,
.mipsel => copy.cpu.arch = .mips64el,
.nvptx => copy.cpu.arch = .nvptx64,
.powerpc => copy.cpu.arch = .powerpc64,
.powerpcle => copy.cpu.arch = .powerpc64le,
.renderscript32 => copy.cpu.arch = .renderscript64,
.riscv32 => copy.cpu.arch = .riscv64,
.sparc => copy.cpu.arch = .sparc64,
.spir => copy.cpu.arch = .spir64,
@ -620,7 +596,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.powerpcle => "powerpcle",
.powerpc64 => "powerpc64",
.powerpc64le => "powerpc64le",
.r600 => "r600",
.amdgcn => "amdgcn",
.riscv32 => "riscv32",
.riscv64 => "riscv64",
@ -628,8 +603,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.sparc64 => "sparc64",
.sparcel => "sparcel",
.s390x => "s390x",
.tce => "tce",
.tcele => "tcele",
.thumb => "thumb",
.thumbeb => "thumbeb",
.x86 => "i386",
@ -638,21 +611,14 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.xtensa => "xtensa",
.nvptx => "nvptx",
.nvptx64 => "nvptx64",
.amdil => "amdil",
.amdil64 => "amdil64",
.hsail => "hsail",
.hsail64 => "hsail64",
.spir => "spir",
.spir64 => "spir64",
.spirv32 => "spirv32",
.spirv64 => "spirv64",
.kalimba => "kalimba",
.shave => "shave",
.lanai => "lanai",
.wasm32 => "wasm32",
.wasm64 => "wasm64",
.renderscript32 => "renderscript32",
.renderscript64 => "renderscript64",
.ve => "ve",
// Note: spu_2 is not supported in LLVM; this is the Zig arch name
.spu_2 => "spu_2",
@ -668,7 +634,7 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
.freebsd => "freebsd",
.fuchsia => "fuchsia",
.linux => "linux",
.lv2 => "lv2",
.ps3 => "lv2",
.netbsd => "netbsd",
.openbsd => "openbsd",
.solaris => "solaris",

127
lib/std/Target.zig
View File

@ -24,7 +24,7 @@ pub const Os = struct {
fuchsia,
ios,
linux,
lv2,
ps3,
macos,
netbsd,
openbsd,
@ -63,6 +63,11 @@ pub const Os = struct {
illumos,
other,
// LLVM tags deliberately omitted:
// - kfreebsd
// - darwin
// - nacl
pub inline fn isDarwin(tag: Tag) bool {
return switch (tag) {
.ios, .macos, .watchos, .tvos, .visionos => true,
@ -138,7 +143,7 @@ pub const Os = struct {
.ananas,
.cloudabi,
.fuchsia,
.lv2,
.ps3,
.zos,
.haiku,
.minix,
@ -370,7 +375,7 @@ pub const Os = struct {
.ananas,
.cloudabi,
.fuchsia,
.lv2,
.ps3,
.zos,
.haiku,
.minix,
@ -557,7 +562,7 @@ pub const Os = struct {
.ananas,
.cloudabi,
.fuchsia,
.lv2,
.ps3,
.zos,
.minix,
.rtems,
@ -653,13 +658,17 @@ pub const Abi = enum {
amplification,
ohos,
// LLVM tags deliberately omitted:
// - gnuf64
// - coreclr
pub fn default(arch: Cpu.Arch, os: Os) Abi {
return if (arch.isWasm()) .musl else switch (os.tag) {
.freestanding,
.ananas,
.cloudabi,
.dragonfly,
.lv2,
.ps3,
.zos,
.minix,
.rtems,
@ -994,7 +1003,6 @@ pub const Cpu = struct {
powerpcle,
powerpc64,
powerpc64le,
r600,
amdgcn,
riscv32,
riscv64,
@ -1002,8 +1010,6 @@ pub const Cpu = struct {
sparc64,
sparcel,
s390x,
tce,
tcele,
thumb,
thumbeb,
x86,
@ -1012,25 +1018,30 @@ pub const Cpu = struct {
xtensa,
nvptx,
nvptx64,
amdil,
amdil64,
hsail,
hsail64,
spir,
spir64,
spirv,
spirv32,
spirv64,
kalimba,
shave,
lanai,
wasm32,
wasm64,
renderscript32,
renderscript64,
ve,
spu_2,
// LLVM tags deliberately omitted:
// - r600
// - le32
// - le64
// - amdil
// - amdil64
// - hsail
// - hsail64
// - shave
// - renderscript32
// - renderscript64
pub inline fn isX86(arch: Arch) bool {
return switch (arch) {
.x86, .x86_64 => true,
@ -1148,26 +1159,19 @@ pub const Cpu = struct {
.mips => .MIPS,
.mipsel => .MIPS_RS3_LE,
.powerpc, .powerpcle => .PPC,
.r600 => .NONE,
.riscv32 => .RISCV,
.sparc => .SPARC,
.sparcel => .SPARC,
.tce => .NONE,
.tcele => .NONE,
.thumb => .ARM,
.thumbeb => .ARM,
.x86 => .@"386",
.xcore => .XCORE,
.xtensa => .XTENSA,
.nvptx => .NONE,
.amdil => .NONE,
.hsail => .NONE,
.spir => .NONE,
.kalimba => .CSR_KALIMBA,
.shave => .NONE,
.lanai => .LANAI,
.wasm32 => .NONE,
.renderscript32 => .NONE,
.aarch64_32 => .AARCH64,
.aarch64 => .AARCH64,
.aarch64_be => .AARCH64,
@ -1178,11 +1182,8 @@ pub const Cpu = struct {
.riscv64 => .RISCV,
.x86_64 => .X86_64,
.nvptx64 => .NONE,
.amdil64 => .NONE,
.hsail64 => .NONE,
.spir64 => .NONE,
.wasm64 => .NONE,
.renderscript64 => .NONE,
.amdgcn => .AMDGPU,
.bpfel => .BPF,
.bpfeb => .BPF,
@ -1212,26 +1213,19 @@ pub const Cpu = struct {
.mips => .Unknown,
.mipsel => .Unknown,
.powerpc, .powerpcle => .POWERPC,
.r600 => .Unknown,
.riscv32 => .RISCV32,
.sparc => .Unknown,
.sparcel => .Unknown,
.tce => .Unknown,
.tcele => .Unknown,
.thumb => .Thumb,
.thumbeb => .Thumb,
.x86 => .I386,
.xcore => .Unknown,
.xtensa => .Unknown,
.nvptx => .Unknown,
.amdil => .Unknown,
.hsail => .Unknown,
.spir => .Unknown,
.kalimba => .Unknown,
.shave => .Unknown,
.lanai => .Unknown,
.wasm32 => .Unknown,
.renderscript32 => .Unknown,
.aarch64_32 => .ARM64,
.aarch64 => .ARM64,
.aarch64_be => .ARM64,
@ -1242,11 +1236,8 @@ pub const Cpu = struct {
.riscv64 => .RISCV64,
.x86_64 => .X64,
.nvptx64 => .Unknown,
.amdil64 => .Unknown,
.hsail64 => .Unknown,
.spir64 => .Unknown,
.wasm64 => .Unknown,
.renderscript64 => .Unknown,
.amdgcn => .Unknown,
.bpfel => .Unknown,
.bpfeb => .Unknown,
@ -1270,14 +1261,10 @@ pub const Cpu = struct {
.aarch64_32,
.aarch64,
.amdgcn,
.amdil,
.amdil64,
.bpfel,
.csky,
.xtensa,
.hexagon,
.hsail,
.hsail64,
.kalimba,
.mipsel,
.mips64el,
@ -1285,10 +1272,8 @@ pub const Cpu = struct {
.nvptx,
.nvptx64,
.sparcel,
.tcele,
.powerpcle,
.powerpc64le,
.r600,
.riscv32,
.riscv64,
.x86,
@ -1299,9 +1284,6 @@ pub const Cpu = struct {
.thumb,
.spir,
.spir64,
.renderscript32,
.renderscript64,
.shave,
.ve,
.spu_2,
// GPU bitness is opaque. For now, assume little endian.
@ -1325,7 +1307,6 @@ pub const Cpu = struct {
.thumbeb,
.sparc,
.sparc64,
.tce,
.lanai,
.s390x,
=> .big,
@ -1780,22 +1761,12 @@ pub const DynamicLinker = struct {
.hexagon,
.m68k,
.msp430,
.r600,
.amdgcn,
.tce,
.tcele,
.xcore,
.amdil,
.amdil64,
.hsail,
.hsail64,
.spir,
.spir64,
.kalimba,
.shave,
.lanai,
.renderscript32,
.renderscript64,
.ve,
.dxil,
.loongarch32,
@ -1834,7 +1805,7 @@ pub const DynamicLinker = struct {
.ananas,
.cloudabi,
.fuchsia,
.lv2,
.ps3,
.zos,
.minix,
.rtems,
@ -1884,24 +1855,17 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
.mipsel,
.powerpc,
.powerpcle,
.r600,
.riscv32,
.sparcel,
.tce,
.tcele,
.thumb,
.thumbeb,
.x86,
.xcore,
.nvptx,
.amdil,
.hsail,
.spir,
.kalimba,
.shave,
.lanai,
.wasm32,
.renderscript32,
.aarch64_32,
.spirv32,
.loongarch32,
@ -1918,11 +1882,8 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
.riscv64,
.x86_64,
.nvptx64,
.amdil64,
.hsail64,
.spir64,
.wasm64,
.renderscript64,
.amdgcn,
.bpfel,
.bpfeb,
@ -2070,12 +2031,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
.long, .ulong, .float, .double, .longdouble => return 32,
.longlong, .ulonglong => return 64,
},
.tce, .tcele => switch (c_type) {
.char => return 8,
.short, .ushort => return 16,
.int, .uint, .long, .ulong, .longlong, .ulonglong => return 32,
.float, .double, .longdouble => return 32,
},
.mips64, .mips64el => switch (c_type) {
.char => return 8,
.short, .ushort => return 16,
@ -2165,12 +2120,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
.long, .ulong, .float, .double, .longdouble => return 32,
.longlong, .ulonglong => return 64,
},
.tce, .tcele => switch (c_type) {
.char => return 8,
.short, .ushort => return 16,
.int, .uint, .long, .ulong, .longlong, .ulonglong => return 32,
.float, .double, .longdouble => return 32,
},
.mips64, .mips64el => switch (c_type) {
.char => return 8,
.short, .ushort => return 16,
@ -2351,7 +2300,7 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
},
.cloudabi,
.lv2,
.ps3,
.zos,
.rtems,
.aix,
@ -2418,15 +2367,9 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.xcore,
.dxil,
.loongarch32,
.tce,
.tcele,
.amdil,
.hsail,
.spir,
.spirv32,
.kalimba,
.shave,
.renderscript32,
.ve,
.spu_2,
.xtensa,
@ -2434,11 +2377,9 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.aarch64_32,
.amdgcn,
.amdil64,
.bpfel,
.bpfeb,
.hexagon,
.hsail64,
.loongarch64,
.m68k,
.mips,
@ -2449,11 +2390,9 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
.lanai,
.nvptx,
.nvptx64,
.r600,
.s390x,
.spir64,
.spirv64,
.renderscript64,
=> 8,
.aarch64,
@ -2537,15 +2476,9 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.xcore,
.dxil,
.loongarch32,
.tce,
.tcele,
.amdil,
.hsail,
.spir,
.spirv32,
.kalimba,
.shave,
.renderscript32,
.ve,
.spu_2,
.xtensa,
@ -2559,11 +2492,9 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.thumbeb,
.aarch64_32,
.amdgcn,
.amdil64,
.bpfel,
.bpfeb,
.hexagon,
.hsail64,
.x86,
.loongarch64,
.m68k,
@ -2575,11 +2506,9 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
.lanai,
.nvptx,
.nvptx64,
.r600,
.s390x,
.spir64,
.spirv64,
.renderscript64,
=> 8,
.aarch64,

10
src/Type.zig
View File

@ -1599,7 +1599,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
.mipsel,
.powerpc,
.powerpcle,
.r600,
.amdgcn,
.riscv32,
.sparc,
@ -1649,20 +1648,11 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
.csky,
.arc,
.m68k,
.tce,
.tcele,
.amdil,
.hsail,
.spir,
.kalimba,
.renderscript32,
.spirv,
.spirv32,
.shave,
.amdil64,
.hsail64,
.spir64,
.renderscript64,
.ve,
.spirv64,
.dxil,

10
src/Zcu.zig
View File

@ -3246,24 +3246,17 @@ pub fn atomicPtrAlignment(
.nvptx,
.powerpc,
.powerpcle,
.r600,
.riscv32,
.sparc,
.sparcel,
.tce,
.tcele,
.thumb,
.thumbeb,
.x86,
.xcore,
.amdil,
.hsail,
.spir,
.kalimba,
.lanai,
.shave,
.wasm32,
.renderscript32,
.csky,
.spirv32,
.dxil,
@ -3282,11 +3275,8 @@ pub fn atomicPtrAlignment(
.riscv64,
.sparc64,
.s390x,
.amdil64,
.hsail64,
.spir64,
.wasm64,
.renderscript64,
.ve,
.spirv64,
.loongarch64,

34
src/codegen/llvm.zig
View File

@ -65,7 +65,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.powerpcle => "powerpcle",
.powerpc64 => "powerpc64",
.powerpc64le => "powerpc64le",
.r600 => "r600",
.amdgcn => "amdgcn",
.riscv32 => "riscv32",
.riscv64 => "riscv64",
@ -73,8 +72,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.sparc64 => "sparc64",
.sparcel => "sparcel",
.s390x => "s390x",
.tce => "tce",
.tcele => "tcele",
.thumb => "thumb",
.thumbeb => "thumbeb",
.x86 => "i386",
@ -83,22 +80,15 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.xtensa => "xtensa",
.nvptx => "nvptx",
.nvptx64 => "nvptx64",
.amdil => "amdil",
.amdil64 => "amdil64",
.hsail => "hsail",
.hsail64 => "hsail64",
.spir => "spir",
.spir64 => "spir64",
.spirv => "spirv",
.spirv32 => "spirv32",
.spirv64 => "spirv64",
.kalimba => "kalimba",
.shave => "shave",
.lanai => "lanai",
.wasm32 => "wasm32",
.wasm64 => "wasm64",
.renderscript32 => "renderscript32",
.renderscript64 => "renderscript64",
.ve => "ve",
.spu_2 => return error.@"LLVM backend does not support SPU Mark II",
};
@ -111,7 +101,7 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
.freebsd => "freebsd",
.fuchsia => "fuchsia",
.linux => "linux",
.lv2 => "lv2",
.ps3 => "lv2",
.netbsd => "netbsd",
.openbsd => "openbsd",
.solaris, .illumos => "solaris",
@ -231,7 +221,7 @@ pub fn targetOs(os_tag: std.Target.Os.Tag) llvm.OSType {
.fuchsia => .Fuchsia,
.ios => .IOS,
.linux => .Linux,
.lv2 => .Lv2,
.ps3 => .Lv2,
.macos => .MacOSX,
.netbsd => .NetBSD,
.openbsd => .OpenBSD,
@ -289,7 +279,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
.powerpcle => .ppcle,
.powerpc64 => .ppc64,
.powerpc64le => .ppc64le,
.r600 => .r600,
.amdgcn => .amdgcn,
.riscv32 => .riscv32,
.riscv64 => .riscv64,
@ -297,8 +286,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
.sparc64 => .sparcv9, // In LLVM, sparc64 == sparcv9.
.sparcel => .sparcel,
.s390x => .systemz,
.tce => .tce,
.tcele => .tcele,
.thumb => .thumb,
.thumbeb => .thumbeb,
.x86 => .x86,
@ -307,22 +294,15 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
.xtensa => .xtensa,
.nvptx => .nvptx,
.nvptx64 => .nvptx64,
.amdil => .amdil,
.amdil64 => .amdil64,
.hsail => .hsail,
.hsail64 => .hsail64,
.spir => .spir,
.spir64 => .spir64,
.spirv => .spirv,
.spirv32 => .spirv32,
.spirv64 => .spirv64,
.kalimba => .kalimba,
.shave => .shave,
.lanai => .lanai,
.wasm32 => .wasm32,
.wasm64 => .wasm64,
.renderscript32 => .renderscript32,
.renderscript64 => .renderscript64,
.ve => .ve,
.spu_2 => .UnknownArch,
};
@ -12092,22 +12072,12 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
},
// LLVM backends that have no initialization functions.
.tce,
.tcele,
.r600,
.amdil,
.amdil64,
.hsail,
.hsail64,
.shave,
.spir,
.spir64,
.spirv,
.spirv32,
.spirv64,
.kalimba,
.renderscript32,
.renderscript64,
.dxil,
=> {},

10
src/target.zig
View File

@ -135,7 +135,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
.powerpcle,
.powerpc64,
.powerpc64le,
.r600,
.amdgcn,
.riscv32,
.riscv64,
@ -143,8 +142,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
.sparc64,
.sparcel,
.s390x,
.tce,
.tcele,
.thumb,
.thumbeb,
.x86,
@ -153,22 +150,15 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
.xtensa,
.nvptx,
.nvptx64,
.amdil,
.amdil64,
.hsail,
.hsail64,
.spir,
.spir64,
.spirv,
.spirv32,
.spirv64,
.kalimba,
.shave,
.lanai,
.wasm32,
.wasm64,
.renderscript32,
.renderscript64,
.ve,
=> true,

1
test/behavior/align.zig
View File

@ -94,7 +94,6 @@ test "alignment and size of structs with 128-bit fields" {
.mipsel,
.powerpc,
.powerpcle,
.r600,
.amdgcn,
.riscv32,
.sparc,

1
test/llvm_targets.zig
View File

@ -76,7 +76,6 @@ const targets = [_]std.Target.Query{
.{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .gnu },
.{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .musl },
.{ .cpu_arch = .powerpc64le, .os_tag = .linux, .abi = .none },
//.{ .cpu_arch = .r600, .os_tag = .mesa3d, .abi = .none },
.{ .cpu_arch = .riscv32, .os_tag = .freestanding, .abi = .none },
.{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .none },
.{ .cpu_arch = .riscv64, .os_tag = .freestanding, .abi = .none },