Commit Graph

3622 Commits

Author SHA1 Message Date
Jakub Konka
557268a448 stage2: augment stage2 test to test optional payload lowering 2022-01-01 14:29:31 +01:00
Marian Beermann
55709de185 stage1: fix @errorName null termination 2022-01-01 10:28:47 +02:00
Jakub Konka
c7f774803a stage2: implement loading-storing via pointer (in register)
* load address (pointer) to a stack variable in a register via
  `lea` instruction
* store value on the stack via a pointer stored in a register via
  `mov [reg], imm` instruction
* the lowerings naturally are handled automatically by Mir -> Isel
  layer
* add initial (without safety) implementation of `.optional_payload`
* add matching stage2 test cases
2021-12-31 18:10:28 +01:00
Andrew Kelley
4645ec89f7
Merge pull request #10455 from joachimschmidt557/stage2-arm
stage2 ARM: basic slice + basic struct support
2021-12-30 15:25:36 -05:00
drew
2f53406ad8
CBE; implement airLoad and airStore for arrays (#10452)
Effectively a small continuation of #10152

This allows the for.zig behavior tests to pass. Unfortunately to fully test everything I had to move a lot of behavior tests from array.zig; most of them now pass (sorry @rainbowbismuth!)

I'm also conflicted on how I store constants into arrays because it's kind of stupid; array's can't be re-initialized using the same syntax, so instead of initializing each element, a new array is made which is copied into the destination. This also required that renderValue can't emit string literals for byte arrays given that they need to always have an extra byte for the NULL terminator, meaning that strings are no longer grep-able in the output.
2021-12-30 15:19:12 -05:00
joachimschmidt557
726ee671be stage2 x86_64: add regression test for #7187 2021-12-30 15:12:38 -05:00
joachimschmidt557
69d03d3a29
stage2 ARM: implement struct_field_ptr and struct_field_val 2021-12-30 14:39:06 +01:00
Jakub Konka
b7e2235973 stage2: lower 1-byte and 2-byte values saved to stack
* fix handling of `ah`, `bh`, `ch`, and `dh` registers (which are
  actually used as aliases to `dil`, etc. registers). Currenly, we
  treat them as aliases only meaning when we encounter `ah` we make
  sure to set the REX.W to promote the instruction to 64bits and use
  `dil` register instead - otherwise we might have mismatch between
  registers used in different parts of the codegen. In the future,
  we can and should use `ah`, etc. as upper 8bit halves of 16bit
  registers `ax`, etc.
* fix bug in `airCmp` where `.cmp` MIR instruction shouldn't force
  type `Bool` but let the type of the original type propagate downwards
  - we need this to make an informed choice of the target register
  size and hence choose the right encoding down the line.
* implement lowering of 1-byte and 2-byte values to stack and add
  matching stage2 tests for x86_64 codegen
2021-12-29 22:06:38 +01:00
Andrew Kelley
be5130ec53 compiler_rt: move more functions to the stage2 section
also move more already-passing behavior tests to the passing section.
2021-12-29 00:39:25 -07:00
Andrew Kelley
efb7148a45 Sema: more union fixes
* `Module.Union.getLayout`: fixes to support components of the union
   being 0 bits.
 * Implement `@typeInfo` for unions.
 * Add missing calls to `resolveTypeFields`.
 * Fix explicitly-provided union tag types passing a `Zir.Inst.Ref`
   where an `Air.Inst.Ref` was expected. We don't have any type safety
   for this; these typess are aliases.
 * Fix explicitly-provided `union(enum)` tag Values allocated to the
   wrong arena.
2021-12-28 23:22:09 -07:00
Andrew Kelley
91619cdf57 Sema: implement calling a fn ptr via a union field
Also, ignore `packed` on unions because that will be removed from the
language.
2021-12-28 23:22:09 -07:00
Andrew Kelley
81a3910e44 Sema: improve union support
* reduce number of branches in zirCmpEq
 * implement equality comparison for enums and unions
 * fix coercion from union to its tag type resulting in the wrong type
 * fix method calls of unions
 * implement peer type resolution for unions, enums, and enum literals
 * fix union tag type memory in the wrong arena
2021-12-28 20:20:30 -07:00
joachimschmidt557
c0ae9647f9 stage2 ARM: implement slice_elem_val for types with size <= 4 2021-12-28 20:38:37 -05:00
Veikka Tuominen
4f4f0bc6f0 stage1: fix access of slice sentinel at comptime 2021-12-28 14:44:46 +02:00
Andrew Kelley
4b9b9e7257 stage2: LLVM backend: fix lowering of union constants
Comment from this commit reproduced here:

LLVM does not allow us to change the type of globals. So we must
create a new global with the correct type, copy all its attributes,
and then update all references to point to the new global,
delete the original, and rename the new one to the old one's name.
This is necessary because LLVM does not support const bitcasting
a struct with padding bytes, which is needed to lower a const union value
to LLVM, when a field other than the most-aligned is active. Instead,
we must lower to an unnamed struct, and pointer cast at usage sites
of the global. Such an unnamed struct is the cause of the global type
mismatch, because we don't have the LLVM type until the *value* is created,
whereas the global needs to be created based on the type alone, because
lowering the value may reference the global as a pointer.
2021-12-28 01:53:58 -07:00
Andrew Kelley
85d4c8620f Sema: implement array coercion 2021-12-27 22:06:23 -07:00
Andrew Kelley
6ed7850972 Sema: fix anytype parameters whose types require comptime 2021-12-27 19:39:28 -07:00
Andrew Kelley
fc1a5cd9e7 Sema: implement @tagName for enum literals 2021-12-27 18:10:24 -07:00
Andrew Kelley
9dd4fb4130 stage2: fix 0-bit function parameters
Before this commit, Zig would incorrectly emit `arg` AIR instructions
for parameters whose types were 0-bit.
2021-12-27 17:56:33 -07:00
Andrew Kelley
886df772f0 stage2: LLVM backend: fix const packed structs
When doing LLVM const bit shifting we must make sure the integer bit
sizes are wide enough or else LLVM gives us a poison result.
2021-12-27 16:59:26 -07:00
Matthew Hall
4266795743 stage2: make tests/behaviour/void.zig work with c backend
* fix initialisation of void* fields of structs (initialises to 0xaa.. rather than {})
* don't generate struct fields when the field type does not have codegen bits
* in airAlloc generate a void* literal if the element type does not have codegen bits
2021-12-27 14:42:25 -08:00
Andrew Kelley
70894d5c2f AstGen: fix loop result locations
The main problem was that the loop body was treated as an expression
that was one of the peer result values of a loop, when in reality the
loop body is noreturn and only the `break` operands are the result
values of loops.

This was solved by introducing an override that prevents rvalue() from
emitting a store to result location instruction for loop bodies.

An orthogonal change also included in this commit is switching
`elem_val` index expressions to using `coerced_ty` and doing the
coercion to `usize` inside `Sema`, resulting in smaller ZIR (since the
cast becomes implied).

I also changed the break operand expression to use `reachableExpr`,
introducing a new compile error for double break.

This makes a few more behavior tests pass for `while` and `for` loops.
2021-12-27 15:30:31 -07:00
Andrew Kelley
c8fb36b36c stage2: LLVM backend: implement @tagName for enums
Introduced a new AIR instruction: `tag_name`. Reasons to do this
instead of lowering it in Sema to a switch, function call, array
lookup, or if-else tower:
 * Sema is a bottleneck; do less work in Sema whenever possible.
 * If any optimization passes run, and the operand to becomes
   comptime-known, then it could change to have a comptime result
   value instead of lowering to a function or array or something which
   would then have to be garbage-collected.
 * Backends may want to choose to use a function and a switch branch,
   or they may want to use a different strategy.

Codegen for `@tagName` is implemented for the LLVM backend but not any
others yet.

Introduced some new `Type` tags:
 * `const_slice_u8_sentinel_0`
 * `manyptr_const_u8_sentinel_0`

The motivation for this was to make typeof() on the tag_name AIR
instruction non-allocating.

A bunch more enum tests are passing now.
2021-12-27 01:14:50 -07:00
Andrew Kelley
f41b9cdb6d Sema: fix enum tag type not initialized when 0 fields 2021-12-26 21:36:12 -07:00
Andrew Kelley
629a54c711 Sema: improve non-exhaustive enum support
* remove false positive "all prongs handled" compile error for
   non-exhaustive enums.
 * implement `@TypeInfo` for enums, except enums which have any
   declarations is still TODO.
 * `getBuiltin` uses nomespaceLookup/analyzeDeclVal rather than
   namespaceLookupRef/analyzeLoad. Avoids a detour through an
   unnecessary type, and adds a detour through a caching mechanism.
 * `Value.eql`: add missing code to handle enum comparisons for
   non-exhaustive enums. It works by converting the enum tags to numeric
   values and comparing those.
2021-12-26 21:07:16 -07:00
Andrew Kelley
5b171f446f stage2: initial implementation of packed structs
Layout algorithm: all `align(0)` fields are squished together as if they
were a single integer with a number of bits equal to `@bitSizeOf` each
field added together. Then the natural ABI alignment of that integer is
used for that pseudo-field.
2021-12-23 23:57:02 -07:00
Andrew Kelley
303bad9989 behavior tests: stage2 is not yet passing this test
Looks like I repeated the same mistake, which last time was addressed in
1e0addcf73.
2021-12-22 20:48:53 -07:00
Andrew Kelley
cc937369fb stage2: Type.hasCodeGenBits asserts structs and unions have fields
Previously, this function would return an incorrect result for structs
and unions which did not have their fields resolved yet.

This required introducing more logic in Sema to resolve types before
doing certain things such as creating an anonmyous Decl and emitting
function call AIR.

As a result a couple more struct tests pass.

Oh, and I implemented the language change to make sizeOf for pointers
always return pointer size bytes even if the element type is 0 bits.
2021-12-22 20:29:26 -07:00
Andrew Kelley
5d6380b38d
Merge pull request #10384 from joachimschmidt557/stage2-arm-optionals
stage2 ARM: basic implementation of optionals and error unions
2021-12-21 21:06:08 -08:00
Andrew Kelley
88be5bd81d Sema: fix empty struct init
* Extract common logic between `zirStructInitEmpty` and
   `zirStructInit`.
 * `resolveTypeFields` additionally sets status to `have_layout` if the
   total number of fields is 0.
2021-12-21 20:34:27 -07:00
joachimschmidt557
c55f58d8bb
stage2 ARM: implement is_err and is_non_err for simple error unions 2021-12-21 23:13:30 +01:00
joachimschmidt557
edcebe7013
stage2 ARM: implement is_null and is_non_null for ptr-like optionals 2021-12-21 23:13:30 +01:00
Andrew Kelley
8df540aeef
Merge pull request #10370 from Snektron/stage2-inferred-error-sets-2
stage2: Make page_allocator work
2021-12-21 11:28:40 -08:00
ominitay
7e16bb36d8 Change ArgIterator.next() return type
Changes the return type of `ArgIterator.next()` from
`?(NextError![:0]u8)` to `NextError!?[:0]u8`.
2021-12-21 11:15:33 -08:00
Robin Voetter
e106e18d96 stage2: @shlWithOverflow 2021-12-21 01:47:27 +01:00
Robin Voetter
964dbeb826 stage2: @subWithOverflow 2021-12-21 01:41:51 +01:00
Robin Voetter
c47ed0c912 stage2: @mulWithOverflow 2021-12-21 01:41:51 +01:00
Robin Voetter
f3d635b668 stage2: @addWithOverflow 2021-12-21 01:41:51 +01:00
Isaac Freund
9f9f215305
stage1, stage2: rename c_void to anyopaque (#10316)
zig fmt now replaces c_void with anyopaque to make updating
code easy.
2021-12-19 00:24:45 -05:00
joachimschmidt557
9892684d35 stage2 ARM: spill insts currently in compare flags if necessary 2021-12-18 15:23:25 -08:00
Andrew Kelley
c8af00c66e glibc: fix inconsistency of powerpc ABI mapping
See the commit message of 5b6d26e97b for
an explanation. This is the same thing but for powerpc instead of mips.
2021-12-16 03:01:13 -07:00
Andrew Kelley
5b6d26e97b glibc: fix inconsistency of mips ABI mapping
Before this commit, glibc headers did the following mapping:

 * (zig) mipsel-linux-gnu      => (glibc) mipsel-linux-gnu
 * (zig) mipsel-linux-gnu-soft => (glibc) (none)
 * (zig) mips-linux-gnu        => (glibc) mips-linux-gnu
 * (zig) mips-linux-gnu-soft   => (glibc) (none)

While the glibc ABI stubs used the (zig) gnueabi and gnueabihf ABIs,
and the stage2 available_libcs array listed:

 * (zig) mipsel-linux-gnu
 * (zig) mips-linux-gnu

The problem is the mismatch between the ABI component of the headers and
the stubs.

This commit makes the following clarifications:

 * (zig) mips-linux-gnueabi     means soft-float
 * (zig) mipsel-linux-gnueabi   means soft-float
 * (zig) mips-linux-gnueabihf   means hard-float
 * (zig) mipsel-linux-gnueabihf means hard-float

Consequently, the glibc headers now do this mapping:

 * (zig) mips-linux-gnueabihf   => (glibc) mips-linux-gnu
 * (zig) mipsel-linux-gnueabihf => (glibc) mipsel-linux-gnu
 * (zig) mips-linux-gnueabi     => (glibc) mips-linux-gnu-soft
 * (zig) mipsel-linux-gnueabi   => (glibc) mipsel-linux-gnu-soft

The glibc ABI stubs are unchanged, and the stage2 available_libcs
array's 2 entries are modified and it gains 2 more:

 * (zig) mipsel-linux-gnueabi
 * (zig) mipsel-linux-gnueabihf
 * (zig) mips-linux-gnueabi
 * (zig) mips-linux-gnueabihf

Now everything is consistent. Zig no longer recognizes a `mips-linux-gnu`
triple; one must use `mips-linux-gnueabi` (soft float) or
`mips-linux-gnueabihf` (hard float).
2021-12-15 19:09:50 -07:00
Andrew Kelley
19ca2415f2 update glibc start files to 2.34
This commit introduces tools/update_glibc.zig to update the start files
for next time.

Some notable changes in recent glibc:

 * abi-note.S has been changed to abi-note.c but we resist the change to
   keep it easier to compile the start files.
 * elf-init.c has been deleted upstream. Further testing should be done
   to verify that binaries against glibc omitting elf-init.c still run
   properly on oldel glibc linux systems.

Closes #4926
2021-12-15 14:30:03 -07:00
Jakub Konka
4b5f8bca5e stage2: clean up tests
* move darwin tests into respective architecture test files: `x86_64`
and `aarch64`
* run majority of `x86_64` tests on macOS
2021-12-15 17:28:48 +01:00
Jakub Konka
bd926e5ea0 add standalone tests for the new linker bug fixes
This is just a temp addition until I figure out how to tweak
the stage2 test harness to add the ability to test the linker too.
2021-12-15 10:31:29 +01:00
Andrew Kelley
ff93486d0c test: remove testing for tools/update_glibc.zig
Fixes test failures introduced by
5da013e39c.
2021-12-14 23:41:35 -07:00
Isaac Freund
7bb6393b59
stage1: implement @prefetch() builtin 2021-12-11 00:29:31 +01:00
Andrew Kelley
8031783539 stage1: fix regression of shift by negative value error
The previous commit (38b2d62092) regressed
the compile error test case for when doing saturating shift left of a
comptime-known negative RHS.

This commit additionally fixes the error for regular shifts in addition
to saturating shifts.
2021-12-08 19:09:37 -07:00
Andrew Kelley
38b2d62092 stage1: saturating shl operates using LHS type
Saturating shift left (`<<|`) previously used the `ir_analyze_bin_op_math`
codepath rather than the `ir_analyze_bit_shift` codepath, leading to it
doing peer type resolution (incorrect) instead of using the LHS type as
the number of bits to do the saturating against.

This required implementing SIMD vector support for `@truncate`.

Additionall, this commit adds a compile error for saturating shift left
on a comptime_int.

stage2 does not pass these new behavior tests yet.

closes #10298
2021-12-08 15:25:31 -07:00
Luuk de Gram
9e03cf9489 wasm: Initial behavior tests succeeding
- Correctly load slice value on stack
- Implement WrapErrorUnionErr and payload
- Implement trunc, fix sliceLen and write undefined
- Implement slice as return type and argument

Note: This also fixes a memory leak for inferred error sets, and for usingnamespace
2021-12-05 12:19:01 -08:00