Commit Graph

15741 Commits

Author SHA1 Message Date
Andrew Kelley
c715d512cb CI: additionally run stage2 behavior tests with -ofmt=c 2021-11-09 16:12:57 -07:00
Žiga Željko
b24e475717 stage1: fix type mapping for integers and c_longdouble on nvptx 2021-11-09 16:43:03 -05:00
Andrew Kelley
d2cdfb9490 stage2: add 4 new linker flags for WebAssembly
--import-memory          import memory from the environment
--initial-memory=[bytes] initial size of the linear memory
--max-memory=[bytes]     maximum size of the linear memory
--global-base=[addr]     where to start to place global data

See #8633
2021-11-09 14:29:20 -07:00
Silver
9bb7ff68cc std: Publicize Allocator.reallocBytes
This is useful when dealing with runtime-known alignments, eg. interfacing
with C code that accepts custom allocation callbacks.

Closes #9394
2021-11-09 13:41:38 -05:00
Martin Hafskjold Thoresen
e04ab39036 Cmake: Specify LLVM versions
Systems with multiple LLVM toolchains installed (e.g. one globally and one
in $HOME/local) would get confused and fail to compile.  Being explicit
about the version required will force CMake to find the right version of LLVM.
2021-11-09 13:39:32 -05:00
Gregory Anders
3534f8a3ed std: ppoll: cast number of fds to nfds_t
On some systems, the type of the length of a slice is different from the
nfds_t type, so cast the slice length to nfds_t. This is already done in
poll, so just copy that implementation for ppoll.
2021-11-09 13:36:36 -05:00
Vincent Rischmann
082072bd4f os/linux/io_uring: implement statx 2021-11-09 13:35:17 -05:00
Andrew Kelley
4d75382452 tools/gen_stubs.zig: better error message on invalid input 2021-11-08 15:31:14 -07:00
Michael Dusan
a7d215759e ci: fully activate ci.ziglang.org linux
- disable azure/linux
- split probe/build/test steps for log clarity
- add package step; enabled only when master/pull
- add on-master-success pipeline; enabled only when master/pull
2021-11-08 13:45:03 -05:00
Jakub Konka
3c7310f8cc stage2 x86_64: add MIR->Isel lowering step for x86_64
* incorporate Andrew's MIR draft as Mir.zig
* add skeleton for Emit.zig module - Emit will lower MIR into
  machine code or textual ASM.
* implement push
* implement ret
* implement mov r/m, r
* implement sub r/m imm and sub r/m, r
* put encoding common ops together - some ops share impl such as
  MOV and cmp so put them together and vary the actual opcode
  with modRM ext only.
* implement pop
* implement movabs - movabs being a special-case of mov not
  handled by general mov MIR instruction due to requirement to
  handle 64bit immediates.
* store imm64 as a struct `Imm64{ msb: u32, lsb: u32 }` in extra data
  for use with for instance movabs inst
* implement more mov variations
* implement adc
* implement add
* implement sub
* implement xor
* implement and
* implement or
* implement sbb
* implement cmp
* implement lea - lea doesn't follow the scheme as other inst above. Similarly, I
  think bit shifts and rotates should be put in a separate basket too.
* implement adc_scale_src
* implement add_scale_src
* implement sub_scale_src
* implement xor_scale_src
* implement and_scale_src
* implement or_scale_src
* implement sbb_scale_src
* implement cmp_scale_src
* implement adc_scale_dst
* implement add_scale_dst
* implement sub_scale_dst
* implement xor_scale_dst
* implement and_scale_dst
* implement or_scale_dst
* implement sbb_scale_dst
* implement cmp_scale_dst
* implement mov_scale_src
* implement mov_scale_dst
* implement adc_scale_imm
* implement add_scale_imm
* implement sub_scale_imm
* implement xor_scale_imm
* implement and_scale_imm
* implement or_scale_imm
* implement sbb_scale_imm
* implement cmp_scale_imm
* port bin math to MIR
* backpatch stack size into prev MIR inst
* implement Function.gen() (minus dbg info)
* implement jmp/call [imm] - we can now call functions using indirect absolute
  addressing, or via registers.
* port airRet to use MIR
* port airLoop to use MIR
* patch up performReloc to use inst indices
* implement conditional jumps (without relocs)
* implement set byte on condition
* implement basic lea r64, [rip + imm]
* implement calling externs
* implement callq in PIE
* implement lea RIP in PIE context
* remove all refs to Encoder from CodeGen
* implement basic imul ops
* pass all Linux tests!
* enable most of dbg info gen
* generate arg dbg info in Emit
2021-11-08 13:27:49 -05:00
Andrew Kelley
4acd8920d8 ci: don't print env because there will be secrets there 2021-11-08 11:27:02 -07:00
Frank Denis
bd8b94bd0e crypto/edwards25519: correctly flip the Y sign in the H2C operation
No security implications, but the current hash-to-curve standard
defines the sign of the Y coordinate to be negative if `gx1`
is a square, positive otherwise.

We were doing it the other way round.
2021-11-08 14:55:27 +01:00
joachimschmidt557
6b5e403e5d stage2 ARM: move codegen to separate file
This also removes i386 codegen code, which was unused and untested
2021-11-07 21:20:58 +01:00
joachimschmidt557
0fb26b0369 stage2 RISCV64: introduce MIR 2021-11-05 15:30:28 -04:00
LemonBoy
2551946a51 std: Fix path resolution on Windows
GetCurrentDirectory returns a path with a trailing slash iff the cwd is
a root directory, making the code in `resolveWindows` return an invalid
path with two consecutive slashes.

Closes #10093
2021-11-04 21:05:14 -04:00
Ryan Liptak
e97feb96e4 Replace ArrayList.init/ensureTotalCapacity pairs with initCapacity
Because ArrayList.initCapacity uses 'precise' capacity allocation, this should save memory on average, and definitely will save memory in cases where ArrayList is used where a regular allocated slice could have also be used.
2021-11-04 14:54:25 -04:00
LemonBoy
d03e9d0b83 compiler-rt: Fix f16 API declarations to be consistent
LLVM and compiler-rt must agree on how the parameters are passed, it
turns out that in LLVM13 something changed and broke the test case for
AArch64 systems.

It has nothing to do with fma at all.

Closes #9900
2021-11-04 14:30:35 -04:00
Daniele Cocca
77ffffc7cc
Add more entries to the list of stage1+stage2+CBE passing tests (#10094)
* CBE: mark call.zig tests as passing

* CBE: mark enum.zig tests as passing

* CBE: mark defer.zig tests as passing

* CBE: mark hasdecl.zig tests as passing

* CBE: mark hasfield.zig tests as passing

* CBE: mark ptrcast.zig tests as passing

* CBE: mark bitcast.zig tests as passing

* CBE: mark pub_enum.zig tests as passing

* CBE: mark underscore.zig tests as passing

* CBE: mark usingnamespace.zig tests as passing

* CBE: mark bugs/655.zig tests as passing

* CBE: mark bugs/679.zig tests as passing

* CBE: mark bugs/704.zig tests as passing

* CBE: mark bugs/1486.zig tests as passing

* CBE: mark bugs/2346.zig tests as passing

* CBE: mark bugs/2889.zig tests as passing

* CBE: mark bugs/4560.zig tests as passing

* CBE: mark bugs/4769_a.zig tests as passing

* CBE: mark bugs/4769_b.zig tests as passing

* CBE: mark bugs/6850.zig tests as passing
2021-11-04 14:24:46 -04:00
Andrew Kelley
a55dc4a3bc
Merge pull request #10079 from mattbork/astgen-temp-allocs
stage2: Reduce temporary allocations in AstGen
2021-11-03 18:30:08 -04:00
Andrew Kelley
08dc840247
Merge pull request #10088 from ziglang/std-os-perf
std: add Linux perf syscall bits
2021-11-02 14:52:54 -04:00
joachimschmidt557
5ebdc8c46c stage2 RISCV64: move codegen to separate file 2021-11-02 13:05:01 -04:00
Emily Bellows
674932e503 C backend: implement ?void, and other zero sized types 2021-11-02 12:45:29 -04:00
Michael Dusan
325bae7fc0
ci: add new linux pipeline
A new zsf-hosted server is being brought online.
This should be enough for linux build, test and packaging pipeline.

Currently this pipeline does not not post artifacts.
2021-11-02 10:44:01 -04:00
Andrew Kelley
a78e61acf9 std: expose rusage constants under rusage namespace 2021-11-01 15:55:22 -07:00
Andrew Kelley
63f4778827 std: add Linux perf syscall bits
Example usage:

```zig
const std = @import("std");
const PERF = std.os.linux.PERF;
const assert = std.debug.assert;

test "perf" {
    var attr: std.os.linux.perf_event_attr = .{
        .type = PERF.TYPE.HARDWARE,
        .config = @enumToInt(PERF.COUNT.HW.INSTRUCTIONS),
        .flags = .{
            .disabled = true,
            .exclude_kernel = true,
            .exclude_hv = true,
        },
    };
    const fd = try std.os.perf_event_open(&attr, 0, -1, -1, PERF.FLAG.FD_CLOEXEC);
    defer std.os.close(fd);

    _ = std.os.linux.ioctl(fd, PERF.EVENT_IOC.RESET, 0);
    _ = std.os.linux.ioctl(fd, PERF.EVENT_IOC.ENABLE, 0);

    long();

    _ = std.os.linux.ioctl(fd, PERF.EVENT_IOC.DISABLE, 0);

    var result: usize = 0;
    assert((try std.os.read(fd, std.mem.asBytes(&result))) == @sizeOf(usize));

    std.debug.print("instruction count: {d}\n", .{result});
}

fn long() void {
    var i: usize = 0;
    while (i < 100000) : (i += 1) {}
}
```
2021-11-01 14:45:05 -07:00
Ryan Liptak
70ef9bc75c Fix ensureTotalCapacity calls that should be ensureUnusedCapacity calls
If these functions are called more than once, then the array list would no longer be guaranteed to have enough capacity during the appendAssumeCapacity calls. With ensureUnusedCapacity, they will always be guaranteed to have enough capacity regardless of how many times the function is called.
2021-11-01 15:08:41 -04:00
Andrew Kelley
77eefebe65
Merge pull request #10077 from squeek502/arraylist-capacity
std.ArrayList: add ensureTotalCapacityPrecise and update doc comments
2021-11-01 14:28:27 -04:00
joachimschmidt557
002fbb0af0 stage2 AArch64: implement unconditional branches 2021-11-01 14:23:38 -04:00
Lee Cannon
f951bf8aeb correct bug with omit frame pointer logic 2021-11-01 14:14:07 -04:00
Matthew Borkowski
01842a6ead astgen.zig: avoid temporary allocations by sharing the instructions ArrayList between a GenZir and its sub-blocks wherever their use of it is strictly nested 2021-11-01 05:42:39 -04:00
Matthew Borkowski
65c27e8e66 astgen.zig: delay adding closure_capture instructions to preserve GenZir nesting. Only containers create Namespaces, so the declaring_gz is always the GenZir passed to containerDecl, and containerDecl will always add exactly one instruction (an extended *_decl) to that GenZir. Thus, closure_capture instructions are always lined up immediately after a container decl instruction, so rather than adding them at the point of first mention, where we're nested arbitrarily deep, simply walk through the Namespace captures hash map at the end of each containerDecl branch and add them then. 2021-11-01 05:42:32 -04:00
Matthew Borkowski
92d2aa1b48 astgen.zig: use scratch buffer for temporary allocations in switchExpr and WipMembers 2021-11-01 05:42:25 -04:00
Matthew Borkowski
5760ba949f astgen.zig: simplify container functions by pulling out common processing of members 2021-11-01 05:42:19 -04:00
Matthew Borkowski
e712f87a66 astgen.zig: replace WipDecls with WipMembers, use one allocation to collect container decls, fields, and bits, instead of up to four 2021-11-01 05:41:37 -04:00
Matthew Borkowski
f0260555d6 astgen.zig: simplify switchExpr and collect payload in one ArrayList instead of three 2021-11-01 05:28:03 -04:00
Matthew Borkowski
a0bf620fbf astgen.zig: avoid unnecessary allocation in identifier for @"" syntax 2021-11-01 05:27:52 -04:00
Matthew Borkowski
2561be2e34 astgen.zig: avoid temporary allocations in arrayInit* and structInit*, callExpr, errorSetDecl, typeOf, and builtinCall's compile_log branch 2021-11-01 05:09:19 -04:00
Ryan Liptak
a343758141 Update ensureTotalCapacity to ensureTotalCapacityPrecise where it makes sense
These calls are all late-initialization of ArrayList's that were initialized outside the current scope. This allows us to still get the potential memory-saving benefits of the 'precision' of initCapacity.
2021-11-01 00:57:33 -07:00
Ryan Liptak
f49d42729a std.ArrayList: add ensureTotalCapacityPrecise and update doc comments
initCapacity did and still does use the ensureTotalCapacityPrecise logic because the initial capacity of an ArrayList is not important in terms of how it grows, so allocating a more exact slice up-front allows for saving memory when the array list never exceeds that initial allocation size. There are use cases where this precise capacity is useful outside of the `init` function, though, like in instances where the user does not call the `init` function themselves but otherwise knows that an ArrayList is empty so calling `ensureTotalCapacityPrecise` can give the same memory savings that `initCapacity` would have.

Closes #9775
2021-11-01 00:57:24 -07:00
Lee Cannon
83dcfd6205 optimize AstGen.callExpr 2021-10-31 18:11:53 -04:00
Andrew Kelley
8346e011c9
Merge pull request #10068 from leecannon/tracy_improvements
stage2: tracy integration improvements
2021-10-31 17:55:29 -04:00
Jakub Konka
91d93b6395 stage2: move x86_64 codegen to arch/x86_64/CodeGen.zig
This mimics steps taken for aarch64 and preps stage2 x86_64
for a rewrite introducing MIR for this arch.
2021-10-31 17:32:39 -04:00
Jakub Konka
c452d10953
Merge pull request #10066 from joachimschmidt557/stage2-aarch64-mir
stage2 AArch64: introduce MIR
2021-10-31 18:54:19 +01:00
Lee Cannon
2d1efba8c5 watch marks a new frame on every recompilation 2021-10-31 14:35:36 +00:00
Lee Cannon
8a3a6a98aa use named frames to mark the stages of compilation 2021-10-31 14:29:49 +00:00
Lee Cannon
49d8723408 add functionality to trace allocations 2021-10-31 14:16:59 +00:00
Lee Cannon
10c9fa0e08 make tracy.zig more feature complete 2021-10-31 14:12:36 +00:00
joachimschmidt557
8a55e6b6c4
stage2 AArch64: introduce Emit.fail for handling errors in MIR emit 2021-10-31 14:27:05 +01:00
joachimschmidt557
0bdb367ee4
stage2 AArch64: implement emit debug line info 2021-10-31 12:32:11 +01:00
joachimschmidt557
9471e3da35
stage2 AArch64 Emit: implement call_extern and load_memory 2021-10-31 12:32:07 +01:00