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5bd464e386
From my very cursory reading, it seems that the register manager doesn't distinguish between registers that are physically the same but have different sizes. In that case, this means that during codegen, we can't rely on `reg.size()` when determining the width of the operations we have to perform. Instead, we must use some form of `ty.abiSize(self.target.*)` to determine the size of the type we're operating with. If this size is 64 bits, then we should enable 64-bit operation. This fixed a bug in the codegen for spilling instructions, which was overwriting the previous stack entry with zeroes. See the modified test case in this commit. |
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| .. | ||
| src | ||
| stage1 | ||
| stage2 | ||
| standalone | ||
| assemble_and_link.zig | ||
| cli.zig | ||
| compare_output.zig | ||
| compile_errors.zig | ||
| gen_h.zig | ||
| run_translated_c.zig | ||
| runtime_safety.zig | ||
| stack_traces.zig | ||
| standalone.zig | ||
| tests.zig | ||
| translate_c.zig | ||