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56 lines
1.9 KiB
C
Vendored
56 lines
1.9 KiB
C
Vendored
/*===---- prfchwintrin.h - PREFETCHW intrinsic -----------------------------===
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*
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*===-----------------------------------------------------------------------===
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*/
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#if !defined(__X86INTRIN_H) && !defined(_MM3DNOW_H_INCLUDED)
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#error "Never use <prfchwintrin.h> directly; include <x86intrin.h> or <mm3dnow.h> instead."
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#endif
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#ifndef __PRFCHWINTRIN_H
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#define __PRFCHWINTRIN_H
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/// Loads a memory sequence containing the specified memory address into
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/// all data cache levels. The cache-coherency state is set to exclusive.
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/// Data can be read from and written to the cache line without additional
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/// delay.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the \c PREFETCHT0 instruction.
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///
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/// \param __P
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/// A pointer specifying the memory address to be prefetched.
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static __inline__ void __attribute__((__always_inline__, __nodebug__))
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_m_prefetch(void *__P)
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{
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__builtin_prefetch (__P, 0, 3 /* _MM_HINT_T0 */);
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}
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/// Loads a memory sequence containing the specified memory address into
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/// the L1 data cache and sets the cache-coherency to modified. This
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/// provides a hint to the processor that the cache line will be modified.
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/// It is intended for use when the cache line will be written to shortly
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/// after the prefetch is performed.
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///
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/// Note that the effect of this intrinsic is dependent on the processor
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/// implementation.
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///
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/// \headerfile <x86intrin.h>
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///
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/// This intrinsic corresponds to the \c PREFETCHW instruction.
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///
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/// \param __P
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/// A pointer specifying the memory address to be prefetched.
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static __inline__ void __attribute__((__always_inline__, __nodebug__))
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_m_prefetchw(void *__P)
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{
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__builtin_prefetch (__P, 1, 3 /* _MM_HINT_T0 */);
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}
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#endif /* __PRFCHWINTRIN_H */
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