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113 lines
4.6 KiB
C++
Vendored
113 lines
4.6 KiB
C++
Vendored
/*===---- cuda_builtin_vars.h - CUDA built-in variables ---------------------===
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*
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* Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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* See https://llvm.org/LICENSE.txt for license information.
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* SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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*
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*===-----------------------------------------------------------------------===
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*/
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#ifndef __CUDA_BUILTIN_VARS_H
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#define __CUDA_BUILTIN_VARS_H
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// Forward declares from vector_types.h.
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struct uint3;
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struct dim3;
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// The file implements built-in CUDA variables using __declspec(property).
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// https://msdn.microsoft.com/en-us/library/yhfk0thd.aspx
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// All read accesses of built-in variable fields get converted into calls to a
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// getter function which in turn calls the appropriate builtin to fetch the
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// value.
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//
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// Example:
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// int x = threadIdx.x;
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// IR output:
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// %0 = call i32 @llvm.nvvm.read.ptx.sreg.tid.x() #3
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// PTX output:
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// mov.u32 %r2, %tid.x;
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#define __CUDA_DEVICE_BUILTIN(FIELD, INTRINSIC) \
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__declspec(property(get = __fetch_builtin_##FIELD)) unsigned int FIELD; \
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static inline __attribute__((always_inline)) \
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__attribute__((device)) unsigned int __fetch_builtin_##FIELD(void) { \
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return INTRINSIC; \
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}
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#if __cplusplus >= 201103L
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#define __DELETE =delete
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#else
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#define __DELETE
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#endif
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// Make sure nobody can create instances of the special variable types. nvcc
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// also disallows taking address of special variables, so we disable address-of
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// operator as well.
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#define __CUDA_DISALLOW_BUILTINVAR_ACCESS(TypeName) \
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__attribute__((device)) TypeName() __DELETE; \
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__attribute__((device)) TypeName(const TypeName &) __DELETE; \
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__attribute__((device)) void operator=(const TypeName &) const __DELETE; \
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__attribute__((device)) TypeName *operator&() const __DELETE
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struct __cuda_builtin_threadIdx_t {
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__CUDA_DEVICE_BUILTIN(x,__nvvm_read_ptx_sreg_tid_x());
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__CUDA_DEVICE_BUILTIN(y,__nvvm_read_ptx_sreg_tid_y());
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__CUDA_DEVICE_BUILTIN(z,__nvvm_read_ptx_sreg_tid_z());
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// threadIdx should be convertible to uint3 (in fact in nvcc, it *is* a
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// uint3). This function is defined after we pull in vector_types.h.
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__attribute__((device)) operator uint3() const;
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private:
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__CUDA_DISALLOW_BUILTINVAR_ACCESS(__cuda_builtin_threadIdx_t);
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};
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struct __cuda_builtin_blockIdx_t {
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__CUDA_DEVICE_BUILTIN(x,__nvvm_read_ptx_sreg_ctaid_x());
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__CUDA_DEVICE_BUILTIN(y,__nvvm_read_ptx_sreg_ctaid_y());
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__CUDA_DEVICE_BUILTIN(z,__nvvm_read_ptx_sreg_ctaid_z());
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// blockIdx should be convertible to uint3 (in fact in nvcc, it *is* a
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// uint3). This function is defined after we pull in vector_types.h.
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__attribute__((device)) operator uint3() const;
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private:
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__CUDA_DISALLOW_BUILTINVAR_ACCESS(__cuda_builtin_blockIdx_t);
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};
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struct __cuda_builtin_blockDim_t {
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__CUDA_DEVICE_BUILTIN(x,__nvvm_read_ptx_sreg_ntid_x());
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__CUDA_DEVICE_BUILTIN(y,__nvvm_read_ptx_sreg_ntid_y());
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__CUDA_DEVICE_BUILTIN(z,__nvvm_read_ptx_sreg_ntid_z());
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// blockDim should be convertible to dim3 (in fact in nvcc, it *is* a
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// dim3). This function is defined after we pull in vector_types.h.
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__attribute__((device)) operator dim3() const;
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private:
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__CUDA_DISALLOW_BUILTINVAR_ACCESS(__cuda_builtin_blockDim_t);
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};
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struct __cuda_builtin_gridDim_t {
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__CUDA_DEVICE_BUILTIN(x,__nvvm_read_ptx_sreg_nctaid_x());
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__CUDA_DEVICE_BUILTIN(y,__nvvm_read_ptx_sreg_nctaid_y());
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__CUDA_DEVICE_BUILTIN(z,__nvvm_read_ptx_sreg_nctaid_z());
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// gridDim should be convertible to dim3 (in fact in nvcc, it *is* a
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// dim3). This function is defined after we pull in vector_types.h.
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__attribute__((device)) operator dim3() const;
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private:
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__CUDA_DISALLOW_BUILTINVAR_ACCESS(__cuda_builtin_gridDim_t);
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};
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#define __CUDA_BUILTIN_VAR \
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extern const __attribute__((device)) __attribute__((weak))
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__CUDA_BUILTIN_VAR __cuda_builtin_threadIdx_t threadIdx;
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__CUDA_BUILTIN_VAR __cuda_builtin_blockIdx_t blockIdx;
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__CUDA_BUILTIN_VAR __cuda_builtin_blockDim_t blockDim;
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__CUDA_BUILTIN_VAR __cuda_builtin_gridDim_t gridDim;
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// warpSize should translate to read of %WARP_SZ but there's currently no
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// builtin to do so. According to PTX v4.2 docs 'to date, all target
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// architectures have a WARP_SZ value of 32'.
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__attribute__((device)) const int warpSize = 32;
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#undef __CUDA_DEVICE_BUILTIN
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#undef __CUDA_BUILTIN_VAR
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#undef __CUDA_DISALLOW_BUILTINVAR_ACCESS
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#endif /* __CUDA_BUILTIN_VARS_H */
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