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locore.S: stash boot arguments in saved registers

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Switch the boot argument registers to the unused s3 and s4. This ensures
the values will not be clobbered by SBI or function calls; they are
consumed late in the assembly routine.

Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D47457
This commit is contained in:
Mitchell Horne 2024-11-21 14:12:23 -04:00
parent ccbe9a9f73
commit c7fa232e9b
1 changed files with 15 additions and 9 deletions
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24
sys/riscv/riscv/locore.S
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@ -83,8 +83,12 @@ _alt_start:
lla t0, boot_hart
sw a0, 0(t0)
/* Load zero as modulep */
mv a0, zero
/*
* Stash the DTB pointer in the callee-saved register s4, and zero s3
* to indicate that we have no loader metadata.
*/
mv s4, a1
mv s3, zero
j pagetables
/*
@ -104,10 +108,12 @@ _start:
.option pop
/*
* Zero a1 to indicate that we have no DTB pointer. It is already
* included in the loader(8) metadata.
* Stash modulep in the callee-saved register s3, and zero s4 to
* indicate that we have no DTB pointer. It is already included in the
* loader(8) metadata.
*/
mv a1, zero
mv s3, a0
mv s4, zero
/*
* Set up page tables: Our goal is to enable virtual memory, doing the
@ -128,8 +134,8 @@ _start:
* here and will conditionally enable Sv48 (or higher) later.
*
* We arrive here with:
* a0 - modulep or zero
* a1 - zero or dtbp
* s3 - modulep or zero
* s4 - zero or dtbp
*/
pagetables:
/* Get the kernel's load address (kernstart) in s9 */
@ -244,8 +250,8 @@ va:
la t0, initstack
sd t0, RISCV_BOOTPARAMS_KERN_STACK(sp)
sd a1, RISCV_BOOTPARAMS_DTBP_PHYS(sp)
sd a0, RISCV_BOOTPARAMS_MODULEP(sp)
sd s4, RISCV_BOOTPARAMS_DTBP_PHYS(sp)
sd s3, RISCV_BOOTPARAMS_MODULEP(sp)
mv a0, sp
call _C_LABEL(initriscv) /* Off we go */