Mitchell Horne e9fa399180 riscv: T-HEAD early locore workaround ... The T-HEAD custom PTE bits are defined in such a way that the default/normal memory type is non-zero value. This _unthoughtful_ choice means that, unlike the Svpbmt and non-Svpbmt cases, this field cannot be left bare in our bootstrap PTEs, or the hardware will fail to proceed far enough in boot (cache strangeness). On the other hand, we cannot unconditionally apply the PTE_THEAD_MA_NONE attributes, as this is not compatible with spec-compliant RISC-V hardware, and will result in a fatal exception. Therefore, in order to handle this errata, we are forced to perform a check of the CPU type at the first moment possible. Do so, and fix up the PTEs with the correct memory attribute bits in the T-HEAD case. Sponsored by: The FreeBSD Foundation Differential Revision: https://reviews.freebsd.org/D47458		2024-11-25 17:08:04 -04:00
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allwinner	aw_syscon: enable for Allwinner D1 (riscv)	2024-11-16 15:04:04 -04:00
conf	riscv: Allwinner D1 clock and reset driver	2024-11-16 15:04:04 -04:00
include	riscv: T-HEAD early locore workaround	2024-11-25 17:08:04 -04:00
riscv	riscv: T-HEAD early locore workaround	2024-11-25 17:08:04 -04:00
sifive	Use bus_delayed_attach_children instead of its inline implementation	2024-10-21 10:24:39 -04:00
starfive	jh7110: Add StarFive JH7110 clock/reset generator drivers	2024-05-07 13:07:36 -03:00
thead	riscv: T-HEAD PBMT support	2024-11-25 17:08:04 -04:00
vmm	riscv: Add support for building vmm as a kernel module	2024-11-13 14:15:07 +00:00