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95b1c4df78
sorry for the huge firehose on this commit, it would be too tedious
to do file by file
r201881 | imp | 2010-01-08 20:08:22 -0700 (Fri, 08 Jan 2010) | 3 lines
Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the
BSP. Provide a missing prototype.
r201880 | neel | 2010-01-08 19:17:14 -0700 (Fri, 08 Jan 2010) | 7 lines
Compute the target of the jump in the 'J' and 'JAL' instructions
correctly. The 256MB segment is formed by taking the top 4 bits
of the address of the instruction in the "branch delay" slot
as opposed to the 'J' or 'JAL' instruction itself.
r201845 | imp | 2010-01-08 15:48:21 -0700 (Fri, 08 Jan 2010) | 2 lines
Centralize initialization of pcpu, and set curthread early...
r201770 | neel | 2010-01-07 22:53:11 -0700 (Thu, 07 Jan 2010) | 4 lines
Add a DDB command "show pcb" to dump out the contents of a thread's PCB.
r201631 | neel | 2010-01-05 23:42:08 -0700 (Tue, 05 Jan 2010) | 5 lines
Remove all CFE-specific code from locore.S. The CFE entrypoint initialization
is now done in platform-specific code.
r201563 | neel | 2010-01-04 23:58:54 -0700 (Mon, 04 Jan 2010) | 6 lines
This change increases the size of the kernel stack for thread0 from
PAGE_SIZE to (2 * PAGE_SIZE). It depends on the memory allocated by
pmap_steal_memory() being aligned to a PAGE_SIZE boundary.
r200656 | imp | 2009-12-17 16:55:49 -0700 (Thu, 17 Dec 2009) | 7 lines
Place holder ptrace mips module. Not entirely sure what's required
here yet, so I've not connected it to the build. I think that we'll
need to move something into the processor specific part of the mips
port by requiring mips_cpu_ptrace or platform_cpu_ptrace be provided
by the ports to get/set processor specific registers, ala SSE
registers on x86.
r200342 | imp | 2009-12-09 18:42:44 -0700 (Wed, 09 Dec 2009) | 4 lines
app_descriptor_addr is unused (I know it is referened still). And
unnecessary since we pass in a3 unmodified to platform_start.
Eliminate it from here and kill one more TARGET_OCTEON in the process.
r199760 | imp | 2009-11-24 10:15:22 -0700 (Tue, 24 Nov 2009) | 2 lines
Add in Cavium's CID. Report what the unknown CID is.
r199755 | imp | 2009-11-24 09:53:58 -0700 (Tue, 24 Nov 2009) | 5 lines
looks like there's more to this patch than just this one file. I'll
leave it to neel@ to get all the relevant pieces into the tree.
r199754 | imp | 2009-11-24 09:32:31 -0700 (Tue, 24 Nov 2009) | 6 lines
Include opt_cputype.h for all .c and .S files referencing TARGET_OCTEON.
Spell ld script name right.
# for the most part, we need to enhance infrastructure to obviate the need
# for such an intrusive option.
r199753 | imp | 2009-11-24 09:30:29 -0700 (Tue, 24 Nov 2009) | 3 lines
Remove a comment that's bogus.
Include opt_cputype.h since TARGET_OCTEON moved there.
r199752 | imp | 2009-11-24 09:29:23 -0700 (Tue, 24 Nov 2009) | 4 lines
Make sure kstack0 is page aligned.
# this may have been from neel@ for the sibyte stuff
r199742 | imp | 2009-11-24 01:35:11 -0700 (Tue, 24 Nov 2009) | 8 lines
Move the hard-wiring of the dcache on octeon outside of the if
statement. When no caches support was added, it looks like
TARGET_OCTEON was bogusly moved inside the if. Also, include
opt_cputype.h to make TARGET_OCTEON actually active.
# now we die in pmap init somewhere... Most likely because 32MB of RAM is
# too tight given the load address we're using.
r199741 | imp | 2009-11-24 01:21:48 -0700 (Tue, 24 Nov 2009) | 2 lines
TARGET_OCTEON reqiures opt_cputype.h.
r199736 | imp | 2009-11-24 00:40:38 -0700 (Tue, 24 Nov 2009) | 2 lines
Prefer ANSI spellings of uintXX_t, etc.
r199598 | imp | 2009-11-20 09:30:35 -0700 (Fri, 20 Nov 2009) | 3 lines
Horrible kludge to make octeon32 work. I think a better way is to
move the generic code into the config files....
r199597 | imp | 2009-11-20 09:27:50 -0700 (Fri, 20 Nov 2009) | 4 lines
cast vaddr to uintptr_t before casting it to a bus_space_handle_t.
# I'm sure this indicates a problem, but I'm not sure what...
r199496 | gonzo | 2009-11-18 15:52:05 -0700 (Wed, 18 Nov 2009) | 5 lines
- Add cpu_init_interrupts function that is supposed to
prepeare stuff required for spinning out interrupts later
- Add API for managing intrcnt/intrnames arrays
- Some minor style(9) fixes
r199246 | neel | 2009-11-13 02:24:09 -0700 (Fri, 13 Nov 2009) | 10 lines
Make pmap_copy_page() L2-cache friendly by doing the copy through the
cacheable window on physical memory (KSEG0). On the Sibyte processor
going through the uncacheable window (KSEG1) bypasses both L1 and L2
caches so we may end up with stale contents in the L2 cache.
This also makes it consistent with the rest of the function that
uses cacheable mappings to copy pages.
Approved by: imp (mentor)
r198842 | gonzo | 2009-11-02 23:42:55 -0700 (Mon, 02 Nov 2009) | 3 lines
- Handle errors when adding children to nexus. This sittuation
might occure when there is dublicate of child's entry in hints
r198669 | rrs | 2009-10-30 02:53:11 -0600 (Fri, 30 Oct 2009) | 5 lines
With this commit our friend RMI will now compile. I have
not tested it and the chances of it running yet are about
ZERO.. but it will now compile. The hard part now begins,
making it run ;-)
r198569 | neel | 2009-10-28 23:18:02 -0600 (Wed, 28 Oct 2009) | 5 lines
Deal with overflow of the COUNT register correctly. The 'cycles_per_hz'
has nothing to do with the rollover.
r198550 | imp | 2009-10-28 11:03:20 -0600 (Wed, 28 Oct 2009) | 3 lines
Remove useless for statement. i isn't used after it.
Remove needless braces.
r198534 | gonzo | 2009-10-27 21:34:05 -0600 (Tue, 27 Oct 2009) | 8 lines
- Fix busdma sync: dcache invalidation operates on cache line aligned
addresses and could modify areas of memory that share the same cache
line at the beginning and at the ending of the buffer. In order to
prevent a data loss we save these chunks in temporary buffer before
invalidation and restore them afer it.
Idea suggested by: cognet
r198531 | gonzo | 2009-10-27 18:01:20 -0600 (Tue, 27 Oct 2009) | 3 lines
- Remove bunch of declared but not defined cach-related variables
- Add mips_picache_linesize and mips_pdcache_linesize variables
r198530 | gonzo | 2009-10-27 17:45:48 -0600 (Tue, 27 Oct 2009) | 3 lines
- Replace stubs with actual cache info
- minor style(9) fix
r198355 | neel | 2009-10-21 22:35:32 -0600 (Wed, 21 Oct 2009) | 11 lines
Remove redundant instructions from tlb.S
The "_MTC0 v0, COP_0_TLB_HI" is actually incorrect because v0 has not been
initialized at that point. It worked correctly because we subsequently
did the right thing and initialized TLB_HI correctly.
The "li v0, MIPS_KSEG0_START" is redundant because we do exactly the same
thing 2 instructions down.
r198354 | neel | 2009-10-21 20:51:31 -0600 (Wed, 21 Oct 2009) | 9 lines
Get rid of the hardcoded constants to define cacheable memory:
SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE
Instead we now keep a copy of the memory regions enumerated by
platform-specific code and use that to determine whether an address
is cacheable or not.
r198310 | gonzo | 2009-10-20 17:13:08 -0600 (Tue, 20 Oct 2009) | 5 lines
- Commit missing part of "bt" fix: store PC register in pcb_context struct
in cpu_switch and use it in stack_trace function later. pcb_regs contains
state of the process stored by exception handler and therefor is not
valid for sleeping processes.
r198264 | neel | 2009-10-19 22:36:08 -0600 (Mon, 19 Oct 2009) | 5 lines
Fix a bug where we would think that the L1 instruction and data cache are
present even though the line size field in the CP0 Config1 register is 0.
r198208 | imp | 2009-10-18 09:21:48 -0600 (Sun, 18 Oct 2009) | 3 lines
Get the PC from the trap frame, since it isn't saved as part of the
pcb regs.
r198205 | imp | 2009-10-18 08:55:55 -0600 (Sun, 18 Oct 2009) | 3 lines
Use correct signature for MipsEmulateBranch. The other one doesn't
work for 64-bit compiles.
r198182 | gonzo | 2009-10-16 18:22:07 -0600 (Fri, 16 Oct 2009) | 11 lines
- Use PC/RA/SP values as arguments for stacktrace_subr instead of trapframe.
Context info could be obtained from other sources (see below) no only from
td_pcb field
- Do not show a0..a3 values unless they're obtained from the stack. These
are only confirmed values.
- Fix bt command in DDB. Previous implementation used thread's trapframe
structure as a source info for trace unwinding, but this structure
is filled only when exception occurs. Valid register values for sleeping
processes are in pcb_context array. For curthread use pc/sp/ra for current
frame
r198181 | gonzo | 2009-10-16 16:52:18 -0600 (Fri, 16 Oct 2009) | 2 lines
- Get rid of label_t. It came from NetBSD and was used only in one place
r198066 | gonzo | 2009-10-13 19:43:53 -0600 (Tue, 13 Oct 2009) | 5 lines
- Move stack tracing function to db_trace.c
- Axe unused extern MipsXXX declarations
- Move all declarations for functions in exceptions.S/swtch.S
from trap.c to respective headers
r197796 | gonzo | 2009-10-05 17:19:51 -0600 (Mon, 05 Oct 2009) | 2 lines
- Revert part of r197685 because this change leads to wrong data in cache.
r197685 | gonzo | 2009-10-01 14:05:36 -0600 (Thu, 01 Oct 2009) | 2 lines
- Sync caches properly when dealing with sf_buf
r197014 | imp | 2009-09-08 21:57:10 -0600 (Tue, 08 Sep 2009) | 2 lines
Ugly hack to get this to compile. I'm sure there's a better way...
r197013 | imp | 2009-09-08 21:54:55 -0600 (Tue, 08 Sep 2009) | 2 lines
First half of making this 64-bit clean: fix prototypes.
r196988 | gonzo | 2009-09-08 13:15:29 -0600 (Tue, 08 Sep 2009) | 2 lines
- MFC from head@196987
r196313 | imp | 2009-08-17 06:14:40 -0600 (Mon, 17 Aug 2009) | 2 lines
suword64 and csuword64. Needed by ELF64 stuff...
r196266 | imp | 2009-08-15 16:51:11 -0600 (Sat, 15 Aug 2009) | 5 lines
(1) Fix a few 32/64-bit bugs.
(2) Also, always allocate 2 pages for the stack to optimize TLB usage.
Submitted by: neel@ (2)
r196265 | imp | 2009-08-15 16:48:09 -0600 (Sat, 15 Aug 2009) | 2 lines
Various 32/64-bit confusion cleanups.
r196264 | imp | 2009-08-15 16:45:46 -0600 (Sat, 15 Aug 2009) | 6 lines
(1) Some CPUs have a range to map I/O cyces on the pci bus. So allow
them to work by allowding the nexus to assign ports.
(2) Remove some Octeon junk that shouldn't be necessary.
Submitted by: neel@ (#1) for SB1 port.
r196061 | gonzo | 2009-08-04 11:32:55 -0600 (Tue, 04 Aug 2009) | 2 lines
- Use register_t for registers values
r195984 | gonzo | 2009-07-30 17:48:29 -0600 (Thu, 30 Jul 2009) | 4 lines
- Properly unwind stack for functions with __noreturn__ attribute
Submitted by: Neelkanth Natu <neelnatu@yahoo.com>
r195983 | gonzo | 2009-07-30 17:29:59 -0600 (Thu, 30 Jul 2009) | 4 lines
- mark map as coherent if requested by flags
- explicitly set memory allocation method in map flags instead
of duplicating conditions for malloc/contigalloc
r195584 | imp | 2009-07-10 13:09:34 -0600 (Fri, 10 Jul 2009) | 3 lines
Use PTR_* macros for pointers, and not potentially mips64 unsafe
operations.
r195583 | imp | 2009-07-10 13:08:48 -0600 (Fri, 10 Jul 2009) | 2 lines
Use PTR_* macros to deal with pointers.
r195579 | imp | 2009-07-10 13:04:32 -0600 (Fri, 10 Jul 2009) | 2 lines
use ta0-ta3 rather than t4-t7 for n32/n64 goodness.
r195511 | gonzo | 2009-07-09 13:02:17 -0600 (Thu, 09 Jul 2009) | 3 lines
- Ooops, this debug code wasn't supposed to get into
final commit. My appologises.
r195478 | gonzo | 2009-07-08 16:28:36 -0600 (Wed, 08 Jul 2009) | 5 lines
- Port busdma code from FreeBSD/arm. This is more mature version
that takes into account all limitation to DMA memory (boundaries,
alignment) and implements bounce pages.
- Add BUS_DMASYNC_POSTREAD case to bus_dmamap_sync_buf
r195438 | imp | 2009-07-08 00:00:18 -0600 (Wed, 08 Jul 2009) | 2 lines
Turns out this code was right, revert last change.
r195429 | gonzo | 2009-07-07 13:55:09 -0600 (Tue, 07 Jul 2009) | 5 lines
- Move dpcpu initialization to mips_proc0_init. It's
more appropriate place for it. Besides dpcpu_init
requires pmap module to be initialized and calling it
int pmap.c hangs the system
r195399 | imp | 2009-07-06 01:49:24 -0600 (Mon, 06 Jul 2009) | 2 lines
Prefer uintptr_t to int cast here.
r195398 | imp | 2009-07-06 01:48:31 -0600 (Mon, 06 Jul 2009) | 3 lines
Better types for 64-bit compatibility. Use %p and cast to void * and
prefer uintptr_t to other int-type casts.
r195397 | imp | 2009-07-06 01:47:39 -0600 (Mon, 06 Jul 2009) | 2 lines
No need to force mips32 here.
r195396 | imp | 2009-07-06 01:46:13 -0600 (Mon, 06 Jul 2009) | 3 lines
Pass in the uint64 value, rather than a pointer to it. that's what
the function expects...
r195395 | imp | 2009-07-06 01:45:02 -0600 (Mon, 06 Jul 2009) | 3 lines
Use ta0 instead of t4 and ta1 instead of t5. These map to the same
registers on O32 builds, but t4 and t5 don't exist on N32 or N64.
r195394 | imp | 2009-07-06 01:43:50 -0600 (Mon, 06 Jul 2009) | 3 lines
Use better casts for passing the small integer as a pointer here.
Basically, replace int with uintptr_t.
r195393 | imp | 2009-07-06 01:42:54 -0600 (Mon, 06 Jul 2009) | 5 lines
(1) Improvements for SB1. only allow real memory to be accessed.
(2) make compile n64 by using more-proper casts.
Submitted by: Neelkanth Natu (1)
r195373 | imp | 2009-07-05 09:23:54 -0600 (Sun, 05 Jul 2009) | 5 lines
(1) Use PTR_LA rather than bare la for N64 goodness (it is dla there)
(2) SB1 needs COHERENT policy, not cached for the config register
Submitted by: (2) Neelkanth Natu
r195372 | imp | 2009-07-05 09:22:22 -0600 (Sun, 05 Jul 2009) | 3 lines
use "PTR_LA" in preference to a bare la so it translates to dla on
64-bit ABIs.
r195371 | imp | 2009-07-05 09:21:35 -0600 (Sun, 05 Jul 2009) | 6 lines
Now that we define atomic_{load,store}_64 inline in atomic.h, we don't
need to define them here for the !N64 case.
We now define atomic_readandclear_64 in atomic.h, so no need to repeat
it here.
r195364 | imp | 2009-07-05 09:10:07 -0600 (Sun, 05 Jul 2009) | 5 lines
use %p in preference to 0x%08x for printing register_t values. Cast
them to void * first. This neatly solves the "how do I print a
register_t" problem because sizeof(void *) is always the same as
sizeof(register_t), afaik.
r195353 | imp | 2009-07-05 00:46:54 -0600 (Sun, 05 Jul 2009) | 6 lines
Publish PAGE_SHIFT to assembler
# we should likely phase out PGSHIFT
Submitted by: Neelkanth Natu
r195350 | imp | 2009-07-05 00:39:37 -0600 (Sun, 05 Jul 2009) | 7 lines
Switch to ABI agnostic ta0-ta3. Provide defs for this in the right
places. Provide n32/n64 register name defintions. This should have
no effect for the O32 builds that everybody else uses, but should help
make N64 builds possible (lots of other changes are needed for that).
Obtained from: NetBSD (for the regdef.h changes)
r195334 | imp | 2009-07-03 21:22:34 -0600 (Fri, 03 Jul 2009) | 6 lines
Move from using the lame invalid address I chose when trying to get
Octeon going... Turns out that you get tlb shutdowns with this...
Use PGSHIFT instead of PAGE_SHIFT.
Submitted by: Neelkanth Natu
r195147 | gonzo | 2009-06-28 15:01:00 -0600 (Sun, 28 Jun 2009) | 2 lines
- Replace casuword and casuword32 stubs with proper implementation
r195128 | gonzo | 2009-06-27 17:27:41 -0600 (Sat, 27 Jun 2009) | 4 lines
- Add support for handling TLS area address in kernel space.
From the userland point of view get/set operations are
performed using sysarch(2) call.
r195127 | gonzo | 2009-06-27 17:01:35 -0600 (Sat, 27 Jun 2009) | 4 lines
- Make cpu_set_upcall_kse conform MIPS ABI. T9 should be
the same as PC in subroutine entry point
- Preserve interrupt mask
r194938 | gonzo | 2009-06-24 20:15:04 -0600 (Wed, 24 Jun 2009) | 3 lines
- Invalidate cache in pmap_qenter. Fixes corruption of data
that comes through pipe (may be other bugs)
r194505 | gonzo | 2009-06-19 13:02:40 -0600 (Fri, 19 Jun 2009) | 5 lines
- Keep interrupts mask intact by RESTORE_CPU in MipsKernGenException
trap() function re-enables interrupts if exception happened with
interrupts enabled and therefor status register might be modified
by interrupt filters
r194277 | gonzo | 2009-06-15 20:36:21 -0600 (Mon, 15 Jun 2009) | 2 lines
- Remove debug printfs
r194275 | gonzo | 2009-06-15 19:43:33 -0600 (Mon, 15 Jun 2009) | 2 lines
- Handle KSEG0/KSEG1 addresses for /dev/mem as well. netstat requires it
r193491 | gonzo | 2009-06-05 03:21:03 -0600 (Fri, 05 Jun 2009) | 6 lines
- Status register should be set last in RESTORE_CPU in order
to prevent race over k0, k1 registers.
- Update interrupts mask in saved status register for
MipsUserIntr and MipsUserGenException. It might be
modified by intr filter or ithread.
r192864 | gonzo | 2009-05-26 16:40:12 -0600 (Tue, 26 May 2009) | 4 lines
- Replace CPU_NOFPU and SOFTFLOAT options with CPU_FPU. By default
we assume that there is no FPU, because majority of SoC does
not have it.
r192794 | gonzo | 2009-05-26 00:20:50 -0600 (Tue, 26 May 2009) | 5 lines
- Preserve INT_MASK fields in Status register across
context switches. They should be modified only by
interrupt setup/teardown and pre_ithread/post_ithread
functions
r192793 | gonzo | 2009-05-26 00:02:38 -0600 (Tue, 26 May 2009) | 2 lines
- Remove erroneus "break" instruction, it was meant for debug
r192792 | gonzo | 2009-05-26 00:01:17 -0600 (Tue, 26 May 2009) | 2 lines
- Remove now unused NetBSDism intr.h
r192791 | gonzo | 2009-05-25 23:59:05 -0600 (Mon, 25 May 2009) | 7 lines
- Provide proper pre_ithread/post_ithread functions for both
hard and soft interrupts
- Do not handle masked interrupts
- Do not write Cause register because most bytes are read-only and
writing the same byte to RW fields are pointless. And in case of
software interrupt utterly wrong
r192664 | gonzo | 2009-05-23 13:42:23 -0600 (Sat, 23 May 2009) | 4 lines
- cpu_establish_hardintr modifies INT_MASK of Status
register, so we should use disableintr/restoreintr that
modifies only IE bit.
r192655 | gonzo | 2009-05-23 12:00:20 -0600 (Sat, 23 May 2009) | 6 lines
- Remove stale comments
- Replace a1 with k1 to while restoring context. a1 was there by mistake,
interrupts are disabled at this point and it's safe to use k0, k1.
This code never was reached beacasue current Status register handling
prevented interrupta from user mode.
r192496 | gonzo | 2009-05-20 17:07:10 -0600 (Wed, 20 May 2009) | 4 lines
- Invalidate caches for respective areain KSEG0 in order
to prevent further overwriting of KSEG1 data with
writeback.
r192364 | gonzo | 2009-05-18 20:43:21 -0600 (Mon, 18 May 2009) | 6 lines
- Cleanup ticker initialization code. For some MIPS cpu Counter
register increments only every second cycle. The only timing
references for us is Count value. Therefore it's better to convert
frequencies related to it and use them. Besides cleanup this commit
fixes twice more then requested sleep interval problem.
r192176 | gonzo | 2009-05-15 20:34:03 -0600 (Fri, 15 May 2009) | 3 lines
- Add informational title for cache info lines to separate
them from environment variables dump
r192119 | gonzo | 2009-05-14 15:26:07 -0600 (Thu, 14 May 2009) | 3 lines
- Off by one check fix. Check for last address in region
to fit in KSEG1
r191841 | gonzo | 2009-05-05 20:55:43 -0600 (Tue, 05 May 2009) | 5 lines
- Use index ops in order to avoid TLBMiss exceptions when flushing caches
on mapping removal
- Writeback all VA for page that is being copied in pmap_copy_page to
guaranty up-to-date data in SDRAM
r191613 | gonzo | 2009-04-27 20:59:18 -0600 (Mon, 27 Apr 2009) | 4 lines
- When destroying va -> pa mapping writeback all caches or we may endup
with partial page content in SDRAM
- style(9) fix
r191583 | gonzo | 2009-04-27 12:46:57 -0600 (Mon, 27 Apr 2009) | 5 lines
- Use new spacebus
- Be a bit more verbose on failures
- style(9) fixes
- Use default rid value of 0 instead of MIPS_MEM_RID (0x20)
r191577 | gonzo | 2009-04-27 12:29:59 -0600 (Mon, 27 Apr 2009) | 4 lines
- Use naming convention the same as MIPS spec does: eliminate _sel1 sufix
and just use selector number. e.g. mips_rd_config_sel1 -> mips_rd_config1
- Add WatchHi/WatchLo accessors for selctors 1..3 (for debug purposes)
r191453 | gonzo | 2009-04-23 23:28:44 -0600 (Thu, 23 Apr 2009) | 4 lines
Fix cut'n'paste code. cfg3 should get the value of selector 3
Spotted by: thompa@
r191452 | gonzo | 2009-04-23 22:18:16 -0600 (Thu, 23 Apr 2009) | 2 lines
- Print supported CPU capabilities during stratup
r191448 | gonzo | 2009-04-23 21:38:51 -0600 (Thu, 23 Apr 2009) | 2 lines
- Fix whitespace to conform style(9)
r191282 | gonzo | 2009-04-19 16:02:14 -0600 (Sun, 19 Apr 2009) | 3 lines
- Make mips_bus_space_generic be of type bus_space_tag_t instead of
struct bus_space and update all relevant places.
r191084 | gonzo | 2009-04-14 20:28:26 -0600 (Tue, 14 Apr 2009) | 6 lines
Use FreeBSD/arm approach for handling bus space access: space tag is a pointer
to bus_space structure that defines access methods and hence every bus can
define own accessors. Default space is mips_bus_space_generic. It's a simple
interface to physical memory, values are read with regard to host system
byte order.
r191083 | gonzo | 2009-04-14 19:47:52 -0600 (Tue, 14 Apr 2009) | 4 lines
- Cleanout stale #ifdef'ed chunk of code
- Fix whitespaces
- Explicitly undefine NEXUS_DEBUG flag
r191079 | gonzo | 2009-04-14 16:53:22 -0600 (Tue, 14 Apr 2009) | 2 lines
- Revert changes accidentally killed by merge operation
------------------------------------------------------------------------
r187512 | gonzo | 2009-01-20 22:49:30 -0700 (Tue, 20 Jan 2009) | 4 lines
- Check if maddr/msize hints are there before setting hinted
resources to device
- Check for irq hint too
r187418 | gonzo | 2009-01-18 19:37:10 -0700 (Sun, 18 Jan 2009) | 4 lines
- Add trampoline stuff for bootloaders that do not support ELF
- Replace arm'ish KERNPHYSADDR/KERNVIRTADDR with
KERNLOADADDR/TRAMPLOADADDR and clean configs
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| .. | ||
| adm5120 | ||
| alchemy | ||
| atheros | ||
| cavium | ||
| compile | ||
| conf | ||
| idt | ||
| include | ||
| malta | ||
| mips | ||
| rmi | ||
| sentry5 | ||
| sibyte | ||