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compiler: Handle arm_aapcs16_vfp alongside arm_aapcs_vfp in some places.

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Alex Rønne Petersen 2024-10-28 20:24:41 +01:00
parent be8a527eb2
commit 3a5142af8d
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4 changed files with 20 additions and 9 deletions
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6
src/Zcu.zig
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@ -3615,12 +3615,16 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.builtin.CallingConvention) union(enu
.aarch64_vfabi,
.aarch64_vfabi_sve,
.arm_aapcs,
.arm_aapcs_vfp,
.riscv64_lp64_v,
.riscv32_ilp32_v,
.m68k_rtd,
=> |opts| opts.incoming_stack_alignment == null,
.arm_aapcs_vfp,
=> |opts| opts.incoming_stack_alignment == null and target.os.tag != .watchos,
.arm_aapcs16_vfp,
=> |opts| opts.incoming_stack_alignment == null and target.os.tag == .watchos,
.x86_sysv,
.x86_win,
.x86_stdcall,

2
src/codegen/c.zig
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@ -7623,7 +7623,7 @@ fn toCallingConvention(cc: std.builtin.CallingConvention, zcu: *Zcu) ?[]const u8
.aarch64_vfabi => "aarch64_vector_pcs",
.aarch64_vfabi_sve => "aarch64_sve_pcs",
.arm_aapcs => "pcs(\"aapcs\")",
.arm_aapcs_vfp => "pcs(\"aapcs-vfp\")",
.arm_aapcs_vfp, .arm_aapcs16_vfp => "pcs(\"aapcs-vfp\")",
.riscv64_lp64_v, .riscv32_ilp32_v => "riscv_vector_cc",
.m68k_rtd => "m68k_rtd",

16
src/codegen/llvm.zig
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@ -11747,7 +11747,14 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: std.Targ
.aarch64_vfabi_sve => .aarch64_sve_vector_pcs,
.arm_apcs => .arm_apcscc,
.arm_aapcs => .arm_aapcscc,
.arm_aapcs_vfp => .arm_aapcs_vfpcc,
.arm_aapcs_vfp => if (target.os.tag != .watchos)
.arm_aapcs_vfpcc
else
null,
.arm_aapcs16_vfp => if (target.os.tag == .watchos)
.arm_aapcs_vfpcc
else
null,
.riscv64_lp64_v => .riscv_vectorcallcc,
.riscv32_ilp32_v => .riscv_vectorcallcc,
.avr_builtin => .avr_builtincc,
@ -11777,7 +11784,6 @@ fn toLlvmCallConvTag(cc_tag: std.builtin.CallingConvention.Tag, target: std.Targ
.aarch64_aapcs,
.aarch64_aapcs_darwin,
.aarch64_aapcs_win,
.arm_aapcs16_vfp,
.mips64_n64,
.mips64_n32,
.mips_o32,
@ -11957,7 +11963,7 @@ fn firstParamSRet(fn_info: InternPool.Key.FuncType, zcu: *Zcu, target: std.Targe
.aarch64_aapcs_darwin,
.aarch64_aapcs_win,
=> aarch64_c_abi.classifyType(return_type, zcu) == .memory,
.arm_aapcs, .arm_aapcs_vfp => switch (arm_c_abi.classifyType(return_type, zcu, .ret)) {
.arm_aapcs, .arm_aapcs_vfp, .arm_aapcs16_vfp => switch (arm_c_abi.classifyType(return_type, zcu, .ret)) {
.memory, .i64_array => true,
.i32_array => |size| size != 1,
.byval => false,
@ -12007,7 +12013,7 @@ fn lowerFnRetTy(o: *Object, fn_info: InternPool.Key.FuncType) Allocator.Error!Bu
.integer => return o.builder.intType(@intCast(return_type.bitSize(zcu))),
.double_integer => return o.builder.arrayType(2, .i64),
},
.arm_aapcs, .arm_aapcs_vfp => switch (arm_c_abi.classifyType(return_type, zcu, .ret)) {
.arm_aapcs, .arm_aapcs_vfp, .arm_aapcs16_vfp => switch (arm_c_abi.classifyType(return_type, zcu, .ret)) {
.memory, .i64_array => return .void,
.i32_array => |len| return if (len == 1) .i32 else .void,
.byval => return o.lowerType(return_type),
@ -12256,7 +12262,7 @@ const ParamTypeIterator = struct {
.double_integer => return Lowering{ .i64_array = 2 },
}
},
.arm_aapcs, .arm_aapcs_vfp => {
.arm_aapcs, .arm_aapcs_vfp, .arm_aapcs16_vfp => {
it.zig_index += 1;
it.llvm_index += 1;
switch (arm_c_abi.classifyType(ty, zcu, .arg)) {

5
src/link/Dwarf.zig
View File

@ -3433,8 +3433,9 @@ fn updateType(
.arm_apcs => .nocall,
.arm_aapcs => .LLVM_AAPCS,
.arm_aapcs_vfp => .LLVM_AAPCS_VFP,
.arm_aapcs16_vfp => .nocall,
.arm_aapcs_vfp,
.arm_aapcs16_vfp,
=> .LLVM_AAPCS_VFP,
.riscv64_lp64_v,
.riscv32_ilp32_v,