mirror of
https://github.com/ziglang/zig.git
synced 2024-11-27 07:32:44 +00:00
zld: use aarch64 for opcodes
This commit is contained in:
Jakub Konka
parent
dc34ac2b9e
commit
d484b3b3cb
@ -221,7 +221,8 @@ pub const Instruction = union(enum) {
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offset: u12,
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opc: u2,
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op1: u2,
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fixed: u4 = 0b111_0,
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v: u1,
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fixed: u3 = 0b111,
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size: u2,
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},
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LoadStorePairOfRegisters: packed struct {
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@ -505,6 +506,7 @@ pub const Instruction = union(enum) {
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.offset = offset.toU12(),
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.opc = opc,
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.op1 = op1,
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.v = 0,
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.size = 0b10,
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},
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};
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@ -517,6 +519,7 @@ pub const Instruction = union(enum) {
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.offset = offset.toU12(),
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.opc = opc,
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.op1 = op1,
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.v = 0,
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.size = 0b11,
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},
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};
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@ -10,6 +10,7 @@ const fs = std.fs;
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const macho = std.macho;
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const math = std.math;
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const log = std.log.scoped(.zld);
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const aarch64 = @import("../../codegen/aarch64.zig");
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const Allocator = mem.Allocator;
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const CodeSignature = @import("CodeSignature.zig");
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@ -19,7 +20,6 @@ const Trie = @import("Trie.zig");
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usingnamespace @import("commands.zig");
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usingnamespace @import("bind.zig");
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usingnamespace @import("reloc.zig");
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allocator: *Allocator,
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@ -968,27 +968,27 @@ fn writeStubHelperCommon(self: *Zld) !void {
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data_blk: {
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const displacement = math.cast(i21, target_addr - this_addr) catch |_| break :data_blk;
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// adr x17, disp
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mem.writeIntLittle(u32, code[0..4], Arm64.adr(17, @bitCast(u21, displacement)).toU32());
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mem.writeIntLittle(u32, code[0..4], aarch64.Instruction.adr(.x17, displacement).toU32());
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// nop
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mem.writeIntLittle(u32, code[4..8], Arm64.nop().toU32());
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mem.writeIntLittle(u32, code[4..8], aarch64.Instruction.nop().toU32());
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break :data_blk_outer;
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}
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data_blk: {
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const new_this_addr = this_addr + @sizeOf(u32);
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const displacement = math.cast(i21, target_addr - new_this_addr) catch |_| break :data_blk;
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// nop
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mem.writeIntLittle(u32, code[0..4], Arm64.nop().toU32());
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mem.writeIntLittle(u32, code[0..4], aarch64.Instruction.nop().toU32());
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// adr x17, disp
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mem.writeIntLittle(u32, code[4..8], Arm64.adr(17, @bitCast(u21, displacement)).toU32());
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mem.writeIntLittle(u32, code[4..8], aarch64.Instruction.adr(.x17, displacement).toU32());
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break :data_blk_outer;
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}
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// Jump is too big, replace adr with adrp and add.
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const this_page = @intCast(i32, this_addr >> 12);
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const target_page = @intCast(i32, target_addr >> 12);
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const pages = @bitCast(u21, @intCast(i21, target_page - this_page));
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mem.writeIntLittle(u32, code[0..4], Arm64.adrp(17, pages).toU32());
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const pages = @intCast(i21, target_page - this_page);
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mem.writeIntLittle(u32, code[0..4], aarch64.Instruction.adrp(.x17, pages).toU32());
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const narrowed = @truncate(u12, target_addr);
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mem.writeIntLittle(u32, code[4..8], Arm64.add(17, 17, narrowed, 1).toU32());
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mem.writeIntLittle(u32, code[4..8], aarch64.Instruction.add(.x17, .x17, narrowed, false).toU32());
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}
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// stp x16, x17, [sp, #-16]!
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code[8] = 0xf0;
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@ -1003,9 +1003,11 @@ fn writeStubHelperCommon(self: *Zld) !void {
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const displacement = math.divExact(u64, target_addr - this_addr, 4) catch |_| break :binder_blk;
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const literal = math.cast(u18, displacement) catch |_| break :binder_blk;
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// ldr x16, label
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mem.writeIntLittle(u32, code[12..16], Arm64.ldr(16, literal, 1).toU32());
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mem.writeIntLittle(u32, code[12..16], aarch64.Instruction.ldr(.x16, .{
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.literal = literal,
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}).toU32());
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// nop
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mem.writeIntLittle(u32, code[16..20], Arm64.nop().toU32());
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mem.writeIntLittle(u32, code[16..20], aarch64.Instruction.nop().toU32());
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break :binder_blk_outer;
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}
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binder_blk: {
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@ -1015,19 +1017,26 @@ fn writeStubHelperCommon(self: *Zld) !void {
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log.debug("2: disp=0x{x}, literal=0x{x}", .{ displacement, literal });
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// Pad with nop to please division.
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// nop
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mem.writeIntLittle(u32, code[12..16], Arm64.nop().toU32());
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mem.writeIntLittle(u32, code[12..16], aarch64.Instruction.nop().toU32());
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// ldr x16, label
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mem.writeIntLittle(u32, code[16..20], Arm64.ldr(16, literal, 1).toU32());
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mem.writeIntLittle(u32, code[16..20], aarch64.Instruction.ldr(.x16, .{
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.literal = literal,
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}).toU32());
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break :binder_blk_outer;
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}
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// Use adrp followed by ldr(immediate).
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const this_page = @intCast(i32, this_addr >> 12);
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const target_page = @intCast(i32, target_addr >> 12);
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const pages = @bitCast(u21, @intCast(i21, target_page - this_page));
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mem.writeIntLittle(u32, code[12..16], Arm64.adrp(16, pages).toU32());
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const pages = @intCast(i21, target_page - this_page);
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mem.writeIntLittle(u32, code[12..16], aarch64.Instruction.adrp(.x16, pages).toU32());
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const narrowed = @truncate(u12, target_addr);
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const offset = try math.divExact(u12, narrowed, 8);
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mem.writeIntLittle(u32, code[16..20], Arm64.ldrq(16, 16, offset).toU32());
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mem.writeIntLittle(u32, code[16..20], aarch64.Instruction.ldr(.x16, .{
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.register = .{
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.rn = .x16,
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.offset = aarch64.Instruction.LoadStoreOffset.imm(offset),
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},
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}).toU32());
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}
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// br x16
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code[20] = 0x00;
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@ -1099,9 +1108,11 @@ fn writeStub(self: *Zld, index: u32) !void {
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const displacement = math.divExact(u64, target_addr - this_addr, 4) catch |_| break :inner;
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const literal = math.cast(u18, displacement) catch |_| break :inner;
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// ldr x16, literal
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mem.writeIntLittle(u32, code[0..4], Arm64.ldr(16, literal, 1).toU32());
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mem.writeIntLittle(u32, code[0..4], aarch64.Instruction.ldr(.x16, .{
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.literal = literal,
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}).toU32());
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// nop
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mem.writeIntLittle(u32, code[4..8], Arm64.nop().toU32());
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mem.writeIntLittle(u32, code[4..8], aarch64.Instruction.nop().toU32());
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break :outer;
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}
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inner: {
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@ -1109,22 +1120,29 @@ fn writeStub(self: *Zld, index: u32) !void {
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const displacement = math.divExact(u64, target_addr - new_this_addr, 4) catch |_| break :inner;
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const literal = math.cast(u18, displacement) catch |_| break :inner;
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// nop
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mem.writeIntLittle(u32, code[0..4], Arm64.nop().toU32());
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mem.writeIntLittle(u32, code[0..4], aarch64.Instruction.nop().toU32());
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// ldr x16, literal
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mem.writeIntLittle(u32, code[4..8], Arm64.ldr(16, literal, 1).toU32());
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mem.writeIntLittle(u32, code[4..8], aarch64.Instruction.ldr(.x16, .{
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.literal = literal,
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}).toU32());
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break :outer;
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}
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// Use adrp followed by ldr(immediate).
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const this_page = @intCast(i32, this_addr >> 12);
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const target_page = @intCast(i32, target_addr >> 12);
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const pages = @bitCast(u21, @intCast(i21, target_page - this_page));
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mem.writeIntLittle(u32, code[0..4], Arm64.adrp(16, pages).toU32());
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const pages = @intCast(i21, target_page - this_page);
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mem.writeIntLittle(u32, code[0..4], aarch64.Instruction.adrp(.x16, pages).toU32());
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const narrowed = @truncate(u12, target_addr);
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const offset = try math.divExact(u12, narrowed, 8);
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mem.writeIntLittle(u32, code[4..8], Arm64.ldrq(16, 16, offset).toU32());
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mem.writeIntLittle(u32, code[4..8], aarch64.Instruction.ldr(.x16, .{
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.register = .{
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.rn = .x16,
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.offset = aarch64.Instruction.LoadStoreOffset.imm(offset),
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},
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}).toU32());
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}
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// br x16
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mem.writeIntLittle(u32, code[8..12], Arm64.br(16).toU32());
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mem.writeIntLittle(u32, code[8..12], aarch64.Instruction.br(.x16).toU32());
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},
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else => unreachable,
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}
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@ -1160,9 +1178,11 @@ fn writeStubInStubHelper(self: *Zld, index: u32) !void {
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const displacement = try math.cast(i28, @intCast(i64, stub_helper.offset) - @intCast(i64, stub_off) - 4);
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const literal = @divExact(stub_size - @sizeOf(u32), 4);
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// ldr w16, literal
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mem.writeIntLittle(u32, code[0..4], Arm64.ldr(16, literal, 0).toU32());
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mem.writeIntLittle(u32, code[0..4], aarch64.Instruction.ldr(.w16, .{
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.literal = literal,
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}).toU32());
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// b disp
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mem.writeIntLittle(u32, code[4..8], Arm64.b(displacement).toU32());
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mem.writeIntLittle(u32, code[4..8], aarch64.Instruction.b(displacement).toU32());
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mem.writeIntLittle(u32, code[8..12], 0x0); // Just a placeholder populated in `populateLazyBindOffsetsInStubHelper`.
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},
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else => unreachable,
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@ -1486,9 +1506,18 @@ fn doRelocs(self: *Zld) !void {
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.ARM64_RELOC_BRANCH26 => {
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assert(rel.r_length == 2);
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const inst = code[off..][0..4];
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const displacement = @intCast(i28, @intCast(i64, target_addr) - @intCast(i64, this_addr));
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var parsed = mem.bytesAsValue(meta.TagPayload(Arm64, Arm64.Branch), inst);
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parsed.disp = @truncate(u26, @bitCast(u28, displacement) >> 2);
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const displacement = @intCast(
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i28,
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@intCast(i64, target_addr) - @intCast(i64, this_addr),
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);
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var parsed = mem.bytesAsValue(
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meta.TagPayload(
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aarch64.Instruction,
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aarch64.Instruction.UnconditionalBranchImmediate,
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),
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inst,
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);
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parsed.imm26 = @truncate(u26, @bitCast(u28, displacement) >> 2);
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},
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.ARM64_RELOC_PAGE21,
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.ARM64_RELOC_GOT_LOAD_PAGE21,
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@ -1501,7 +1530,13 @@ fn doRelocs(self: *Zld) !void {
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const target_page = @intCast(i32, ta >> 12);
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const pages = @bitCast(u21, @intCast(i21, target_page - this_page));
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log.debug(" | moving by {} pages", .{pages});
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var parsed = mem.bytesAsValue(meta.TagPayload(Arm64, Arm64.Address), inst);
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var parsed = mem.bytesAsValue(
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meta.TagPayload(
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aarch64.Instruction,
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aarch64.Instruction.PCRelativeAddress,
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),
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inst,
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);
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parsed.immhi = @truncate(u19, pages >> 2);
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parsed.immlo = @truncate(u2, pages);
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addend = null;
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@ -1510,17 +1545,29 @@ fn doRelocs(self: *Zld) !void {
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.ARM64_RELOC_GOT_LOAD_PAGEOFF12,
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=> {
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const inst = code[off..][0..4];
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if (Arm64.isArithmetic(inst)) {
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if (aarch64IsArithmetic(inst)) {
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log.debug(" | detected ADD opcode", .{});
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// add
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var parsed = mem.bytesAsValue(meta.TagPayload(Arm64, Arm64.Add), inst);
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var parsed = mem.bytesAsValue(
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meta.TagPayload(
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aarch64.Instruction,
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aarch64.Instruction.AddSubtractImmediate,
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),
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inst,
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);
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const ta = if (addend) |a| target_addr + a else target_addr;
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const narrowed = @truncate(u12, ta);
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parsed.offset = narrowed;
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parsed.imm12 = narrowed;
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} else {
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log.debug(" | detected LDR/STR opcode", .{});
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// ldr/str
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var parsed = mem.bytesAsValue(meta.TagPayload(Arm64, Arm64.LoadRegister), inst);
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var parsed = mem.bytesAsValue(
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meta.TagPayload(
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aarch64.Instruction,
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aarch64.Instruction.LoadStoreRegister,
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),
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inst,
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);
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const ta = if (addend) |a| target_addr + a else target_addr;
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const narrowed = @truncate(u12, ta);
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const offset: u12 = blk: {
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@ -1541,27 +1588,43 @@ fn doRelocs(self: *Zld) !void {
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addend = null;
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},
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.ARM64_RELOC_TLVP_LOAD_PAGEOFF12 => {
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// TODO why is this necessary?
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const RegInfo = struct {
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rt: u5,
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rd: u5,
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rn: u5,
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size: u1,
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};
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const inst = code[off..][0..4];
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const parsed: RegInfo = blk: {
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if (Arm64.isArithmetic(inst)) {
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const curr = mem.bytesAsValue(meta.TagPayload(Arm64, Arm64.Add), inst);
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break :blk .{ .rt = curr.rt, .rn = curr.rn, .size = curr.size };
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if (aarch64IsArithmetic(inst)) {
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const curr = mem.bytesAsValue(
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meta.TagPayload(
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aarch64.Instruction,
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aarch64.Instruction.AddSubtractImmediate,
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),
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inst,
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);
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break :blk .{ .rd = curr.rd, .rn = curr.rn, .size = curr.sf };
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} else {
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const curr = mem.bytesAsValue(meta.TagPayload(Arm64, Arm64.LoadRegister), inst);
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break :blk .{ .rt = curr.rt, .rn = curr.rn, .size = @truncate(u1, curr.size) };
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const curr = mem.bytesAsValue(
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meta.TagPayload(
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aarch64.Instruction,
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aarch64.Instruction.LoadStoreRegister,
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),
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inst,
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);
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break :blk .{ .rd = curr.rt, .rn = curr.rn, .size = @truncate(u1, curr.size) };
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}
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};
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const ta = if (addend) |a| target_addr + a else target_addr;
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const narrowed = @truncate(u12, ta);
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log.debug(" | rewriting TLV access to ADD opcode", .{});
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// For TLV, we always generate an add instruction.
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mem.writeIntLittle(u32, inst, Arm64.add(parsed.rt, parsed.rn, narrowed, parsed.size).toU32());
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mem.writeIntLittle(u32, inst, aarch64.Instruction.add(
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@intToEnum(aarch64.Register, parsed.rd),
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@intToEnum(aarch64.Register, parsed.rn),
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narrowed,
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false,
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).toU32());
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},
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.ARM64_RELOC_SUBTRACTOR => {
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sub = @intCast(i64, target_addr);
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@ -2965,3 +3028,8 @@ fn isExtern(sym: *const macho.nlist_64) callconv(.Inline) bool {
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fn isWeakDef(sym: *const macho.nlist_64) callconv(.Inline) bool {
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return (sym.n_desc & macho.N_WEAK_DEF) != 0;
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}
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fn aarch64IsArithmetic(inst: *const [4]u8) callconv(.Inline) bool {
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const group_decode = @truncate(u5, inst[3]);
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return ((group_decode >> 2) == 4);
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}
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@ -1,197 +0,0 @@
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const std = @import("std");
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const log = std.log.scoped(.reloc);
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pub const Arm64 = union(enum) {
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Branch: packed struct {
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disp: u26,
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fixed: u5 = 0b00101,
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link: u1,
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},
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BranchRegister: packed struct {
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_1: u5 = 0b0000_0,
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reg: u5,
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_2: u11 = 0b1111_1000_000,
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link: u1,
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_3: u10 = 0b1101_0110_00,
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},
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Address: packed struct {
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reg: u5,
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immhi: u19,
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_1: u5 = 0b10000,
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immlo: u2,
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page: u1,
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},
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LoadRegister: packed struct {
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rt: u5,
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rn: u5,
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offset: u12,
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opc: u2,
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_2: u2 = 0b01,
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v: u1,
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_1: u3 = 0b111,
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size: u2,
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},
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LoadLiteral: packed struct {
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reg: u5,
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literal: u19,
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_1: u6 = 0b011_0_00,
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size: u1,
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_2: u1 = 0b0,
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},
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Add: packed struct {
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rt: u5,
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rn: u5,
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offset: u12,
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_1: u9 = 0b0_0_100010_0,
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size: u1,
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},
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Nop: packed struct {
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fixed: u32 = 0b1101010100_0_00_011_0010_0000_000_11111,
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},
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pub fn toU32(self: Arm64) u32 {
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const as_u32 = switch (self) {
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.Branch => |x| @bitCast(u32, x),
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.BranchRegister => |x| @bitCast(u32, x),
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.Address => |x| @bitCast(u32, x),
|
||||
.LoadRegister => |x| @bitCast(u32, x),
|
||||
.LoadLiteral => |x| @bitCast(u32, x),
|
||||
.Add => |x| @bitCast(u32, x),
|
||||
.Nop => |x| @bitCast(u32, x),
|
||||
};
|
||||
return as_u32;
|
||||
}
|
||||
|
||||
pub fn b(disp: i28) Arm64 {
|
||||
return Arm64{
|
||||
.Branch = .{
|
||||
.disp = @truncate(u26, @bitCast(u28, disp) >> 2),
|
||||
.link = 0,
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
pub fn bl(disp: i28) Arm64 {
|
||||
return Arm64{
|
||||
.Branch = .{
|
||||
.disp = @truncate(u26, @bitCast(u28, disp) >> 2),
|
||||
.link = 1,
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
pub fn br(reg: u5) Arm64 {
|
||||
return Arm64{
|
||||
.BranchRegister = .{
|
||||
.reg = reg,
|
||||
.link = 0,
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
pub fn blr(reg: u5) Arm64 {
|
||||
return Arm64{
|
||||
.BranchRegister = .{
|
||||
.reg = reg,
|
||||
.link = 1,
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
pub fn adr(reg: u5, disp: u21) Arm64 {
|
||||
return Arm64{
|
||||
.Address = .{
|
||||
.reg = reg,
|
||||
.immhi = @truncate(u19, disp >> 2),
|
||||
.immlo = @truncate(u2, disp),
|
||||
.page = 0,
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
pub fn adrp(reg: u5, disp: u21) Arm64 {
|
||||
return Arm64{
|
||||
.Address = .{
|
||||
.reg = reg,
|
||||
.immhi = @truncate(u19, disp >> 2),
|
||||
.immlo = @truncate(u2, disp),
|
||||
.page = 1,
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
pub fn ldr(reg: u5, literal: u19, size: u1) Arm64 {
|
||||
return Arm64{
|
||||
.LoadLiteral = .{
|
||||
.reg = reg,
|
||||
.literal = literal,
|
||||
.size = size,
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
pub fn add(rt: u5, rn: u5, offset: u12, size: u1) Arm64 {
|
||||
return Arm64{
|
||||
.Add = .{
|
||||
.rt = rt,
|
||||
.rn = rn,
|
||||
.offset = offset,
|
||||
.size = size,
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
pub fn ldrq(rt: u5, rn: u5, offset: u12) Arm64 {
|
||||
return Arm64{
|
||||
.LoadRegister = .{
|
||||
.rt = rt,
|
||||
.rn = rn,
|
||||
.offset = offset,
|
||||
.opc = 0b01,
|
||||
.v = 0b0,
|
||||
.size = 0b11,
|
||||
},
|
||||
};
|
||||
}
|
||||
pub fn ldrh(rt: u5, rn: u5, offset: u12) Arm64 {
|
||||
return Arm64{
|
||||
.LoadRegister = .{
|
||||
.rt = rt,
|
||||
.rn = rn,
|
||||
.offset = offset,
|
||||
.opc = 0b01,
|
||||
.v = 0b0,
|
||||
.size = 0b01,
|
||||
},
|
||||
};
|
||||
}
|
||||
pub fn ldrb(rt: u5, rn: u5, offset: u12) Arm64 {
|
||||
return Arm64{
|
||||
.LoadRegister = .{
|
||||
.rt = rt,
|
||||
.rn = rn,
|
||||
.offset = offset,
|
||||
.opc = 0b01,
|
||||
.v = 0b0,
|
||||
.size = 0b00,
|
||||
},
|
||||
};
|
||||
}
|
||||
|
||||
pub fn nop() Arm64 {
|
||||
return Arm64{
|
||||
.Nop = .{},
|
||||
};
|
||||
}
|
||||
|
||||
pub fn isArithmetic(inst: *const [4]u8) bool {
|
||||
const group_decode = @truncate(u5, inst[3]);
|
||||
log.debug("{b}", .{group_decode});
|
||||
return ((group_decode >> 2) == 4);
|
||||
// if ((group_decode >> 2) == 4) {
|
||||
// log.debug("Arithmetic imm", .{});
|
||||
// } else if (((group_decode & 0b01010) >> 3) == 1) {
|
||||
// log.debug("Load/store", .{});
|
||||
// }
|
||||
}
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user