PAGE_SIZE to (2 * PAGE_SIZE). It depends on the memory allocated by
pmap_steal_memory() being aligned to a PAGE_SIZE boundary.
Approved by: imp (mentor)
This replaces d_mmap() with the d_mmap2() implementation and also
changes the type of offset to vm_ooffset_t.
Purge d_mmap2().
All driver modules will need to be rebuilt since D_VERSION is also
bumped.
Reviewed by: jhb@
MFC after: Not in this lifetime...
here yet, so I've not connected it to the build. I think that we'll
need to move something into the processor specific part of the mips
port by requiring mips_cpu_ptrace or platform_cpu_ptrace be provided
by the ports to get/set processor specific registers, ala SSE
registers on x86.
statement. When no caches support was added, it looks like
TARGET_OCTEON was bogusly moved inside the if. Also, include
opt_cputype.h to make TARGET_OCTEON actually active.
# now we die in pmap init somewhere... Most likely because 32MB of RAM is
# too tight given the load address we're using.
o Introduce a uart bus space so that we don't have to hack dev/uart to do 8
byte reads. This also handles the shift properly, so reset the shift we
want dev/uart doing to 0. In effect, this bus space makes the octeon
registers have an interface to dev/uart that looks just like the old ISA
bus, but does the necessary 64-bit read/write to the bus. We only support
read/write operations. We do all the widths, but likely could get away
with only 64-bit and 8-bit given the restricted nature of use of this bus.
o use bus_space_map to set the .bsh rather than a direct assignment.
o Minor cleanup of uart_cpu_getdev to make it conform more to the other
implementations.
o Add some coments for future work.
# with these changes, we now make it through cninit, but there's still some
# problem that's preventing output, as well as another problem that causes
# us to call panic just after we return from cninit() in platform_start.
cacheable window on physical memory (KSEG0). On the Sibyte processor
going through the uncacheable window (KSEG1) bypasses both L1 and L2
caches so we may end up with stale contents in the L2 cache.
This also makes it consistent with the rest of the function that
uses cacheable mappings to copy pages.
Approved by: imp (mentor)
fixed-state media with parameters set via hints
and configure MAC accordingly to these parameters.
All the underlying PHY magic is done by boot manager
on startup. At the moment there is no proper way
to make active and control all PHYs simultaneously
from one MII bus and there is no way to associate
incoming/outgoing packet with specific PHY.
original codes (I had changed one by accident)
Also do the pic_ack/pic_delayed_ack after the interrupt
so we clear it. The clock with these changes starts working.
Its off doing a short/long short/long warning but it
now runs.
My NFS mount now works but has the same problem with
sbin/init (errno 8 ENOEXEC) so it panics with no init.
Either this is a problem with my buildworld.. OR its a
yet undiscovered RMI issue.
- Move dpcpu initialization to mips_proc0_init. It's
more appropriate place for it. Besides dpcpu_init
requires pmap module to be initialized and calling it
int pmap.c hangs the system
the mi_startup (or to the last of it).. and
hit a panic after :
uart0: <16550 or compatible> on iodi0
Trap cause = 2 (TLB miss....)
I did have to take the pci bus OUT of the
build to get this far, hit a cache error with
the PCI code in. Interesting thing is the machine
reboots too ;-)
addresses and could modify areas of memory that share the same cache
line at the beginning and at the ending of the buffer. In order to
prevent a data loss we save these chunks in temporary buffer before
invalidation and restore them afer it.
Idea suggested by: cognet
while in kernel mode, and later changing signal mask to block the
signal, was fixed for sigprocmask(2) and ptread_exit(3). The same race
exists for sigreturn(2), setcontext(2) and swapcontext(2) syscalls.
Use kern_sigprocmask() instead of direct manipulation of td_sigmask to
reschedule newly blocked signals, closing the race.
Reviewed by: davidxu
Tested by: pho
MFC after: 1 month
The "_MTC0 v0, COP_0_TLB_HI" is actually incorrect because v0 has not been
initialized at that point. It worked correctly because we subsequently
did the right thing and initialized TLB_HI correctly.
The "li v0, MIPS_KSEG0_START" is redundant because we do exactly the same
thing 2 instructions down.
Approved by: imp (mentor)
SDRAM_ADDR_START, SDRAM_ADDR_END and SDRAM_MEM_SIZE
Instead we now keep a copy of the memory regions enumerated by
platform-specific code and use that to determine whether an address
is cacheable or not.
Approved by: imp (mentor)
the memory or D-cache, depending on the semantics of the platform.
vm_sync_icache() is basically a wrapper around pmap_sync_icache(),
that translates the vm_map_t argumument to pmap_t.
o Introduce pmap_sync_icache() to all PMAP implementation. For powerpc
it replaces the pmap_page_executable() function, added to solve
the I-cache problem in uiomove_fromphys().
o In proc_rwmem() call vm_sync_icache() when writing to a page that
has execute permissions. This assures that when breakpoints are
written, the I-cache will be coherent and the process will actually
hit the breakpoint.
o This also fixes the Book-E PMAP implementation that was missing
necessary locking while trying to deal with the I-cache coherency
in pmap_enter() (read: mmu_booke_enter_locked).
The key property of this change is that the I-cache is made coherent
*after* writes have been done. Doing it in the PMAP layer when adding
or changing a mapping means that the I-cache is made coherent *before*
any writes happen. The difference is key when the I-cache prefetches.
in cpu_switch and use it in stack_trace function later. pcb_regs contains
state of the process stored by exception handler and therefor is not
valid for sleeping processes.
